KR101469343B1 - Vertical power mosfet and methods of forming the same - Google Patents

Vertical power mosfet and methods of forming the same Download PDF

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KR101469343B1
KR101469343B1 KR1020130009281A KR20130009281A KR101469343B1 KR 101469343 B1 KR101469343 B1 KR 101469343B1 KR 1020130009281 A KR1020130009281 A KR 1020130009281A KR 20130009281 A KR20130009281 A KR 20130009281A KR 101469343 B1 KR101469343 B1 KR 101469343B1
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semiconductor
layer
gate
gate electrode
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KR20140001087A (en
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천-와이 응
수에-리앙 초우
포-치 수
뤠이-신 리우
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Priority claimed from US13/483,633 external-priority patent/US8918608B2/en
Priority claimed from US13/588,893 external-priority patent/US9087920B2/en
Application filed by 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 filed Critical 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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Abstract

The device includes a first conductive semiconductor layer and first and second body regions over the semiconductor layer, wherein the first and second body regions have a second conductivity type opposite to the first conductivity type. A doped semiconductor region of a first conductivity type is disposed between the first body region and the second body region to contact the first and second body regions. A gate dielectric layer is disposed over the doped semiconductor regions with the first and second body regions. First and second gate electrodes are disposed over the gate dielectric layer and overlie the first and second body regions, respectively. The first and second gate electrodes are physically separated from each other by a space and are electrically interconnected. The space between the first gate electrode and the second gate electrode overlaps the doped semiconductor region. The device also includes a MOS-containing device.

Description

TECHNICAL FIELD [0001] The present invention relates to a vertical power MOSFET and a method of manufacturing the same.

This application is a continuation-in-part of U.S. Patent Application No. 13 / 483,633, filed June 1, 1012 entitled " Vertical Power MOSFET and Method of Manufacturing the Same " .

In a conventional vertical power metal oxide semiconductor field effect transistor (MOSFET), two p-body regions are formed in the n-type epitaxial region. Vertical power MOSFETs are so named because their source and drain regions overlap. The portion of the epitaxial region between the two p-body regions is lightly doped to form an n-type doped region, which is sometimes referred to as an n-type junction field effect transistor (n-JFET) region. The p-body region and the n-JFET region are under the gate dielectric and the gate electrode. When a positive voltage is applied to the gate, a reverse region of electrons is formed in the p-body region. The inversion region acts as a channel region connecting the source region of the vertical power MOSFET to the n-JFET region and the n-JFET region is also connected to the drain region of the power MOSFET through the n-type epitaxial region. Thus, the source-drain current is conducted from the source region to the channel of the p-body region, the n-JFET region, the epitaxial region, and then the drain region.

An n-JFET region is disposed under the gate electrode, and a gate dielectric layer is disposed between the n-JFET region and the gate electrode. There is a large overlap region between the gate electrode and the n-JFET region. As a result, there are significant gate-drain capacitances, which adversely affects performance, including the speed of the vertical MOSFET. Also, the n-JFET region is lightly doped because it is part of the n-type epitaxial region. Therefore, the resistance of the n-JFET region is high, which adversely affects the driving current of the vertical power MOSFET.

The device includes a first conductive semiconductor layer and first and second body regions over the semiconductor layer, wherein the first and second body regions have a second conductivity type opposite to the first conductivity type. A doped semiconductor region of a first conductivity type is disposed between the first body region and the second body region to contact the first and second body regions. A gate dielectric layer is disposed over the doped semiconductor regions with the first and second body regions. First and second gate electrodes are disposed over the gate dielectric layer and overlie the first and second body regions, respectively. The first and second gate electrodes are physically separated from each other by a space and are electrically interconnected. The space between the first gate electrode and the second gate electrode overlaps the doped semiconductor region. The device also includes a MOS-containing device.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the embodiments and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: FIG.
1A-1F are cross-sectional views of intermediate steps in the fabrication of a vertical power metal oxide semiconductor field effect transistor (MOSFET) in accordance with some exemplary embodiments.
Figures 2A-2C are cross-sectional views of intermediate steps in the fabrication of a vertical power MOSFET according to an alternative embodiment.
Figures 3A-5F are cross-sectional views of intermediate steps incorporating the formation of various MOS devices.

The construction and use of various embodiments of the present invention will be described in detail below. It should be understood, however, that these embodiments provide many applicable inventive concepts that may be realized in various specific contexts. The particular embodiments described herein are illustrative only and are not intended to limit the scope of the invention.

A vertical power metal oxide semiconductor field effect transistor (MOSFET) and a method of manufacturing the same are provided according to various exemplary embodiments. Intermediate steps for fabricating a vertical power MOSFET are illustrated. Modifications of the embodiment are described. In the various drawings and the illustrative embodiments, the same reference numerals are used to denote the same elements.

Figures 1A-1F are cross-sectional views of intermediate steps in the fabrication of an n-type vertical power MOSFET. Referring to FIG. 1A, a semiconductor region 20 is provided that is a part of a semiconductor substrate. The semiconductor region 20 and each semiconductor substrate may have a crystalline silicon structure. Alternatively, the semiconductor region 20 and each semiconductor substrate may be formed from other semiconductor materials such as silicon germanium. The semiconductor substrate may be a bulk substrate. In some embodiments, the semiconductor region 20 is formed by an n-type impurity such as phosphorus or arsenic, for example, a heavily doped layer doped with an impurity concentration between about 10 19 / cm 3 and about 10 21 / cm 3 to be. In the embodiment described herein, the term "rich doping " means an impurity concentration of at least about 10 19 / cm 3. However, those skilled in the art will recognize that dense doping is a technical term depending on the particular device type, technology generation, minimum feature size, and the like. Therefore, this term is intended to be construed in light of the technology being evaluated and not to be limited to the embodiments described herein.

Over the heavily doped semiconductor region 20, an epitaxial layer 22 is formed through epitaxy and is lightly doped with n-type impurities. The impurity concentration of the epitaxial layer 22 may be between about 10 15 / cm 3 and about 10 18 / cm 3. The epitaxial layer 22 may be a silicon layer and other semiconductor materials may be used.

A body layer 26 is then formed. The body layer 26 is of a p-type, and hence will be referred to as a p-body 26 hereinafter. In some embodiments, the p-body 26 is formed by implanting an upper portion of the epitaxial layer 22 with a p-type impurity such as boron and / or indium, wherein the lower portion of the epitaxial layer 22 is implanted And remains in the n-type. The p-type impurity concentration of the p-body 26 may be between about 10 15 / cm 3 and about 10 18 / cm 3. implanting the p-body 26 may include oxidizing the surface layer of the epitaxial layer 22 to form a pad oxide layer (not shown) and forming a pad oxide layer Implanting p-type impurities through the pad oxide layer, and removing the pad oxide layer. In an alternative embodiment, the p-body 26 epitaxially grows a semiconductor layer (e.g., a silicon layer) over the epitaxial layer 22 and epitaxially grows the p- Type dopant in-situ.

Next, as shown in FIG. 1B, a gate oxide layer 28 is formed. In some embodiments, the forming process includes thermal oxidation of the surface layer of the p-body 26. Thus, the gate oxide layer 28 comprises silicon oxide. In an alternative embodiment, a gate oxide layer 28 is formed through deposition. The corresponding gate oxide layer 28 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and multiple layers thereof.

1B also shows the formation of the gate electrode 30 (including 30A and 30B). The forming process may include blanket deposition of the conductive material and then patterning of the conductive material. In some embodiments, the gate electrodes 30A and 30B comprise polysilicon, but other conductive materials such as metals, metal suicides, etc. may also be used. The gate electrodes 30A and 30B are spaced apart from each other by a space 29. [ The spacing S1 between the gate electrodes 30A and 30B may be between about 100 nm and about 10 mu m in some embodiments. The values recited throughout this specification are to be understood as merely illustrative, and may be changed to other values.

Next, implantation to form the n-type doped region 32 is performed. The n-type doped region 32 is sometimes referred to as an n-type junction field effect transistor (n-JFET) region because the n-type doped region 32 functions as a part of the junction field effect transistor (JFET) After the photoresist (not shown) is applied, it is patterned, the space 29 between the gate electrodes 30A and 30B is exposed, and the implantation is performed through the space 29. [ The n-type impurity implanted may include phosphorus, arsenic, and the like. At least a portion of the gate electrodes 30A, 30B may be used as an implant mask. The injected n-type impurity neutralizes the p-type impurity in the implanted portion of the p-body 26 and converts the implanted portion to n-type. The resulting n-type doped region 32 may extend through the p-body 26 to at least the bottom and extend into the epitaxial layer 22. Thus, the p-body 26 is divided into two parts, the p-body 26A and the p-body 26B. The impurity concentration of the n-type doped region 32 may be between about 10 15 / cm 3 and about 10 18 / cm 3, depending on some embodiments. the interface 32A between the n-type doped region 32 and the p-body 26A is substantially aligned with the edge 30A1 of the gate electrode 30A and the n-type doped region 32 and the p- ) Is substantially aligned with the edge 30B1 of the gate electrode 30B. However, the interface can also be extended toward the gate electrode due to the outer diffusion of the implant, after the heat treatment performed after implantation.

Referring to Fig. 1C, further implantation is performed to form a heavily doped n-type region 34 that serves as the source contact region. The n-type region 34 may have an n-type impurity concentration, for example, between about 10 19 / cm 3 and about 10 21 / cm 3. The bottom surface of the n-type region 34 is spaced from the epitaxial layer 22 by the portion of the p-body 26. In a subsequent step, gate spacers 36 are formed on the side walls of the gate electrodes 30A and 30B. The forming process may include depositing a dielectric layer and then performing an anisotropic etch to remove the horizontal portion of the dielectric layer. The vertical portions of the dielectric layer at the sidewalls of the gate electrodes 30A and 30B remain after etching to form the gate spacers 36. [

1D, a dielectric layer 38 is formed over n-type region 34, spacers 36, and gate electrodes 30A and 30B. In some embodiments, dielectric layer 38 is used as an etch stop layer when forming contact openings in subsequent steps, and contact openings are used to form contact plugs connected to gate electrodes 30A and 30B. Dielectric layer 38 may include an oxide, a nitride, an oxynitride, a combination thereof, and multiple layers thereof.

1E, a dielectric layer 38, a gate dielectric layer 28, and a portion of the heavily doped n-type region 34 are etched to form a contact hole 40. After the contact hole formation, the sidewalls of the heavily doped n-type region 34 are exposed to the contact holes 40 and the upper surface of the p-bodies 26A and 26B is also exposed. Next, p-type impurity implantation is performed to form the heavily doped p-type region 42 in the p-body region 26. In some embodiments, the p-type impurity concentration of the heavily doped p-type region 42 is between about 10 19 / cm 3 and about 10 21 / cm 3. The heavily doped p-type region 42 serves as a pickup region of the p-body 26A, 26B.

Referring to FIG. 1F, a conductive material is deposited to form a source region 43. The source region 43 contacts the sidewalls of the heavily doped n-type region 34. Further, a conductive material is deposited under the heavily doped semiconductor region 20 to form the drain region 44. A source region 43 and a drain region 44 are formed on the opposite sides of the respective wafers and chips. In some embodiments, the source region 43 and the drain region 44 are formed of a metal or metal alloy such as aluminum, copper, tungsten, nickel, or the like. Thereby, the vertical power MOSFET 52 is formed. Electrical connections 45 such as contact plugs, metal wires, etc. are formed over the gate electrodes 30A and 30B and are connected to the gate electrodes 30A and 30B. The gate electrodes 30A and 30B are therefore interconnected, at the same voltage level, and act as a gate.

The on-current of the vertical power MOSFET 52 is schematically illustrated by the curve 46 which includes the source region 43, the heavily doped n-type region 34, the p- Type doped region 32, the epitaxial region 22 and the semiconductor region 20 in the source region 26A and the drain region 26 in the source region 26A. It can be seen that the source region 43 includes a portion 42 'extending to the space between the gate electrodes 30A and 30B and overlapping the n-type doped region 32. [ The conductive portion 42 'serves as a field plate connected to the source region 43 and serves to reduce the surface electric field in the n-type doped region 32.

Figures 2A-2C are cross-sectional views of intermediate steps in the fabrication of vertical power MOSFETs in accordance with an alternative embodiment. Unless otherwise specified, the materials and methods of formation of the components of the embodiments shown in Figs. 2A-2C are essentially the same as the components indicated by the same reference numerals in the embodiment shown in Figs. 1A-1F . Therefore, details of the same components shown in Figs. 2A to 2C can be found in the description of the embodiment shown in Figs. 1A to 1F.

The initial steps of these embodiments are essentially the same as those shown in Figs. 1A-1D. Next, as shown in Fig. 2A, a field plate 48 is formed. The field plate 48 is conductive and may include polysilicon, metal silicide, metal, metal alloys, and the like. The field plate 48 extends into the space between the gate electrodes 30A and 30B and overlaps the n-type doped region 32. [ In some embodiments, the field plate 48 extends over the gate electrodes 30A and 30B and overlaps a portion of each gate electrode 30A and 30B. In an alternative embodiment, the field plate 48 does not extend over the gate electrodes 30A, 30B. The field plate 48 serves to reduce the surface electric field in the n-type doped region 32. In some embodiments, the field plate 48 is separated from the subsequently formed source region 43 and a different voltage than the source region 43 can be applied. In an alternative embodiment, the field plate 48 is connected to the subsequently formed source region 43, and thus is at the same voltage level as the source region 43.

Referring to FIG. 2B, an inter-layer dielectric (ILD) 50 is formed over the structure shown in FIG. 2A and is on dielectric layer 38. ILD 50 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS) oxide, and the like. The ILD 50 may be formed as a blanket layer. A contact hole 40 is then formed by etching the ILD 50, the gate dielectric layer 28 and a portion of the heavily doped n-type region 34 to form a contact hole 40. After forming the contact holes, the sidewalls of the heavily doped n-type region 34 are exposed and the top surface of the p-body 26A, 26B is also exposed.

Next, implantation is performed to implant the p-type impurity through the contact openings 40 and into the p-body 26 such that a heavily doped p-type region 42 is formed in the surface region of the p- . In a subsequent step, as shown in Figure 2C, a conductive material is deposited to form a source region 43 and a drain region 44. [ The vertical power MOSFET 52 is formed accordingly. Electrical connections 45 connected to gate electrodes 30A / 30B and field plate 48 may be formed by forming contact plugs and metal lines. In some embodiments, the field plate 48 is electrically coupled to the source region 43 and has the same voltage as the source region 43. In an alternative embodiment, the field plate 48 is separated from the source region 43 and a voltage different from the voltage of the source region 43 is applied.

The gate electrodes 30A and 30B do not overlap the n-type region 32 that is electrically connected to the drain region 44 through the n-type epitaxial layer 22 and the n-type region 20 . Therefore, the gate-drain capacitance is greatly reduced. In addition, since the n-type region 32 is formed by implantation and is doped with a high impurity concentration, the resistance of the n-type region 32 is reduced and the driving current of the vertical power MOSFET 52 is increased.

Although the embodiments shown in Figs. 1A-2C provide a method of fabricating an n-type vertical power MOSFET, those skilled in the art will appreciate that the description above applies to each region 20, 22, 26, 32, 34, 42 ) ≪ / RTI > is also readily available for the fabrication of p-type vertical power MOSFETs with opposite conductivity types.

3A-5F illustrate the fabrication of vertical MOSFET 52 with high voltage (HV) N-type MOS (HVNMOS) devices, low voltage LVN MOS devices, LV P MOS type LVPMOS devices, HV) P-type MOS (HVPMOS) device. Unless otherwise specified, the materials and methods of forming the components of these embodiments are essentially the same as the components indicated by the same reference numerals in the embodiment shown in Figs. 1A-2C. Therefore, details of the forming process and materials of the components shown in Figs. 3A to 5F can be found in the description of the embodiment shown in Figs. 1A to 2C.

3A shows device regions 100, 200, 300, 400, and 500 corresponding to the vertical power MOSFET region, the HVNMOS region, the LVNMOS region, the LVPMOS region, and the HVPMOS region, respectively. Referring to FIG. 3A, a substrate 21 is provided. According to some embodiments, the substrate 21 is a p-type substrate, but the substrate 21 may be an n-type substrate, according to an alternative embodiment. For example, an N type buried layer (NBL) 110 is formed on the upper surface of the substrate 21 through implantation. NBL 110 is in device region 100 and does not extend into device regions 200, 300, 400, Next, epitaxy is performed to form an epitaxial layer 22 on the substrate 21, where the epitaxial layer 22 can be doped in-situ with n-type impurities during epitaxy have. After epitaxy, an isolation region 23 is formed extending from the top surface of the epitaxial layer 22 to the epitaxial layer 22. The isolation region 23 may also be a field oxide, although it may be a shallow trench isolation (STI) region and thus is referred to throughout the specification as the STI region 23 . The STI region 23 may define active regions of the device regions 100, 200, 300, 400 and 500.

3B, a gate oxide layer 28 is formed on the surface of the epitaxial layer 22 and extends into the device regions 100, 200, 300, 400, A plurality of implants is performed to form a plurality of doped regions in the epitaxial layer 22. [ In some embodiments, a gate oxide layer 28 is formed prior to the implantation step, and the implanted impurities penetrate through the gate oxide layer 28 to form the implant region. In an alternative embodiment, a gate oxide layer 28 is formed after the implantation step.

The p-bodies 26 and 226 are simultaneously formed using the same lithography mask, and the lithography mask defines the pattern of the photoresist to be used as the implantation mask. A low voltage well (LVW) region 329, which may be a p-type region, is formed in the device region 300. The LVW region 329 can be configured to support each device to operate at an operating voltage of about 5V. A P-type doped drain (PDD) region 531 is formed in the device region 500. High voltage N-well (HVNW) regions 225, 325 and 525 are formed in the device regions 200, 300/400, and 500, respectively. The symbol "300/400" represents the junction area of the element regions 300 and 400. The p-body 226, the LVW region 329 and the PDD region 531 are formed inside the HVNW regions 225, 325, and 525, respectively. The doping concentration of the p-body 26, 226 is the same as in the embodiment shown in Figs. 1 to 2C. The LVW region 329 may have a p-type doping concentration between about 10 15 / cm 3 and about 10 18 / cm 3. The PDD region 531 may be lightly doped and have a p-type doping concentration between about 10 15 / cm 3 and about 10 18 / cm 3.

Depth p-well regions 227, 327 and 527 are also formed in device regions 200, 300/400 and 500 respectively and extend below HVNW regions 225, 325 and 525, respectively. The HVNW regions 225, 325, 525 and the deep p-well regions 227, 327, 527 may have a doping concentration between about 10 15 / cm 3 and about 10 18 / cm 3. 3B, the respective photoresists and the respective lithography masks are not illustrated, but those skilled in the art will be able to realize the details by the description of the embodiments .

3C, a gate electrode 30 (including 30A and 30B), 230, 330, 430, and 530 is formed over the gate oxide layer 28 in the device regions 100, 200, 300, 400, . Thereafter, implantation is performed to form an n-type doped region 32 located between the gate electrodes 30A and 30B, where the gate electrodes 30A and 30B act as part of the implant mask. Thus, the p-body 26 is separated into the p-body 26A and the p-body 26B by the n-type doped region 32. [ the n-type doped region 32 is formed and the n-type region 232 is simultaneously formed in the element region 200 by the same implantation. In some embodiments, a portion of the gate electrode 230 overlaps a portion of the p-body 226 and the other portion of the gate electrode 230 is offset from the p-body 226. Alternatively, the edge of the p-body 226 is aligned with the edge of the gate electrode 230. A part of the gate electrode 530 overlaps a part of the PDD region 531 and the other portion of the gate electrode 530 is deviated from the PDD region 531. [ Alternatively, the edge of the PDD region 531 is aligned with the edge of the gate electrode 530.

Referring to FIG. 3D, gate spacers 36, 236, 336, 436, and 536 are formed on the sidewalls of the gate electrodes 30, 230, 330, 430, and 530 at the same time. An implant is then implanted into the epitaxial layer 22 to form a heavily doped n-type region (denoted by N + regions) 34, 234, 334, 434, 534. Further implantation is also effected which is implanted into the epitaxial layer 22 to form a heavily doped p-type region (denoted as P + region) 42, 242, 342, 442, 542.

Next, as shown in FIG. 3E, a dielectric layer (not shown) is formed as a blanket layer so as to cover over the upper surfaces of the gate electrodes 30, 230, 330, 430, 530 and the gate spacers 36, 236, 336, 436, 38 are formed. A field plate (48) is formed over the dielectric layer (38) of the device region (100). At the same time as forming the field plate 48, field plates 248 and 548 are also formed in the device areas 200 and 500, respectively. The field plate 248 includes a portion on the drain side of the gate electrode 230 and may or may not include a portion overlapping the gate electrode 230. [ Similarly, the field plate 548 includes a portion on the drain side of the gate electrode 530, and may or may not include a portion overlapping the gate electrode 530. [

Referring to FIG. 3F, a deep metal via 54 is formed through the epitaxial layer 22 to reach the contact NBL 110. The formation of the deep metal vias 54 may include etching the epitaxial layer 22 to form openings and then filling the openings with a metallic material such as copper, aluminum, tungsten, or the like. The deep metal vias 54 are electrically connected to the NBL 110 and the NBL 110 forms the drain region of the vertical power MOSFET 52. (Shown by using line 43), which may be essentially the same as the source region 43 shown in FIG. 1F or FIG. 2C, is then connected to the P + region 42 and the N + region 34 . The source, drain, and gate of the vertical power MOSFET 52 are also designated S, D, and G, respectively.

3F, the HVNMOS device 252 is isolated from the gate electrode 230 by a portion of the n-type doped region 232 and the HVNW region 225, The right side of the electrode 230). Thus, due to the low doping concentration of the HVNW region 225, the HVNMOS device 252 can maintain a high drain voltage. The field plate 248 also helps to reduce the surface field at the HVNMOS device 252. The field plate 248 may be electrically coupled to the source 234 (on the left side of the gate electrode 230).

The LVNMOS device 352 includes source and drain regions 334 in the LVW region 329. The LVPMOS device 452 includes source and drain regions 442 in the HVNW region 325. The HVPMOS device 552 includes a drain 542 (the right side of the gate electrode 530) isolated from the gate electrode 530 by a portion of the PDD region 531. Thus, the HVPMOS device 552 can maintain a high drain voltage. The field plate 548 also helps to reduce the surface field at the HVPMOS device 552. Field plate 548 may be electrically coupled to source 542 (to the left of gate electrode 530).

The components of the HVNMOS device 252, the LVNMOS device 352, the LVPMOS device 452, and the HVPMOS device 552 are also formed while the various components of the vertical power MOSFET 52 are formed . By simultaneously forming device components, such as implant regions of MOS devices 52, 252, 352, 452, and 552, the lithographic mask and each process step can be shared, thus saving manufacturing costs.

4A-4F illustrate how to integrate HVNMOS device 252, LVNMOS device 352, LVPMOS device 452 and HVPMOS device 552 with the formation of vertical power MOSFET 52 in accordance with an alternative embodiment, Respectively. These embodiments are similar to the embodiment shown in Figs. 3A to 3F, but instead of forming the n-type epitaxial layer 22, a p-type epitaxial layer 22 'is formed and the HVNW region is formed of a p- Is formed in the taxi layer 22 '. Devices 52, 252, 352, 452, and 552 are then formed in the HVNW region.

Referring to Fig. 4A, a substrate 21, which may be a p-type substrate, is provided. NBLs 110, 210, 310 and 510 are formed in the device regions 100, 200, 300/400, and 500 by performing an implantation process on the substrate 21. The epitaxial layer 22 'is then formed, wherein the p-type impurity is in-situ doped when the epitaxial layer 22' is formed. An STI region 23 is then formed and extends from the top surface to the epitaxial layer 22 '. Further, HVNW regions 125, 225, 325, and 525 are formed in the device regions 100, 200, 300/400, and 500, respectively, by implantation of n-type impurities. The HVNW regions 125, 225, 325 and 525 may extend from the upper surface to the lower surface of the epitaxial layer 22 'and may be coupled to the lower NBLs 110, 210, 310 and 510, respectively. A gate oxide layer 28 is also formed. In some embodiments, the gate oxide layer 28 is formed prior to the implantation step, and impurities implanted therein penetrate through the gate oxide layer 28 to form the implant region. In an alternative embodiment, the gate oxide layer 28 is performed after the implantation step.

4B, p-bodies 26 and 226 are formed through implantation. Further, an LVW region 329 and a PDD region 531 are formed by implantation. The subsequent process steps in Figures 4C-4F are essentially the same as those shown in Figures 3C-3F. Therefore, details of FIGS. 4C to 4F can be found in the description of FIGS. 3C to 3F, and a simple process flow will be described below. 4C, gate electrodes 30, 230, 330, 430, and 530 are formed, and then n-type doped regions 32 and 232 are formed. Thus, the p-body 26 of Fig. 4B is separated into p-body 26A and p-body 26B. 4D shows that the gate spacers 36, 236, 336, 436 and 536 are formed. After forming the gate spacers, N + regions 34, 234, 334, 434 and 534 and P + regions 42, 242, 342, 442 and 542 are formed by implantation.

In Figure 4E, a dielectric layer 38 is formed, followed by field plates 48, 248, and 548. In FIG. 4F, a deep metal via 54 is formed and an electrical connection to the vertical power MOSFET 52 is formed. The electrical connections are indicated by source (S), drain (D) and gate (G).

5A-5F illustrate how to integrate HVNMOS device 252, LVNMOS device 352, LVPMOS device 452 and HVPMOS device 552 with the formation of vertical power MOSFET 52 in accordance with an alternative embodiment. Respectively. These embodiments are similar to the embodiment shown in Figs. 3A to 4F except that the electrical connection to the vertical power element 52 is formed on the opposite side of each substrate 21 'which is n-type in this embodiment.

Referring to FIG. 5A, an N + substrate 21 'is provided. The N + substrate 21 'has a high n-type impurity concentration that can be, for example, between about 10 19 / cm 3 and about 10 21 / cm 3. The N-type epitaxial layer 22 is epitaxially grown on the N + substrate 21 '. Next, an STI region 23 is formed and extends from the upper surface to the epitaxial layer 22.

5B, a gate oxide layer 28 is also formed over the epitaxial layer 22 and p-bodies 26 and 226 are formed by implantation. Further, an LVW region 329 and a PDD region 531 are formed by implantation. Further, HVNW regions 225, 325, and 525 are formed in the device regions 200, 300/400, and 500, respectively, through implantation of n-type impurities. The HVNW regions 225, 325 and 525 partially extend into the epitaxial layer 22 and are separated from the N + substrate 21 'by portions of the epitaxial layer 22. In some embodiments, the gate oxide layer 28 is formed prior to the implantation step. In an alternative embodiment, the gate oxide layer 28 is performed after the implantation step. Deep p-well regions 227, 327 and 527 are also formed.

The subsequent process steps in Figures 5C-5E are essentially the same as those shown in Figures 3C-3E. Therefore, the details of Figs. 5C to 5E can be found in the description of Figs. 3C to 3E. A simple process flow is described below. 5C, gate electrodes 30, 230, 330, 430, and 530 are formed, and then n-type doped regions 32 and 232 are formed. Thus, the p-body 26 of Fig. 5B is separated into p-body 26A and p-body 26B as shown in Fig. 5C. 5D shows that the gate spacers 36, 236, 336, 436 and 536 are formed. After forming the gate spacers, N + regions 34, 234, 334, 434 and 534 and P + regions 42, 242, 342, 442 and 542 are formed by implantation.

In Figure 5E, a dielectric layer 38 is formed, followed by field plates 48, 248, and 548. Next, in FIG. 5F, a metal plate 54 'is deposited on the N + substrate 21' and is physically contacted with the N + substrate 21 '. The metal plate 54 'and the N + substrate 21' act as the drain of the vertical power MOSFET 52. Thus, the source and drain connections of the vertical power MOSFET 52 are formed on the opposite side of each substrate 21 '. By forming the source and drain connections on the opposite side, in the subsequent packaging process, the vertical power MOSFET 52 can be easily stacked with other components.

In Figs. 3A to 5F, the formation of various MOS elements in different element regions and having different functions are integrated. The formation of various MOS devices may share the same lithographic mask. Structurally, the components of a MOS device formed at the same time can have the same type of impurity, the same depth, and the like. By sharing the lithography mask and the formation steps, manufacturing costs are saved.

According to embodiments, the device includes a first conductive semiconductor layer and first and second body regions over the semiconductor layer, wherein the first and second body regions have a second conductivity Type. A doped semiconductor region of a first conductivity type is disposed between the first body region and the second body region to contact the first and second body regions. A gate dielectric layer is disposed over the doped semiconductor regions with the first and second body regions. First and second gate electrodes are disposed over the gate dielectric layer and overlie the first and second body regions, respectively. The first and second gate electrodes are physically separated from each other by a space and are electrically interconnected. The space between the first gate electrode and the second gate electrode overlaps the doped semiconductor region. The device also includes a MOS-containing device on the surface of the semiconductor layer and the MOS-containing device is selected from the group consisting of an HVNMOS device, an LVNMOS device, an LVPMOS device, a HVPMOS device, and combinations thereof.

According to another embodiment, the device comprises a first conductivity type semiconductor layer and a vertical power MOSFET. The vertical power MOSFET includes first and second body regions of a second conductivity type opposite to the first conductivity type and includes a doped semiconductor region of a first conductivity type between the first body region and the second body region . The lower portion of the doped semiconductor region and the first and second body regions are in contact with the upper surface of the semiconductor layer. A gate dielectric layer is formed over the doped semiconductor regions with the first and second body regions. First and second gate electrodes are formed over the gate dielectric layer and are overlaid on the first and second body regions, respectively. The first and second gate electrodes are physically separated from each other by a space and are electrically interconnected. The source region includes a portion over the first and second body regions. The vertical power MOSFET also includes a drain region below the semiconductor layer. The high voltage MOS device is disposed on the semiconductor layer.

According to yet another embodiment, a method includes epitaxially growing a layer of an epitaxial semiconductor of a first conductivity type, and forming a semiconductor body layer over the epitaxial semiconductor layer. The semiconductor body layer has a second conductivity type opposite to the first conductivity type. A gate dielectric layer is formed over the semiconductor body layer. First and second gate electrodes are formed over the gate dielectric layer, wherein the first and second gate electrodes are spaced from each other by a space. A portion of the semiconductor body layer is implanted to form a doped semiconductor region of a first conductivity type, wherein the doped semiconductor regions are overlapped by a space. The doped semiconductor region extends to contact the epitaxial semiconductor layer. A source region is formed over the semiconductor body layer. A drain region is formed below the epitaxial semiconductor layer. A high-voltage MOS device is also formed on the surface of the epitaxial semiconductor layer.

Although various embodiments and advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present invention is not intended to be limited to the particular embodiments of processing, machine, manufacture, composition of matter, means, methods and steps described in the specification. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims, Manufacture, composition of matter, means, methods and steps may be utilized according to the description of the specification. Accordingly, the appended claims are intended to include within their scope such processing, machine, manufacture, composition of matter, means, methods and steps. Further, each claim constitutes a separate embodiment, and combinations of various claims and embodiments are also included in the scope of the present invention.

20: semiconductor region 22: epitaxial layer
26: p-body 28: gate dielectric layer
30A, 30B: gate electrode 32: n-type doping region
34: n-type region 36: spacer
38: dielectric layer 43: source region
44: drain region

Claims (10)

A first conductive semiconductor layer;
First and second body regions on the semiconductor layer, the first and second body regions being a second conductive type opposite to the first conductive type;
A first conductive type doped semiconductor region in contact with the first and second body regions between the first body region and the second body region;
A gate dielectric layer over the first and second body regions and the doped semiconductor region;
First and second gate electrodes respectively superimposed on the first and second body regions above the gate dielectric layer, the first and second gate electrodes being physically separated from each other by a space, Wherein the space overlaps the doped semiconductor region and the first and second gate electrodes do not overlap the doped semiconductor region;
A metal-oxide semiconductor (MOS) -containing element on the surface of the semiconductor layer; the MOS-containing element includes a high-voltage N-type MOS (HVNMOS) Type MOS (LVNMOS) device, a low voltage P-type MOS (LVPMOS) device, a high voltage P-type MOS (HVPMOS) device, and combinations thereof The device containing the selected. The method of claim 1, wherein the first and second gate electrodes are included in a vertical power MOS field effect transistor (MOSFET)
A source region including a first portion over the first and second body regions;
A buried semiconductor layer of the first conductivity type serving as a drain of the vertical power MOSFET under the semiconductor layer;
Further comprising a deep metal via penetrating the semiconductor layer to contact the buried semiconductor layer. 2. The device of claim 1, wherein the first and second gate electrodes are included in a vertical power metal oxide semiconductor field effect transistor (MOSFET)
A source region including a first portion over the first and second body regions;
And further comprising a drain region under the semiconductor layer. 2. The device of claim 1, wherein the MOS-containing device comprises an HVNMOS device,
A third body region of the second conductivity type on the semiconductor layer;
A third gate electrode over the third body region;
A source region and a drain region of the first conductivity type adjacent to the third gate electrode and on opposite sides of the third gate electrode;
And a field plate including a portion on the drain side of the third gate electrode. 2. The device of claim 1, wherein the MOS-containing device comprises an HVPMOS device,
A lightly doped drain region of the second conductivity type over the semiconductor layer;
A third gate electrode over the lightly doped drain region;
A source region and a drain region of the second conductivity type adjacent to the third gate electrode and on opposing sides of the third gate electrode, the drain region being formed by a portion of the lightly doped drain region, Spaced apart from the electrode;
And a field plate including a portion on the drain side of the third gate electrode. The method according to claim 1,
A conductive field plate disposed in a space between the first gate electrode and the second gate electrode;
Further comprising an interlayer dielectric on said conductive field plate. 2. The semiconductor device of claim 1, wherein a first interface between the first body region and the doped semiconductor region is aligned with an edge of the first gate electrode, and a second interface between the second body region and the doped semiconductor region Is aligned with an edge of the second gate electrode. A first conductive semiconductor layer;
A vertical power metal oxide semiconductor field effect transistor (MOSFET);
And a high voltage MOS device on the surface of the semiconductor layer,
First and second body regions within a surface region of the semiconductor layer and having a second conductivity type opposite to the first conductivity type;
A first doped semiconductor region of the first conductivity type located between the first body region and the second body region, the lower portion of the first and second body regions and the first doped semiconductor region being electrically connected to the semiconductor Contacting the upper surface of the layer;
A gate dielectric layer over the first and second body regions and the first doped semiconductor region;
First and second gate electrodes over the gate dielectric layer and overlapping the first and second body regions, respectively, the first and second gate electrodes being physically separated from each other by a space and electrically interconnected, Not overlapping the first doped semiconductor region;
A first source region comprising a first portion over the first and second body regions;
Wherein the first source region and the first drain region are on opposite sides of a region comprising the first and second body regions. Epitaxially growing an epitaxial semiconductor layer of a first conductivity type;
Forming a semiconductor body layer over the epitaxial semiconductor layer, the semiconductor body layer being a second conductive type opposite the first conductive type;
Forming a gate dielectric layer over the semiconductor body layer;
Forming first and second gate electrodes over the gate dielectric layer, the first and second gate electrodes being spaced from each other by a space;
The doped semiconductor region of the first conductivity type, the doped semiconductor region being overlapped by the space but not overlapping the first and second gate electrodes, the doped semiconductor region being in contact with the epitaxial semiconductor layer Implanting a portion of the semiconductor body layer to form a semiconductor body layer;
Forming a source region over the semiconductor body layer;
Forming a drain region below the epitaxial semiconductor layer;
And forming a high-voltage MOS device on the surface of the epitaxial semiconductor layer. 10. The method of claim 9,
Forming a dielectric layer over the first and second gate electrodes after implanting a portion of the semiconductor body layer to form the doped semiconductor region;
Further comprising forming a first conductive field plate over the dielectric layer, wherein the first conductive field plate extends into the space between the first gate electrode and the second gate electrode.
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