JP2005072356A - Insulated gate type electric field effect semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a capacity, to realize speed-up, to reduce a capacity much more, to realize the reduction of ON-resistance, and to improve a performance index by a method wherein a power MOSFET for use in a high-speed DC/DC converter or the like is constituted of a stripe structure. <P>SOLUTION: The insulated gate type electric field effect semiconductor device is provided with: a one conduction type drain region provided on a semiconductor substrate; a reverse conduction type channel layer provided on the surface of the drain region; a trench provided on the channel layer and having a depth not arriving at the drain region; an insulating film provided on the inner wall of the trench; a gate electrode consisting of a side wall provided on the side wall of the trench; a one-conduction type impurity region provided on the bottom of the trench; an interlayer insulating film for covering at least the gate electrode, a one-conduction type source region provided on the surface of the channel layer so as to be neighbored to the trench; and a reverse-conduction type body contact region provided on the surface of the channel layer between the neighboring source regions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an insulated gate field effect semiconductor device and a method for manufacturing the same, and more particularly to an insulated gate field effect semiconductor device capable of improving a figure of merit by reducing capacitance and on-resistance and a method for manufacturing the same.

  In an insulated gate field effect semiconductor device in which a gate electrode is embedded in a stripe-structured trench, the source region is also formed with a uniform width along the trench (see, for example, Patent Document 1).

  Referring to FIGS. 8 and 9, a trench type power MOSFET is shown as an example of a conventional insulated gate field effect semiconductor device.

FIG. 8 shows an example of a cross-sectional structure of a conventional MOSFET using an n-channel type. A drain region 22 made of an n ⁻ type epitaxial layer is provided on an n ⁺ type silicon semiconductor substrate 21, and a p type channel layer 23 is provided on the surface thereof. The trench penetrates the channel layer 23 and reaches the drain region 22, and the inner wall of the trench 27 is coated with a gate oxide film 31. The gate electrode is made of polysilicon filled in the trench 27, an n + type source region 35 is formed on the surface of the channel layer 23 adjacent to the trench 27, and the surface of the channel layer 23 between the source regions 35 of two adjacent cells. Is provided with a p + type body contact region 34. When a gate voltage is applied to the gate electrode 33, a channel region CH is formed in the channel layer 23 from the source region 35 along the trench 27. The gate electrode 33 is covered with an interlayer insulating film 36, and a source electrode 37 that contacts the source region 35 and the body contact region 34 is provided (see, for example, Patent Document 1).

  With reference to FIG. 9, a method of manufacturing the MOSFET will be described.

First, an n ⁻ type epitaxial layer is stacked on an n ⁺ type silicon semiconductor substrate 21 to form a drain region 22, boron is implanted into the surface, and then diffused to form a p type channel layer 23. Further, an NSG (Non-doped Silicate Glass) CVD oxide film 25 is formed on the entire surface by CVD, and the CVD oxide film 25 is partially removed by dry etching to form a trench opening 26 where the channel region 23 is exposed. It is formed (FIG. 9A).

  Next, the silicon semiconductor substrate in the trench opening 26 is dry-etched using the CVD oxide film 25 as a mask to form a trench 27 having a depth reaching the drain region 22 through the channel layer 23. Thereafter, dummy oxidation is performed to remove etching damage during dry etching, and then the entire surface is thermally oxidized to form a gate oxide film 31 (FIG. 9B).

  Further, a gate electrode 33 embedded in the trench 27 is formed. That is, after depositing non-doped polysilicon on the entire surface, an impurity is introduced or a polysilicon layer into which an impurity is introduced is deposited, and the polysilicon layer is dry-etched without a mask to form the gate electrode 33 embedded in the trench 27. It is formed (FIG. 9C).

Thereafter, boron is selectively ion-implanted with a mask of resist PR to form a p ⁺ -type body region 34, and then the resist PR is removed. Further, masking is performed so that the planned source region 35 and the gate electrode 33 are exposed with a new resist PR, and arsenic is ion-implanted with a dose amount of 5.0 × 10 ¹⁵ , and the n ⁺ -type source region 35 is formed in the trench 27. Then, the resist PR is removed (FIG. 9D).

Thereafter, a BPSG (Boron Phosphorus Silicate Glass) layer is deposited on the entire surface by a CVD method to form an interlayer insulating film 36. Thereafter, the interlayer insulating film 36 is left at least on the gate electrode 33 using the resist film as a mask. Thereafter, aluminum is deposited on the entire surface by a sputtering apparatus to form a source electrode 37 in contact with the source region 35 and the body region 34 to obtain the final structure shown in FIG.
US Pat. No. 6,060,747, FIG. 1

  FIG. 10 shows a plan view of a part of the MOSFET. Note that the source electrode and the interlayer insulating film are omitted. For example, in a MOSFET for use in a DC-DC converter having a large chip size, the trench 27 and the gate electrode 33 are provided in stripes as shown in the figure. In this structure, the area of the gate oxide film 31 per unit cell area can be reduced as compared with the structure in which the trenches are provided in a lattice shape, and thus the parasitic capacitance between the gate and the drain can be reduced. That is, even if the chip size is large, charges are not accumulated during switching, and the switching speed can be improved. Therefore, it is generally used for switching elements having a large chip size.

  However, for high-speed DC-DC converter applications, it is necessary to improve the figure of merit. Since the figure of merit is the product of the on-resistance and the capacity of the device, it is desired to reduce not only the capacity but also the on-resistance.

  In order to reduce the area of the gate oxide film 31 and reduce the parasitic capacitance between the gate and the drain, it is conceivable to reduce the depth of the trench 27. However, making the trench 27 shallower also makes the channel layer 23 shallower. In particular, in a device that requires a high breakdown voltage, the breakdown voltage depends on the thickness of the epitaxial layer 22 that is the drain region and its impurity concentration, so that the breakdown voltage deteriorates if the channel layer 23 is too shallow.

  The present invention has been made in view of such a problem. First, a drain region of one conductivity type provided in a semiconductor substrate, a channel layer of opposite conductivity type provided on the surface of the drain region, and the drain provided in the channel layer. A trench not deep enough to reach the region; an insulating film provided on the inner wall of the trench; a gate electrode comprising a sidewall provided on the trench side wall; a one-conductivity type impurity region provided on the bottom of the trench; and the gate electrode An inter-layer insulating film covering at least the gate electrode, a source region of one conductivity type provided on the surface of the channel layer adjacent to the trench, and a body contact region of opposite conductivity type provided on the surface of the channel layer between the adjacent source regions To solve the problem.

  The one-conductivity type impurity region partially reaches the drain region.

  The width of the one conductivity type impurity region is wider than the width of the opening of the gate electrode.

  Further, the one conductivity type impurity region has an impurity concentration comparable to that of the source region.

  The one-conductivity type impurity region has a lower concentration than the source region and a higher impurity concentration than the drain region.

  Second, forming a drain region of one conductivity type on a semiconductor substrate, forming a channel layer of reverse conductivity type on the surface of the drain region, forming a trench that does not reach the drain region in the channel layer, Forming a thin insulating film on the inner wall of the trench; forming a sidewall-shaped gate electrode on the sidewall of the trench; forming a one-conductivity type impurity region at a bottom of the trench; and the channel layer adjacent to the trench A step of forming a source region of one conductivity type on the surface, a step of forming a body contact region of opposite conductivity type on the surface of the channel layer between the adjacent source regions, and an interlayer insulating film covering at least the surface of the gate electrode This is solved by including the forming step.

  The one conductivity type impurity region may be formed by implanting impurities using the gate electrode as a mask.

  Further, the source region and the one-conductivity type impurity region are formed in the same step.

  Further, the source region is formed after the one-conductivity type impurity region is formed.

  The one conductivity type impurity region is formed to reach the drain region.

  According to the present invention, the following effects can be obtained. First, since the trench can be formed shallow, the area of the gate oxide film in contact with the gate electrode on the side surface of the trench can be reduced. In the MOSFET having the trench structure, the source electrode is also in contact with the channel layer through the body contact region, and the gate-source capacitance Cgs can be reduced by reducing the capacitance between the channel and the gate electrode. Since the gate electrode has a sidewall shape, the area of the gate electrode in contact with the gate oxide film at the bottom of the trench can be reduced, and the gate-drain capacitance Cgd can be reduced. That is, since Cgs and Cgd can be reduced, the switching speed of the transistor can be improved.

  Second, since the length of the channel formed along the trench can be reduced, the channel resistance component of the on-resistance can be reduced. Thereby, both the capacity and the on-resistance are reduced, and the figure of merit is greatly improved.

  Third, unlike the conventional structure, there is no need to form a trench penetrating the channel layer. Since the channel is formed by providing the one conductivity type impurity region at the bottom of the trench so as to reach the drain region, a deep channel layer can also be formed. That is, it is possible to reduce the capacitance and the on-resistance with a shallow trench while ensuring a breakdown voltage with a deep channel layer.

  In addition, according to the manufacturing method of the present invention, an n-type (n + -type) impurity region can be formed in the same process as the source region, so that an insulated gate semiconductor that reduces capacitance and on-resistance without increasing the manufacturing process A device manufacturing method can be provided.

  An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7 by taking an n-channel type MOSFET having a trench structure as an example.

  FIG. 1 is a cross-sectional view showing a MOSFET of the present invention. The MOSFET of the present invention includes a drain region 2, a channel layer 3, a trench 4, a gate oxide film 5, a gate electrode 7, a one conductivity type impurity region 8, a source region 9, a body contact region 10, It is composed of an interlayer insulating film 11, a source electrode 12, and a drain electrode 13.

A drain region 2 made of an n ⁻ type epitaxial layer is provided on an n ⁺ type silicon semiconductor substrate 1, and a channel layer 3 is provided on the surface by diffusing p type impurities.

  The trench 4 is provided at a depth that does not reach the drain region 2 of the channel layer 3, that is, does not penetrate the channel layer 3. Although not shown, the planar shape is provided in a plurality of stripes as in FIG. On the inner wall of the trench 4, a gate oxide film 5 is provided on the order of several hundreds of squares depending on the driving voltage.

  A side wall is formed of polysilicon on the side wall of the trench 4 and serves as a gate electrode 7. Because of the sidewall shape, a part of the bottom of the trench 4 is exposed, and an opening OP of the gate electrode 7 is formed.

The n-type impurity region 8 is provided between the trench 4 and the drain region 2 immediately below the opening OP, and part of the n-type impurity region 8 reaches the drain region 2. The impurity concentration is higher than that of the drain region 2 and equal to or lower than that of the source region 9, for example, about 2 × 10 ¹⁴ cm −3. The n-type impurity region 8 is provided wider than the opening OP. Furthermore, although illustration is omitted, it may be provided so as to cover from the bottom of the trench 4 to the side wall of the trench 4.

  Source region 9 is an n + type region provided on the surface of channel layer 3 adjacent to trench 4, and body contact region 10 is a p + type region provided on the surface of channel layer 3 between adjacent source regions 9. .

  The interlayer insulating film 11 is an insulating film embedded in the opening OP and the trench 4 and is provided so as to cover the gate electrode 7. A source electrode 12 that contacts the source region 9 and the body contact region 10 is provided on the substrate surface, and a drain electrode 13 is provided on the back surface of the substrate by metal vapor deposition.

  FIG. 1B shows an enlarged view of the vicinity of the trench 4. As shown in the figure, in this embodiment, an n-type impurity region 8 is provided at the bottom of the trench 4 shallower than the channel layer 3, and the n-type impurity region 8 reaches the drain region 2. Further, the end portion of the n-type impurity region 8 is formed so as to overlap with a part of the gate electrode 7 with the gate insulating film 5 interposed therebetween. Thereby, when a gate voltage is applied to the gate electrode 7, a channel CH is formed from the source region 9 to the channel layer 3 in the n-type impurity region 8 along the trench 4 as indicated by a broken line.

  Assuming that the depth of the channel layer 3 and the width of the trench 4 are the same as those of the conventional structure (FIG. 8), in this embodiment, the length of the channel CH can be reduced because the trench 4 is shallow. That is, the channel resistance component of the on-resistance of the MOSFET can be reduced.

  Further, by making the trench 4 shallow, the gate-source capacitance Cgs can also be reduced. Since the source electrode 12 is also in contact with the channel layer 3 through the body contact region 10 as shown in FIG. 1A, the gate-source capacitance Cgs can be considered as the capacitance between the channel CH and the gate electrode 7. That is, the gate-source capacitance Cgs can be reduced by reducing the length of the channel CH. Further, the gate-drain capacitance Cgd generated at the bottom of the trench 4 can be reduced because the capacitance of the opening OP portion of the gate electrode 7 is eliminated.

  As described above, high-speed switching is required for applications such as a DC-DC converter, and the capacitance is reduced by forming the trench 4 in a stripe structure. However, according to the present embodiment, the capacitance can be further reduced.

  Here, the trench 4 will be described. In the present embodiment, the n-type impurity region 8 provided at the bottom of the trench 4 needs to be in contact with the drain region 2. As will be described in detail later, the n-type impurity region 8 is a region to be diffused after ion implantation is performed on the bottom of the trench 4 using a side wall having a width (thickness) Wg as the gate electrode 7 as a mask.

  It is known that in the case of a silicon substrate, when the (100) plane is used as the substrate surface, channeling is most prevented when ions are implanted from a direction inclined by 7 ° (FIG. 1 (B) α) from the crystal axis, that is, the side surface of the trench. Yes. That is, the opening OP of the gate electrode 7 may be provided so as to satisfy the condition of trench depth d = gate electrode width Wg / tan 7 °.

  Further, the depth of the trench 4 is formed shallower than the depth of the channel layer 3. For example, the distance between the bottom of the trench 4 and the channel layer 3 is provided to be narrower than the depth of the source region 9. As will be described later, the n-type impurity region 8 may be formed simultaneously with the source region 9 (in this case, the impurity concentration is approximately the same as that of the source region 9).

  The n-type impurity region 8 can be deepened by increasing the acceleration voltage during ion implantation. The depth of the trench 4 and the depth of the n-type impurity region 8 are provided so that the n-type impurity region 8 can reach the channel layer 3 in consideration of the characteristics as an element and the limit of the acceleration voltage.

  As described above, according to the present embodiment, the gate-source capacitance Cgs and the gate-drain capacitance Cgd can be reduced, and the channel resistance component of the on-resistance can be further reduced, which can greatly contribute to the improvement of the performance index of the transistor. Further, even if the trench 4 is shallow, the channel layer 3 can secure a depth of the conventional level or more, and therefore has an advantage that a high withstand voltage design is possible.

  Next, a method of manufacturing the MOSFET shown in FIG. 1 will be described with reference to FIGS.

  The MOSFET forms a drain region of one conductivity type on a semiconductor substrate, forms a channel layer of a reverse conductivity type on the surface of the drain region, forms a trench that does not reach the drain region in the channel layer, Forming a thin insulating film on the inner wall of the trench; forming a gate electrode in a sidewall shape on the sidewall of the trench; forming a one-conductivity type impurity region at the bottom of the trench to be an opening of the gate electrode; Forming a source region of one conductivity type on the surface of the channel layer adjacent to the trench; forming a body contact region of opposite conductivity type on the surface of the channel layer between the adjacent source regions; and surface of the gate electrode Forming an interlayer insulating film that at least covers the substrate.

  First step (see FIG. 2): A step of forming a drain region of one conductivity type on a semiconductor substrate and forming a channel layer of a reverse conductivity type on the surface of the drain region.

A drain region 2 is formed by stacking an n ⁻ type epitaxial layer on the n ⁺ type silicon semiconductor substrate 1. After an oxide film (not shown) is formed on the surface, an oxide film in a predetermined channel layer portion is opened, and boron is implanted into the entire surface, for example, at a dose of about 1.0 × 10 ¹³ cm ⁻³ using the oxide film as a mask. Thereafter, the p-type channel layer 3 is formed by diffusion.

  Second step (see FIG. 3): a step of forming a trench that does not reach the drain region in the channel layer and forming a thin insulating film on the inner wall of the trench.

  A CVD oxide film (not shown) of NSG (Non-doped Silicate Glass) is formed on the entire surface by CVD. The CVD oxide film is partially removed to form a trench opening, and the trench 4 is formed by dry etching the silicon semiconductor substrate in the trench opening with CF-based gas and HBr-based gas. The trench 4 is formed to a depth that is shallower than the channel layer 3 and does not reach the drain region 2.

  Further, the inside of the trench 4 is dummy oxidized to remove etching damage during dry etching. The dummy oxide film formed by this dummy oxidation and the CVD oxide film used as a mask for forming the trench 4 are simultaneously removed by an oxide film etchant such as hydrofluoric acid. This is because a stable gate oxide film is formed in a later process. In addition, there is an effect of rounding the opening of the trench 4 due to thermal oxidation at a high temperature to avoid electric field concentration in the opening of the trench 4. Thereafter, the entire surface is thermally oxidized to form a gate oxide film 5 with a film thickness of, for example, several hundreds of squares according to the driving voltage.

  Third step (see FIG. 4): a step of forming a gate electrode in a sidewall shape on the sidewall of the trench.

  First, as shown in FIG. 4A, non-doped polysilicon 6 is deposited on the entire surface, and phosphorus is implanted and diffused at a high concentration to increase the conductivity. Alternatively, polysilicon 6 containing impurities may be deposited. The thickness of the polysilicon 6 is set to ½ or less of the width of the trench 4 and is formed in the trench 4.

  Next, as shown in FIG. 4B, the polysilicon layer 6 deposited on the entire surface is dry-etched without a mask to form a sidewall on the side wall of the trench 4. In the present embodiment, this is the gate electrode 7. Since it is a sidewall, a part of the bottom of the trench 4 is exposed, and an opening OP of the gate electrode 7 is formed.

  Fourth step (see FIG. 5): a step of forming a one-conductivity type impurity region at the bottom of the trench to be an opening of the gate electrode and forming a one-conductivity type source region on the surface of the channel layer adjacent to the trench.

First, as shown in FIG. 5A, n-type ions are implanted and diffused over the entire surface with, for example, arsenic at about 2 × 10 ¹⁴ cm ⁻³ . At this time, the gate electrode 7 serves as a mask, ions are implanted from the opening OP, and an n-type impurity region 8 is formed at the bottom of the trench 4.

After that, as shown in FIG. 5B, a mask with a resist PR is applied so that only the source region 9 is exposed, and, for example, arsenic is ion-implanted and diffused at a dose of about 5.0 × 10 ¹⁵ cm ^{−3. After the +} -type source region 9 is formed on the surface of the channel layer 3 adjacent to the trench 4, the resist PR is removed.

  If the impurity concentration of the n-type impurity region 8 is too high, the extension of the depletion layer with the other drain region 2 part changes, and electric field concentration tends to occur, so that the breakdown voltage is deteriorated. If the impurity concentration is too low, the accumulation resistance increases and the on-resistance increases. Therefore, as described above, it is preferable to form it in a range higher than the drain region 2 and lower than the impurity concentration of the source region 9.

Further, as shown in FIG. 5C, the n-type impurity region 8 and the source region 9 may be formed simultaneously. That is, as shown in the figure, the trench PR 4 and the surface of the channel layer 3 adjacent to the trench 4 are masked with a resist PR so that, for example, arsenic is implanted and diffused at a dose of about 5.0 × 10 ¹⁵ cm ^−3. Then, the n + type source region 9 is formed, and ions are implanted and diffused into the opening OP to form the n type impurity region 8 at the bottom of the trench 4. In this case, since the source region 9 is formed in the same process, the impurity concentration is high (n + type impurity region 8 in the figure), but in this embodiment, the n type (n + type) impurity region 8 is the same as the drain region 2. If it is the same conductivity type, it can be implemented, and there is no problem if the impurity concentration is higher than the impurity concentration of the drain region 2 and up to about the source region 9.

  In this case, the trench 4 is formed so that the depth from the bottom of the trench 4 to the channel layer 3 is shallower than the depth of the source region 9. Thereby, even if the source region 9 and the n + -type impurity region 8 are formed simultaneously, the n + -type impurity region can reach the drain region 2.

  Even in the case of forming in a separate process as shown in FIG. 5B, the depth of the trench 4, the channel layer 3, and the n-type impurity region 8 is appropriately selected so that the n-type impurity region 8 reaches the drain region 2. .

  Fifth step (see FIG. 6): a step of forming a reverse conductivity type body contact region on the surface of the channel layer between adjacent source regions.

A mask made of resist PR was formed so that the body contact region portion was exposed, and boron was ion-implanted selectively with a dose amount of 5.0 × 10 ¹⁴ cm ⁻³ to form p ⁺ type body contact region 10. Thereafter, the resist PR is removed. The body contact region 10 is formed on the surface of the channel layer 3 between the adjacent source regions 9 and stabilizes the potential of the substrate.

  Sixth step (see FIG. 7): a step of forming an interlayer insulating film covering at least the gate electrode surface and forming a source electrode.

  A BPSG (Boron Phosphorus Silicate Glass) layer is deposited on the entire surface by a CVD method and patterned so as to cover the gate electrode 7 and the opening OP, thereby forming an interlayer insulating film 11. Thereafter, aluminum is deposited on the entire surface by a sputtering apparatus to form a source electrode 12 that contacts the source region 9 and the body contact region 10.

  Further, a drain electrode 13 made of vapor-deposited metal is formed on the back surface of the substrate to obtain the final structure shown in FIG.

  As described above, the embodiments of the present invention have been described using the n-channel MOSFET, but the present invention can also be applied to a p-channel MOSFET, and the same effect can be obtained. In addition, the present invention can be similarly implemented even with an IGBT in which a bipolar transistor and a power MOSFET are monolithically combined in one chip.

It is sectional drawing explaining the insulated gate field effect semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate field effect semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate field effect semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate field effect semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate field effect semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate field effect semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate field effect semiconductor device of this invention. It is sectional drawing explaining the conventional insulated gate field effect semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional insulated gate field effect semiconductor device. It is a top view explaining the conventional and the insulated gate field effect semiconductor device of this invention.

Explanation of symbols

1 n + type semiconductor substrate
2 drain region 3 channel layer 4 trench 5 gate oxide film 6 polysilicon 7 gate electrode 8 n-type impurity region 9 source region 10 body contact region 11 interlayer insulating film 12 source electrode
13 Drain electrode 21 n + type semiconductor substrate
22 drain region 23 channel layer 27 trench 31 gate oxide film 33 gate electrode 34 body contact region 35 source region 36 interlayer insulating film 37 source electrode
OP opening CH channel

Claims (10)

A drain region of one conductivity type provided in a semiconductor substrate;
A reverse conductivity type channel layer provided on the surface of the drain region;
A trench provided in the channel layer and having a depth not reaching the drain region;
An insulating film provided on the inner wall of the trench;
A gate electrode comprising a sidewall provided on the trench sidewall;
One conductivity type impurity region provided at the bottom of the trench;
An interlayer insulating film covering at least the gate electrode;
A source region of one conductivity type provided on the surface of the channel layer adjacent to the trench;
An insulated gate field effect semiconductor device comprising: a reverse conductivity type body contact region provided on a surface of the channel layer between adjacent source regions. 2. The insulated gate field effect semiconductor device according to claim 1, wherein a part of the one conductivity type impurity region reaches the drain region. 2. The insulated gate field effect semiconductor device according to claim 1, wherein the width of the one conductivity type impurity region is wider than the width of the opening of the gate electrode. 2. The insulated gate field effect semiconductor device according to claim 1, wherein the one conductivity type impurity region has an impurity concentration comparable to that of the source region. 2. The insulated gate field effect semiconductor device according to claim 1, wherein the one conductivity type impurity region has a lower concentration than the source region and a higher concentration than the drain region. Forming a drain region of one conductivity type on a semiconductor substrate and forming a channel layer of opposite conductivity type on the surface of the drain region;
Forming a trench that does not reach the drain region in the channel layer, and forming a thin insulating film on the inner wall of the trench;
Forming a sidewall-shaped gate electrode on the trench sidewall;
Forming one conductivity type impurity region at the bottom of the trench, and forming a one conductivity type source region on the surface of the channel layer adjacent to the trench;
Forming a reverse conductivity type body contact region on the surface of the channel layer between the adjacent source regions;
Forming an interlayer insulating film covering at least the surface of the gate electrode. A method of manufacturing an insulated gate field effect semiconductor device, comprising: 7. The method of manufacturing an insulated gate field effect semiconductor device according to claim 6, wherein the one conductivity type impurity region is formed by implanting impurities using the gate electrode as a mask. 7. The method of manufacturing an insulated gate field effect semiconductor device according to claim 6, wherein the source region and the one conductivity type impurity region are formed in the same step. The method of manufacturing an insulated gate field effect semiconductor device according to claim 6, wherein the source region is formed after forming the one conductivity type impurity region. 7. The method of manufacturing an insulated gate field effect semiconductor device according to claim 6, wherein the one conductivity type impurity region is formed to reach the drain region.

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