JP2850852B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a high voltage lateral MOS transistor used at a high voltage.

[0002]

2. Description of the Related Art Depending on equipment on which a semiconductor device is mounted, the power supply voltage may be extremely high. For this reason, semiconductor devices used in such devices are required to have excellent high withstand voltage characteristics. As a high breakdown voltage transistor used in such a semiconductor device, a lateral MOS transistor is generally used.

[0003] A conventional high breakdown voltage, horizontal insulated gate field effect transistor (hereinafter referred to as a high breakdown voltage lateral MOSFET)
Will be described with reference to FIG. 8 and FIG. FIG. 8 is a cross-sectional view of a high-withstand-voltage lateral MOSFET described in US Pat. No. 4,811,075. Also, FIG.
High withstand voltage horizontal type MO described in US Pat. No. 5,294,824.
It is a top view of SFET. Hereinafter, the former is referred to as a first conventional example, and the latter is referred to as a second conventional example.

First, a first conventional example will be described. As shown in FIG. 8, a p-type silicon substrate 101 is provided with an n ⁻ extended drain region 102, and a surface of the n ⁻ extended drain region 102 is in contact with a p-type diffusion layer 103, an element isolation insulating film 104, and a p-type diffusion layer 103. N ⁺ drain region 108
N ⁺ source region 107 to the surface of the type silicon substrate provided with a p ⁺ diffusion region 109 serving as the back gate electrode, a p-type silicon substrate 101 as a channel, n ^- gate across the extended drain region 102 and n ⁺ source region 107 A gate electrode 106 is provided with an insulating film 105 interposed therebetween. Further, an interlayer insulating film 110, a source electrode 111 and a drain electrode 112 are provided.

[0005] MOS transistor of this structure, n ^-
N ⁻ from both directions of the p-type silicon substrate 101 below the extended drain region 102 and the p-type diffusion layer 103 above it.
Since the extended drain region 102 can be depleted, n ⁻ is lower than that of the MOS transistor having no p-type diffusion layer 103.
The resistance of the extended drain region 102 can be reduced, and the on-resistance between the drain and the source when the transistor is conductive (on) can be reduced. Such a structure is generally called a double RESURF (Duuble RESURF) structure.

[0006] Next, USP 5294 as a second conventional example.
The structure proposed in US Pat.
075, the upper p-type diffusion layer 1
03 is striped. Such a high withstand voltage horizontal type M
FIG. 9 is a plan view of the OSFET. Here, the p-type diffusion layer 203 corresponding to the p-type diffusion layer 103 is hatched.

As shown in FIG. 9, a p-type silicon substrate 20
An n ^- extended drain region 202 is formed on 1, and a striped p-type diffusion layer 203 is formed in this region. Then, a gate electrode 206, an n ⁺ source region 207, an n ⁺ drain region 208, and a p ⁺ diffusion region 209 are formed. Here, p-type silicon substrate 201 below n ⁻ extended drain region 202 and p-type diffusion layer 2 above
The effect of depleting the n ⁻ extension drain region 202 from both directions is the same as that of the first conventional example. However, in this case, since the p-type diffusion layer 203 is formed in a stripe shape, the cross-sectional area of the charge passage of the n ⁻ -extended drain region 202 when the MOS transistor is turned on is larger than that in the first conventional example. I do. Then, the on-resistance between the drain and the source when the transistor is turned on is further reduced.

[0008]

However, in such a conventional double RESURF high breakdown voltage lateral MOSFET structure, when a high voltage is applied to the n ⁺ drain region,
The n ^- extended drain region is depleted from above and below.
Thus, n ^- when you try to further facilitate the depletion of the extended drain region, n ^- it is necessary to lower the impurity concentration of the extended drain region.

However, when the impurity concentration of the n ^- extended drain region is reduced, the resistance of this region increases. Eventually, the drain resistance of the high-withstand-voltage lateral MOSFET increases, and the driving capability of this transistor decreases. For this reason, there is a limit in reducing the on-resistance of the transistor.

Alternatively, depending on the device on which the high breakdown voltage lateral MOSFET is mounted, a high current operation may be required for the high breakdown voltage lateral MOSFET. In this case, in the conventional technique, there is a limit in reducing the resistance of the drain region for the above-described reason, and there has been a problem in the large-current operation of the high breakdown voltage lateral MOSFET.

An object of the present invention is to provide a high breakdown voltage lateral MOSFET.
The depletion of the extended drain region is further facilitated and its driving capability is enhanced. It is intended to solve the above problems.

[0012]

According to the present invention, there is provided a semiconductor device according to the present invention, comprising: a source region containing a high-concentration impurity of the opposite conductivity type formed in one region on a semiconductor substrate of one conductivity type; A gate electrode formed via a gate insulating film on the main surface, and a first diffusion region containing a low-concentration impurity of a reverse conductivity type formed opposite to the source region with the gate electrode interposed therebetween. A drain region containing a high-concentration impurity of the opposite conductivity type is formed on the surface of the first diffusion region, and one conductive region is provided between the gate electrode and the drain region and on the surface of the first diffusion region. A second diffusion region containing a low-concentration impurity in a mold is formed; a groove is formed between the gate electrode and the drain region at a predetermined depth from the surface of the first diffusion region; Third side wall containing one conductivity type impurity Diffusion regions are formed.

Here, the depth of the groove is set to be smaller than the depth of the first diffusion region.

Alternatively, in the semiconductor device according to the present invention, a reverse conductivity type epitaxial layer formed on a semiconductor substrate of one conductivity type, a back gate region formed in the epitaxial layer, and a back gate region formed in the back gate region. A source region containing a high-concentration impurity of the opposite conductivity type, a gate electrode formed on a surface of the back gate region via a gate insulating film, and formed facing the source region with the gate electrode interposed therebetween. A second diffusion region containing a low-concentration impurity of one conductivity type between the gate electrode and the drain region and having a surface portion of the epitaxial layer between the gate electrode and the drain region. Is formed, a groove is formed between the gate electrode and the drain region and at a predetermined depth from the surface of the epitaxial layer, and a one conductivity type is formed on a side wall of the groove. Third diffusion region containing an impurity is formed.

Here, the depth of the groove is set to be smaller than the thickness of the epitaxial layer.

The trench is filled with an insulating material containing one conductivity type impurity.

In the operation of the high breakdown voltage insulated gate field effect transistor, the source region, the semiconductor substrate, the second diffusion region and the third diffusion region are fixed to a ground potential, and a power supply voltage is applied to the drain region. Have been.

In the operation of the high-breakdown-voltage insulated gate field effect transistor, the first diffusion region is completely depleted.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1, FIG. 2, and FIG. 3 are for explaining the first embodiment of the present invention. Here, FIG. 1 is a plan view of the high breakdown voltage lateral MOSFET of the present invention, and FIG.
Is a cross-sectional view taken along the line AB shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line CD. The feature of the structure in this case is that n
^- a trench in the extended drain region, the side wall of the surrounding p
Forming a p-type diffusion layer on the surface of the n ^- extended drain region.

As shown in FIG. 1, an n ^- extended drain region 2 is formed on a p-type silicon substrate 1, and a plurality of trenches 3 are formed in this region. A buried BPSG is buried in the trench 3, and a side wall p-type diffusion layer 5 is formed around the buried BPSG. Also, the n ^- extended drain region 2
A p-type diffusion layer 6 is formed therein. Then, similarly to the conventional technique, a gate insulating film 8, a gate electrode 9, an n ⁺ source region 10, an n ⁺ drain region 11, a p ⁺ diffusion region 12, and the like are formed.

High-voltage lateral MOSF shown in FIGS. 2 and 3
ET is manufactured as follows. That is, a 450 nm silicon oxide film is formed on the surface of the p-type silicon substrate 1 having a resistivity of about 50 Ωcm by thermal oxidation at 950 ° C.
Phosphorus is selectively applied from the surface of the p-type silicon substrate 1 to a dose of 3 × by photolithography and ion implantation.
Ion implantation is performed at 10 ¹³ / cm ² and energy of 150 keV. Then, n ^- extended drain region 2 having a depth of about 6 μm as a first diffusion region is formed by heat treatment at 1200 ° C.

Next, the CVD oxide film is made to have a thickness of 300 nm by chemical vapor deposition (CVD), and the CVD oxide film is selectively anisotropically etched by a photolithography technique and a dry etching technique. Then, using the CVD oxide film as a mask, the p-type silicon substrate 1 is anisotropically etched to a depth of about 5 μm, and the trench 3 is formed as shown in FIG.
^- forming the extended drain region 2.

Next, BPSG (silicon oxide film containing boron glass and phosphorus glass) is CVD-formed to a thickness of 650 nm.
After regrowth by a heat treatment at 950 ° C. for about 30 minutes, the entire surface is etched back. Thereby, the inside of the trench 3 is filled with the buried BPSG 4. Then, a sidewall p-type diffusion layer 5 as a third diffusion region is formed around the trench 3 in the n ⁻ extension drain region 2 by boron diffusion from the buried BPSG 4.

Next, as shown in FIGS. 2 and 3, boron is selectively implanted from the surface of the p-type silicon substrate 1 at a dose of 2.times. By photolithography and ion implantation techniques.
Ion implantation is performed at 10 ¹² / cm ² and energy of 100 keV. As a result, the second surface of the n ^- extended drain region 2 is
A p-type diffusion layer 6 is formed as a diffusion region.

Next, a silicon oxide film is deposited to a thickness of 600 nm by a low pressure CVD method, and the silicon oxide film is selectively wet-etched by photolithography and dry etching to partially thicken the element isolation insulation. A film 7 is formed.

Next, a gate insulating film 8 having a thickness of about 50 nm is formed by performing thermal oxidation at a temperature of 950 ° C. in an H ₂ —O ₂ atmosphere for about 5 minutes. Then, the polysilicon film is 600 nm
Then, the polysilicon film is selectively anisotropically etched by a photolithography technique and a dry etching technique to form a gate electrode 9.

Next, arsenic is selectively doped at a dose of 5 × by photolithography and dry etching.
Ion implantation is performed at 10 ¹⁵ / cm ^{2 at} an energy of 70 keV to form an n ⁺ source region 10 and an n ⁺ drain region 11.

Next, boron is selectively doped by photolithography and ion implantation at a dose of 5 × 10 ¹⁵ / c.
Ions are implanted at m ² and energy of 50 keV to form ap ⁺ diffusion region 12. Next, BPSG is grown to a thickness of 1000 nm by CVD and reflowed by a heat treatment at 850 ° C. for about 30 minutes, and then selectively anisotropically etched by photolithography and dry etching to form an interlayer insulating film 13. And source / drain contact holes.

Next, an aluminum metal film is deposited to a thickness of about 1 μm by a vapor deposition method or a sputtering method, and this aluminum metal film is anisotropically etched by a dry etching technique to form a source electrode 14 and a drain electrode 15. I do. Thus, the high breakdown voltage lateral MOSFET of the present invention is formed.

In the structure of such a high-withstand-voltage lateral MOSFET, a pn junction between the p-type silicon substrate 1 and the p-type diffusion layer 6 is formed in the n ⁻ extension drain region 2 serving as a drain voltage relaxation region, ie, an electric field relaxation region. Side wall p around trench 3
A pn junction with the mold diffusion layer 5 is formed. Therefore, the n ⁻ extended drain region that could not be depleted by the pn junction from the p-type silicon substrate and the upper p-type diffusion layer is depleted, and the entire n ⁻ extended drain region can be easily depleted. . Even if the resistance of the n ^- extended drain region is made lower than that of the conventional case, the depletion layer can be extended to a distance where the voltage generated between the drain and the source can be reduced. FIG. 4 schematically shows the effect.

FIG. 4A shows the case of the present invention.
(B) shows the case of the second conventional example described above. here,
The impurity concentration is the same and the drain voltage is constant.

In the case of the present invention, as shown in FIG. 4A, the depletion layer formed in n ⁻
It is formed from the direction of the silicon substrate 1 and from the direction of the p-type diffusion layer 6. Further, the depletion of the n ⁻ extension drain region 2 is also performed between the plurality of side wall p-type diffusion layers 5 around the buried BPSG 4. On the other hand, in the case of the second conventional example, as shown in FIG. 4B, the depletion layer formed in the n ⁻ extension drain region 202 is formed on the p-type silicon substrate 2.
No. 01 and the direction of the p-type diffusion layer 203 only. Here, all the shaded regions are shown as depleted regions.

As a result, in the case of the present invention, the resistance in the n ^- extended drain region can be further reduced as compared with the case of the second conventional example, so that the high breakdown voltage lateral MOSF
It is possible to reduce the on-resistance between the drain and the source when the ET is on.

Next, a second embodiment of the present invention will be described with reference to FIG.
A description will be given based on FIG. 6 and FIG. Here, FIG. 5 is a plan view of the high breakdown voltage lateral MOSFET of the present invention, and FIG.
Is a cross-sectional view taken along the line EF shown in FIG. 5, and FIG. 7 is a cross-sectional view taken along the line GH.

In the first embodiment of the present invention, the n ^- extended drain region 2 serving as the electric field relaxation region is formed by ion implantation and impurity diffusion into the p-type silicon substrate 1 by high-temperature heat treatment. In the second embodiment, the electric field relaxation region is provided in a low-concentration impurity layer formed by epitaxial growth.

In the first embodiment, the channel region of the MOS transistor is the surface of the p-type silicon substrate 1, whereas in the second embodiment, the impurity diffusion called the p ⁺ back gate region is performed. The surface of the layer becomes the channel region.

The details will be described below. As shown in FIGS. 5, 6 and 7, n ^- epitaxial layer 22 is formed on p-type silicon substrate 21, and a plurality of trenches 23 are formed in this region. A buried BPSG 24 is buried in the trench 23, and a side wall p-type diffusion layer 25 is formed therearound. A p-type diffusion layer 26 is formed on the surface of n ⁻ epitaxial layer 22. Then, the p ⁺ back gate region 3 whose surface becomes a channel
0 is formed. In other respects, the element isolation insulating film 27, the gate insulating film 28, the gate electrode 2
9, an n ⁺ source region 31, an n ⁺ drain region 32, an interlayer insulating film 33, a source electrode 34, and a drain electrode 35 are formed.
ET is configured.

In this case, n ⁻ epitaxial layer 22
Are a p-type silicon substrate 21 and a p-type diffusion layer 2
6 and a pn junction with the sidewall p-type diffusion layer 25 around the trench 23 in the n ⁻ epitaxial layer 22. Therefore, similarly to the effect of the first embodiment, n ⁻
The entire area of the epitaxial layer 22 can be easily depleted. Then, even if the n ⁻ epitaxial layer has a lower resistivity than the conventional one, the depletion layer can be extended to a distance where the voltage generated between the drain and the source can be relaxed. As a result, since the resistance in the n ⁻ epitaxial layer 22 can be reduced, it is possible to reduce the drain-source resistance when the high breakdown voltage lateral MOSFET is turned on, as in the first embodiment.

[0039]

Structure of a high breakdown voltage lateral MOSFET of the present invention exhibits, n ^- extended drain region, a p-type silicon substrate, in addition to the pn junction between the p-type diffusion layer of the element upper, n ^- extended drain region It has a pn junction with the sidewall p-type diffusion layer around the trench.

Therefore, the p-type silicon substrate and the upper p
The n ⁻ extended drain region that could not be depleted only from the type diffusion layer can be depleted, and the entire n ⁻ extended drain region can be easily depleted. Then, even if the n ^- extended drain region has a lower resistivity than the conventional one, the depletion layer can be extended to a distance where the voltage generated between the drain and the source can be relaxed. For this reason, the resistance in the n ⁻ -extended drain region can be reduced, and the drain-source resistance when the high breakdown voltage lateral MOSFET is on, that is, the on-resistance can be reduced.

[0041] Such effects, n ^- instead of the extended drain region n ^- is also the same when the epitaxial layer is formed.

Further, since the current driving capability of the high-withstand-voltage lateral MOSFET is greatly improved, a high-withstand-voltage, large-current, high-withstand-voltage lateral MOSFET can be formed.

[Brief description of the drawings]

FIG. 1 shows a high-withstand-voltage lateral MOS according to a first embodiment of the present invention.
It is a top view of FET.

FIG. 2 is a cross-sectional view of the high breakdown voltage lateral MOSFET.

FIG. 3 is a sectional view of the high breakdown voltage lateral MOSFET.

FIG. 4 is a schematic sectional view for explaining the effect of the present invention.

FIG. 5 shows a high breakdown voltage lateral MOS according to a second embodiment of the present invention.
It is a top view of FET.

FIG. 6 shows a high breakdown voltage lateral MOS according to a second embodiment of the present invention.
It is sectional drawing of FET.

FIG. 7 shows a high breakdown voltage lateral MOS according to a second embodiment of the present invention.
It is sectional drawing of FET.

FIG. 8 shows a high withstand voltage horizontal type MO for explaining a first conventional example.
It is sectional drawing of SFET.

FIG. 9 is a high breakdown voltage horizontal MO for explaining a second conventional example.
It is a top view of SFET.

[Explanation of symbols]

1,101,201 p-type silicon substrate 2,102,202 n ^- extended drain region 3,23 trench 4,24 buried BPSG 5,25 sidewall p-type diffusion layer 6,26,103,203 p-type diffusion layer 7, 27,104 device isolation insulating film 8,28,105 gate insulating film 9,29,106,206 gate electrode 10,31,107,207 n ⁺ source region 11,32,108,208 n ⁺ drain region 12,109, 209 p ⁺ diffusion region 13, 33, 110 interlayer insulating film 14, 34, 111 source electrode 15, 35, 112 drain electrode 21 p-type silicon substrate 22 n ⁻ epitaxial layer 30 p ⁺ back gate region

Claims (7)

(57) [Claims] A source region containing a high-concentration impurity of opposite conductivity type formed in one region on a semiconductor substrate of one conductivity type; a gate electrode formed via a gate insulating film on a main surface of the semiconductor substrate; A first diffusion region containing a low-concentration impurity of a reverse conductivity type formed opposite to the source region with the gate electrode interposed therebetween, and a surface of the first diffusion region has a reverse conductivity type. A drain region containing a high-concentration impurity is formed, and a second diffusion region containing a one-conductivity-type low-concentration impurity is formed between the gate electrode and the drain region and on a surface of the first diffusion region. A groove is formed between the gate electrode and the drain region at a predetermined depth from the surface of the first diffusion region, and a third diffusion region containing one conductivity type impurity is formed on a side wall of the groove. Semiconductor device characterized by being formed . 2. The semiconductor device according to claim 1, wherein a depth of said groove is set to be smaller than a depth of said first diffusion region. 3. An epitaxial layer of a reverse conductivity type formed on a semiconductor substrate of one conductivity type, a back gate region formed in said epitaxial layer, and a high conductivity type of a reverse conductivity type formed in said back gate region. A source region containing a high-concentration impurity, a gate electrode formed on the surface of the back gate region via a gate insulating film, and a high-concentration reverse conductivity type formed opposite to the source region with the gate electrode interposed therebetween. A drain region containing an impurity, and a second diffusion region containing a low-concentration impurity of one conductivity type is formed between the gate electrode and the drain region and on a surface portion of the epitaxial layer; A groove is formed at a predetermined depth from the surface of the epitaxial layer between the gate electrode and the drain region, and a third diffusion region containing an impurity of one conductivity type is formed on a side wall of the groove. A semiconductor device characterized by being performed. 4. The semiconductor device according to claim 3, wherein a depth of said groove is set to be smaller than a thickness of said epitaxial layer. 5. The semiconductor device according to claim 1, wherein said trench is filled with an insulating material containing an impurity of one conductivity type. 6. In the operation of the high-breakdown-voltage insulated gate field effect transistor, the source region, the semiconductor substrate,
6. The device according to claim 1, wherein the second diffusion region and the third diffusion region are fixed to a ground potential, and a power supply voltage is applied to the drain region. 7. Semiconductor device. 7. The semiconductor device according to claim 6, wherein said first diffusion region is entirely depleted.