JP2941823B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2941823B2 JP2941823B2 JP63298386A JP29838688A JP2941823B2 JP 2941823 B2 JP2941823 B2 JP 2941823B2 JP 63298386 A JP63298386 A JP 63298386A JP 29838688 A JP29838688 A JP 29838688A JP 2941823 B2 JP2941823 B2 JP 2941823B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- groove
- opening
- insulating film
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に係り、特にいわゆ
る縦型の絶縁ゲート型（以下MISと略す）電界効果トラ
ンジスタ（以下FETと略す）を有する半導体装置の製造
方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a so-called vertical insulated gate (hereinafter abbreviated as MIS) field effect transistor (hereinafter abbreviated as FET). The present invention relates to a method for manufacturing a semiconductor device having the same.
従来、チャネルの電流が基板に対し縦に流れるいわゆ
る縦型のMISFETについては、特開昭58−3287及びアイ・
イー・デー・エム、テクニカル ダイジェスト、第674
頁〜第677頁（1987）（IDEM,Technical Digest pp.674
〜677（1987））に論じられている。前者に記載のMISFE
Tの断面図を第７図に示す。高濃度半導体基板１上にｎ
型ドレイン領域２、ｐ型ベース領域３、ｎ型ソース領域
４が順次形成され、上記ｎ型ソース領域４からｎ型ドレ
イン領域２に達するように形成された溝中にゲート絶縁
膜５を介してゲート電極６が埋め込まれている。７はソ
ース電極、８はドレイン電極、９はシリコン酸化膜であ
る。このMISFETは、チャネルの電流が縦に流れるため、
単位セル当りの電流密度が増大し、オン抵抗が減少して
いる。また、ソース領域がプレーナー型より小さく形成
されているので、ソースをエミッタとし、ドレイン領域
２とベース領域３とで構成される寄生バイポーラトラン
ジスタの動作が低く抑えられ、Ｌ負荷ラッチング耐量や
熱的破壊強度が向上した。Conventionally, a so-called vertical MISFET in which a channel current flows vertically to a substrate is disclosed in Japanese Patent Application Laid-Open No. 58-3287 and
EDM, Technical Digest, No. 674
Pp. 677 (1987) (IDEM, Technical Digest pp.674)
677 (1987)). MISFE described in the former
FIG. 7 shows a sectional view of T. N on the high concentration semiconductor substrate 1
A drain region 2, a p-type base region 3, and an n-type source region 4 are sequentially formed, and a gate insulating film 5 is interposed in a groove formed from the n-type source region 4 to the n-type drain region 2. The gate electrode 6 is buried. 7 is a source electrode, 8 is a drain electrode, and 9 is a silicon oxide film. In this MISFET, the channel current flows vertically,
The current density per unit cell increases, and the on-resistance decreases. In addition, since the source region is formed smaller than the planar type, the operation of the parasitic bipolar transistor including the source as the emitter and the drain region 2 and the base region 3 is suppressed, and the L load latching resistance and thermal breakdown are suppressed. Strength improved.
また、上述の従来技術の他に、特開昭63−224260号公
報に開示されている如き縦型のMOSFETが知られている。
しかし、そのMOSFETの場合、ソース電極の段切れが問題
となる。In addition to the above-mentioned prior art, a vertical MOSFET as disclosed in JP-A-63-224260 is also known.
However, in the case of the MOSFET, disconnection of the source electrode becomes a problem.
上記従来技術は、素子の信頼性について十分な配慮が
なされておらず、Ｌ負荷ラッチング耐量がなお不十分で
あるという問題があった。The prior art described above has a problem that sufficient consideration is not given to the reliability of the device, and the L load latching resistance is still insufficient.
本発明の目的は、Ｌ負荷ラッチング耐量の向上した信
頼性に優れた半導体装置の製造方法を提供することにあ
る。An object of the present invention is to provide a method for manufacturing a semiconductor device having improved L load latching resistance and excellent reliability.
上記目的を達成するために、本発明の半導体装置の製
造方法は、第１導電型の半導体基板主面に、第１導電型
であって、上記半導体基板の不純物濃度よりも低濃度の
半導体層が形成された半導体本体を準備する工程、上記
半導体層内に第２導電型の不純物を導入してチャネル領
域となる第１の領域を設ける工程、第１の領域主面上に
絶縁膜を形成する工程、この絶縁膜に第１開孔部を設
け、該第１開孔部を通して第１の領域に第２導電型の不
純物を導入して、底部が第１の領域の底部より深く、上
記半導体層内に位置した第２の領域を設ける工程、上記
絶縁膜に第２開孔部を設け、第２開孔部を通して第１の
領域に第１導電型の不純物を導入して、第２開孔部から
第１の領域に伸びる第３の領域を設ける工程、第２開孔
部内の第１の領域をエッチングし、第２の領域の底部よ
り浅く、第１の領域の底部より深い溝を形成する工程及
び溝内にゲート絶縁膜を介してゲート電極を設ける工程
を含むようにしたものである。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a method of manufacturing a semiconductor device, wherein a semiconductor layer of a first conductivity type having a lower concentration than an impurity concentration of the semiconductor substrate is provided on a main surface of a semiconductor substrate of the first conductivity type. Preparing a semiconductor body on which is formed, forming a first region serving as a channel region by introducing an impurity of a second conductivity type into the semiconductor layer, and forming an insulating film on a main surface of the first region Providing a first opening in the insulating film, introducing a second conductivity type impurity into the first region through the first opening, and making the bottom deeper than the bottom of the first region. Providing a second region located in the semiconductor layer, providing a second opening in the insulating film, introducing a first conductivity type impurity into the first region through the second opening, Providing a third region extending from the opening to the first region, and etching the first region in the second opening. And quenching, shallower than the bottom of the second region, in which to include the step of providing a gate electrode through a gate insulating film in step and the groove forming a deep trench from the bottom of the first region.
本発明は、前記第２の領域（後に説明する第１図の高
濃度ベース領域13）から下方に空乏層が延び、ブレーク
ダウンが発生する。そのためＬ負荷ラッチング耐量は向
上する。In the present invention, a depletion layer extends downward from the second region (the high-concentration base region 13 in FIG. 1 described later), and a breakdown occurs. Therefore, the L load withstand capability is improved.
以下、本発明の一実施例を第１図により説明する。第
１図は縦型パワーMOSFETの主要セル部の断面構造図であ
る。抵抗率が0.01Ω・cmのｎ形高濃度半導体基板１の上
に抵抗率が0.8Ω・cm、厚さが10μｍのｎ形エピタキシ
ャル層からなるドレイン領域２、その上にシート抵抗が
500Ω／□、深さが1.0μｍのｐ形ベース領域３が形成さ
れている。この領域は前記第１の領域に相当するが以下
ベース領域という。この領域の一部はｐ形の高濃度ベー
ス領域13が存在し、その深さは1.5μｍである、表面か
らドレイン領域２に達する溝中には、厚さ50nmのゲート
酸化膜５が周囲に設けられ、その中に多結晶シリコンの
ゲート電極６が設けられている。溝の外側上部には、溝
に接してシート抵抗が500Ω／□、深さが0.5μｍのｎ形
高濃度ソース領域４が設けられている。７はAlのソース
電極、８はTi−Ni−Agのドレイン電極そして９はシリコ
ン酸化膜である。Hereinafter, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a sectional structural view of a main cell portion of a vertical power MOSFET. A drain region 2 composed of an n-type epitaxial layer having a resistivity of 0.8 Ω · cm and a thickness of 10 μm is formed on an n-type high-concentration semiconductor substrate 1 having a resistivity of 0.01 Ω · cm.
A p-type base region 3 having a resistance of 500 Ω / □ and a depth of 1.0 μm is formed. This region corresponds to the first region, but is hereinafter referred to as a base region. A part of this region has a p-type high-concentration base region 13 having a depth of 1.5 μm. In a groove reaching the drain region 2 from the surface, a gate oxide film 5 having a thickness of 50 nm is formed around the trench. A polycrystalline silicon gate electrode 6 is provided therein. An n-type high-concentration source region 4 having a sheet resistance of 500Ω / □ and a depth of 0.5 μm is provided in contact with the groove at the upper portion outside the groove. 7 is an Al source electrode, 8 is a Ti-Ni-Ag drain electrode, and 9 is a silicon oxide film.
第２図はこの縦型パワーMOSFETの製造プロセスを示す
主要部の断面構造図である。（ａ）n+高濃度半導体基板
１の上にｎ形エピタキシャル層を成長させｐ型ベース領
域３を1.0μｍの深さに形成する。（ｂ）厚さ0.2μｍの
シリコン窒化膜10を所望のパターンに形成し、その上に
ホトレジスト103を所望のパターンに形成する。高エネ
ルギーイオン打ち込みによりＢを１×1015cm打ち込み、
ホトレジスト膜103を除去後熱処理によりＢを拡散し高
濃度ベース領域13を1.45μｍの深さ迄形成する。従って
この状態では（ｂ）に示した断面構造からホトレジスト
膜103が除かれた構造となっている。（ｃ）上記シリコ
ン窒化膜10の上にホトレジスト膜104を形成し、所望の
形状とする。開口部に１×1016/cmの砒素をイオン打ち
込みし、熱処理により、0.5μｍの深さにしてソース領
域４を形成する。（ｄ）しかる後、SiCl4ガスのドライ
エッチングにより、深さ1.1μｍのＵ字形溝11を形成す
る。このときシリコン窒化膜の削れ量は約0.1μｍであ
る。（ｅ）そして厚さ50nmのシリコン酸化膜をゲート絶
縁膜５としてCVD法により被着する。（ｆ）ゲート電極
６となる多結晶シリコンを溝幅の２分の１以上の膜厚で
被着して溝を充填した後、SF6ガスのドライエッチング
により全面エッチングして溝内のみに図のごとく多結晶
シリコンを残存させる。なお多結晶シリコンは燐を５×
1020/cm3の濃度にドープして低抵抗にしておく。燐や砒
素を多結晶シリコン被着時に添加しておいてもよい。
（ｇ）熱酸化によってシリコン酸化膜９を図のごとく形
成し、シリコン窒化膜10を除去する。（ｈ）取り出し電
極として、ソース電極７及びドレイン電極８を形成す
る。FIG. 2 is a sectional structural view of a main part showing a manufacturing process of the vertical power MOSFET. (A) An n-type epitaxial layer is grown on an n + high-concentration semiconductor substrate 1 to form a p-type base region 3 at a depth of 1.0 μm. (B) A silicon nitride film 10 having a thickness of 0.2 μm is formed in a desired pattern, and a photoresist 103 is formed thereon in a desired pattern. B was implanted at 1 × 10 15 cm by high energy ion implantation,
After removing the photoresist film 103, B is diffused by heat treatment to form a high concentration base region 13 to a depth of 1.45 μm. Therefore, in this state, the photoresist film 103 is removed from the cross-sectional structure shown in FIG. (C) A photoresist film 104 is formed on the silicon nitride film 10 to have a desired shape. Arsenic of 1 × 10 16 / cm is ion-implanted into the opening, and the source region 4 is formed to a depth of 0.5 μm by heat treatment. (D) Thereafter, a 1.1 μm deep U-shaped groove 11 is formed by dry etching of SiCl 4 gas. At this time, the shaved amount of the silicon nitride film is about 0.1 μm. (E) Then, a silicon oxide film having a thickness of 50 nm is deposited as a gate insulating film 5 by a CVD method. (F) Polycrystalline silicon to be the gate electrode 6 is applied with a film thickness of at least half the groove width to fill the groove, and then the entire surface is etched by dry etching with SF 6 gas so that only the inside of the groove is formed. The polycrystalline silicon is left as described above. For polycrystalline silicon, phosphorus is 5 ×
It is doped to a concentration of 10 20 / cm 3 to keep low resistance. Phosphorus or arsenic may be added during polycrystalline silicon deposition.
(G) A silicon oxide film 9 is formed by thermal oxidation as shown in the figure, and the silicon nitride film 10 is removed. (H) A source electrode 7 and a drain electrode 8 are formed as extraction electrodes.
本実施例の構造は、ソース領域４がゲート電極６を有
するＵ字形溝形成によって自己整合的に小さく形成され
ていることである。これにより、ソース領域４の断面形
状における幅すなわち横方向の長さは、深さすなわち縦
方向の長さより短く形成できるので、ソースをエミッタ
としベース領域３とドレイン領域２とで構成される寄生
バイポーラトランジスタ動作が低く抑えられる。また高
濃度ベース領域13が深部迄導入されているので、ドレイ
ン・ベース間のブレークダウンはこの領域の底部発生す
る。その結果ドレイン耐圧は65Vに低下したがＬ負荷ラ
ッチングは向上した。The structure of the present embodiment is that the source region 4 is formed small in a self-aligned manner by forming a U-shaped groove having the gate electrode 6. Thus, the width of the cross-sectional shape of the source region 4, that is, the length in the horizontal direction can be formed shorter than the depth, that is, the length in the vertical direction. Therefore, a parasitic bipolar transistor composed of the base region 3 and the drain region 2 using the source as the emitter. Transistor operation can be kept low. Also, since the high concentration base region 13 is introduced to a deep portion, breakdown between the drain and the base occurs at the bottom of this region. As a result, the drain withstand voltage was reduced to 65 V, but the L load latching was improved.
本実施例によれば、3.5mm□チップのパワーMOSFETに
おいてドレイン耐圧が60V、オン抵抗が10mΩ、Ｌ負荷ラ
ッチング耐量が100μＨ、50Vに対して35Aでも破壊しな
かった。According to this example, the power MOSFET of the 3.5 mm square chip did not break down even at a drain withstand voltage of 60 V, an on-resistance of 10 mΩ, an L load latching resistance of 100 μH, and 35 A at 50 V.
次に本発明の他の実施例を第３図を用いて説明する。
第３図（ａ）はパワーMOSFETの主要部の平面図、第３図
（ｂ）は同図（ａ）のＡ−Ａ′断面図である。全面にソ
ース電極に接続されたソース領域４及びベース領域３の
平面形状はそれぞれ円環形状である。ここで一セルのゲ
ート絶縁膜５の直径は３μｍである。またソース領域４
の幅はゲート電極６を有するＵ字形溝部分によって自己
整合されて一様の大きさになっているので、全面ソース
電極７に接続されたベース領域３の大きさにも一定に確
保される。この結果ベース抵抗は小さく抑えられ、寄生
バイポーラトランジスタ動作も発生しにくい。Next, another embodiment of the present invention will be described with reference to FIG.
FIG. 3 (a) is a plan view of a main part of the power MOSFET, and FIG. 3 (b) is a sectional view taken along the line AA 'of FIG. 3 (a). The planar shape of each of the source region 4 and the base region 3 connected to the source electrode over the entire surface is an annular shape. Here, the diameter of the gate insulating film 5 of one cell is 3 μm. Source region 4
Is self-aligned by the U-shaped groove portion having the gate electrode 6 and has a uniform size, so that the size of the base region 3 connected to the entire source electrode 7 is also kept constant. As a result, the base resistance is kept small, and the operation of the parasitic bipolar transistor hardly occurs.
次に本発明の他の実施例を第４図を用いて説明する。
図はパワーMOSFETの主要部の平面図であり、ソース領域
４の平面形状が円環の一部の形状をしている。ゲート絶
縁膜として厚さ60nmの酸化タンタル膜と厚さ20nmのシリ
コ酸化膜の複合膜を用いた。その結果単位面積当りのゲ
ート幅つまり実装密度が約２倍向上し、またゲート面積
が増加したにもかかわらず、歩留まりの低下はみられな
かった。Next, another embodiment of the present invention will be described with reference to FIG.
The figure is a plan view of a main part of the power MOSFET, and the planar shape of the source region 4 is a part of an annular shape. A composite film of a tantalum oxide film having a thickness of 60 nm and a silicon oxide film having a thickness of 20 nm was used as a gate insulating film. As a result, the gate width per unit area, that is, the mounting density was improved about twice, and the yield did not decrease even though the gate area increased.
次に本発明の他の実施例を第５図を用いて説明する。
図はパワーMOSFETの主要部の断面図であり、ベース領域
３にライフタイムキラー12が導入されている。このライ
フタイムキラー12は１×1015/cm2のプロトンのイオン打
ち込みによって形成された。この結果、寄生バイポーラ
トランジスタ動作の発生がさらに低く抑えられ、またド
レイン・ベース間のダイオードの逆回復時間も約１桁低
減できた。Next, another embodiment of the present invention will be described with reference to FIG.
The figure is a cross-sectional view of a main part of the power MOSFET, and a lifetime killer 12 is introduced in the base region 3. This lifetime killer 12 was formed by ion implantation of 1 × 10 15 / cm 2 protons. As a result, the occurrence of the parasitic bipolar transistor operation was further suppressed, and the reverse recovery time of the diode between the drain and the base was reduced by about one digit.
次に本発明の他の実施例を第６図を用いて説明する。
第６図（ａ）はパワーMOSFET、ドライバMOSFETからなる
回路図、第６図（ｂ）はその集積回路の断面図である。
ｐ形半導体基板14上にｎ形高濃度領域15をドレインとす
るパワーMOSFET及びドライバMOSFETが形成され、アイソ
レーション17もＵ字形溝構造を利用して形成されてい
る。この結果、パワーMOSFETのドライブが容易になると
共に、実装密度は従来の構造の約２倍向上し、かつ破壊
耐量も低下することはなかった。Next, another embodiment of the present invention will be described with reference to FIG.
FIG. 6A is a circuit diagram including a power MOSFET and a driver MOSFET, and FIG. 6B is a cross-sectional view of the integrated circuit.
A power MOSFET and a driver MOSFET having an n-type high-concentration region 15 as a drain are formed on a p-type semiconductor substrate 14, and an isolation 17 is also formed using a U-shaped groove structure. As a result, the drive of the power MOSFET is facilitated, the mounting density is improved about twice that of the conventional structure, and the breakdown strength is not reduced.
以上の実施例ではｎチャネルパワーMOSFETを例にとっ
て説明したが、ｐチャネル形でも同様な効果がある。ま
たゲート絶縁膜としてシリコン酸化膜及び酸化タンタル
膜を含む高誘電率複合膜を用いたが他の高誘電率複合
膜、例えば酸化チタン膜、オキシナイトライド膜、酸化
イットリウム膜を含む膜等でもよく、そしてゲート電極
として多結晶シリコンを用いたが、他の材料、例えば、
アルミニウム、タングステン、モリブデン、タングステ
ンシリサイド、モリブデンシリサイド、又はチタンシリ
サイドでも本発明の思想を逸脱しない限りにおいて変更
可能である。Although the above embodiment has been described with reference to an n-channel power MOSFET as an example, a p-channel type has the same effect. Although a high dielectric constant composite film including a silicon oxide film and a tantalum oxide film was used as the gate insulating film, other high dielectric constant composite films, for example, a film including a titanium oxide film, an oxynitride film, and a yttrium oxide film may be used. , And polycrystalline silicon as the gate electrode, but other materials, for example,
Aluminum, tungsten, molybdenum, tungsten silicide, molybdenum silicide, or titanium silicide can be changed without departing from the spirit of the present invention.
本発明によれば、Ｌ負荷ラッチング耐量の向上した信
頼性に優れた半導体装置の製造方法を提供することがで
きた。According to the present invention, it is possible to provide a method of manufacturing a semiconductor device having improved L load latching resistance and excellent reliability.
第１図は本発明の一実施例の縦型パワーMOSFETの主要部
の縦断面図、第２図はその製造プロセスを示す主要部の
縦断面図、第３図は本発明の他の実施例の縦型パワーMO
SFETの主要部の平面図及び縦断面図、第４図は本発明の
他の実施例の縦型パワーMOSFETの主要部の平面図、第５
図は本発明の他の実施例の縦型パワーMOSFETの主要部の
縦断面図、第６図は本発明の他の実施例の回路図及びそ
の主要部の縦断面図、第７図は従来の縦型パワーMOSFET
の主要部の縦断面図である。 １……高濃度半導体基板 ２……ドレイン領域、３……ベース領域 ４……ソース領域、５……ゲート絶縁膜 ６……ゲート電極、７……ソース電極 ８……ドレイン電極、９……絶縁膜 10……シリコン窒化膜、11……溝 12……ライフタイムキラー 13……高濃度ベース領域 14……ｐ形半導体基板 15……ｎ形高濃度領域 16……ドレイン取り出し領域 17……アイソレーション 18……保護膜 103、104……ホトレジスト膜1 is a longitudinal sectional view of a main part of a vertical power MOSFET according to one embodiment of the present invention, FIG. 2 is a longitudinal sectional view of a main part showing a manufacturing process thereof, and FIG. 3 is another embodiment of the present invention. Vertical power MO
FIG. 4 is a plan view and a longitudinal sectional view of a main part of an SFET. FIG. 4 is a plan view of a main part of a vertical power MOSFET according to another embodiment of the present invention.
FIG. 6 is a longitudinal sectional view of a main part of a vertical power MOSFET according to another embodiment of the present invention. FIG. 6 is a circuit diagram and a longitudinal sectional view of the main part of another embodiment of the present invention. Vertical power MOSFET
3 is a longitudinal sectional view of a main part of FIG. DESCRIPTION OF SYMBOLS 1 ... High-concentration semiconductor substrate 2 ... Drain region, 3 ... Base region 4 ... Source region, 5 ... Gate insulating film 6 ... Gate electrode, 7 ... Source electrode 8 ... Drain electrode, 9 ... Insulating film 10 Silicon nitride film 11 Groove 12 Lifetime killer 13 High-concentration base region 14 P-type semiconductor substrate 15 N-type high-concentration region 16 Drain extraction region 17 Isolation 18: Protective film 103, 104: Photoresist film
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−155768（ＪＰ，Ａ) 実開 昭63−124762（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 29/78 ────────────────────────────────────────────────── (5) References JP-A-63-155768 (JP, A) JP-A-63-124762 (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 29/78
Claims (2)
型であって、上記半導体基板の不純物濃度よりも低濃度
の半導体層が形成された半導体本体を準備する工程、 上記半導体層内に第２導電型の不純物を導入してチャネ
ル領域となる第１の領域を設ける工程、 上記第１の領域主面上に絶縁膜を形成する工程、 上記絶縁膜に第１開孔部を設け、該第１開孔部を通して
上記第１の領域に第２導電型の不純物を導入して、底部
が上記第１の領域の底部より深く、上記半導体層内に位
置した第２の領域を設ける工程、 上記絶縁膜に第２開孔部を設け、該第２開孔部を通して
上記第１の領域に第１導電型の不純物を導入して、上記
第２開孔部から上記第１の領域に伸びる第３の領域を設
ける工程、 上記第２開孔部内の上記第１の領域をエッチングし、上
記第２の領域の底部より浅く、上記第１の領域の底部よ
り深い溝を形成する工程及び 上記溝内にゲート絶縁膜を介してゲート電極を設ける工
程を含むことを特徴とする半導体装置の製造方法。A step of preparing a semiconductor body having a semiconductor layer of a first conductivity type formed on a main surface of a semiconductor substrate of the first conductivity type and having a lower concentration than an impurity concentration of the semiconductor substrate; A step of introducing a second conductivity type impurity into the layer to provide a first region serving as a channel region; a step of forming an insulating film on the main surface of the first region; a first opening in the insulating film A second conductivity type impurity is introduced into the first region through the first opening, and the second region is located in the semiconductor layer, the bottom being deeper than the bottom of the first region. Providing a second opening in the insulating film, introducing a first conductivity type impurity into the first region through the second opening, and removing the first conductive type impurity from the second opening. Providing a third region extending in the region of the above, etching the first region in the second opening portion Forming a groove shallower than the bottom of the second region and deeper than the bottom of the first region; and providing a gate electrode in the groove via a gate insulating film. Manufacturing method.
幅の２分の１以上の膜厚で多結晶シリコンを上記溝に充
填し、しかる後上記多結晶シリコンをエッチングして上
記溝のみに残存させる工程からなり、 上記ゲート電極を設ける工程に続いて、上記ゲート電極
表面に酸化膜を形成する工程と、該酸化膜上に上記第２
及び第３の領域に接続するソース電極を形成する工程を
備えたことを特徴とする請求項１記載の半導体装置の製
造方法。2. The step of providing said gate electrode, said step of filling said groove with polycrystalline silicon having a thickness of at least half the width of said groove, and then etching said polycrystalline silicon to form only said groove A step of forming an oxide film on the surface of the gate electrode, a step of forming an oxide film on the surface of the gate electrode,
2. The method according to claim 1, further comprising the step of forming a source electrode connected to the third region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298386A JP2941823B2 (en) | 1988-11-28 | 1988-11-28 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298386A JP2941823B2 (en) | 1988-11-28 | 1988-11-28 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02144971A JPH02144971A (en) | 1990-06-04 |
| JP2941823B2 true JP2941823B2 (en) | 1999-08-30 |
Family
ID=17859028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63298386A Expired - Fee Related JP2941823B2 (en) | 1988-11-28 | 1988-11-28 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2941823B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2689606B2 (en) * | 1989-05-24 | 1997-12-10 | 富士電機株式会社 | Method for manufacturing insulated gate field effect transistor |
| JP2582724Y2 (en) * | 1991-10-08 | 1998-10-08 | 株式会社明電舎 | Insulated gate type semiconductor device |
| JP2837014B2 (en) * | 1992-02-17 | 1998-12-14 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP4521643B2 (en) * | 1997-05-07 | 2010-08-11 | シリコニックス・インコーポレイテッド | Fabrication of high density trench DMOS using sidewall spacers |
| US6351009B1 (en) | 1999-03-01 | 2002-02-26 | Fairchild Semiconductor Corporation | MOS-gated device having a buried gate and process for forming same |
| JP4528460B2 (en) * | 2000-06-30 | 2010-08-18 | 株式会社東芝 | Semiconductor element |
| JP2002329727A (en) * | 2001-04-27 | 2002-11-15 | Toyota Motor Corp | Vertical semiconductor device and circuit using it |
| JP5008046B2 (en) * | 2005-06-14 | 2012-08-22 | ローム株式会社 | Semiconductor device |
| US8643071B2 (en) * | 2012-06-14 | 2014-02-04 | Alpha And Omega Semiconductor Incorporated | Integrated snubber in a single poly MOSFET |
| JP6988175B2 (en) * | 2017-06-09 | 2022-01-05 | 富士電機株式会社 | Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020559A (en) * | 1983-07-15 | 1985-02-01 | Hitachi Ltd | Composite semiconductor device |
| JPS6180859A (en) * | 1984-09-28 | 1986-04-24 | Hitachi Ltd | Power mosfet |
| JPS62298120A (en) * | 1986-06-18 | 1987-12-25 | Hitachi Ltd | Semicionductor device and manufacture thereof |
| JPS63124762U (en) * | 1987-02-04 | 1988-08-15 |
-
1988
- 1988-11-28 JP JP63298386A patent/JP2941823B2/en not_active Expired - Fee Related
Also Published As
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| JPH02144971A (en) | 1990-06-04 |
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