JPH06318714A - High-breakdown voltage semiconductor element - Google Patents

Abstract

PURPOSE:To provide a semiconductor element which is enabled to obtain a sufficiently high breakdown voltage with a thin active layer and has a dielectric separating structure. CONSTITUTION:This semiconductor element has an active layer 13 composed of a high-resistance n<->-type silicon layer formed on a semiconductor substrate 10 with a silicon oxide layer 11 in-between and an N-and p-type impurity layers 14 and 13 at prescribed distances from the layer 12. The layer 14 is formed of two or more diffusion layers 14a, 14b, and 14c with diffusion windows having different widths and diffusion depths and, at the same time, the layer 14 is formed to such a depth that the layer 14 can reach the silicon oxide film 11. In addition, a high-resistance film 18 is formed on the active layer 12 between the layers 13 and 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor element having a dielectric isolation structure, and more particularly to a high breakdown voltage semiconductor element with an improved diffusion layer shape.

[0002]

2. Description of the Related Art Conventionally, various high breakdown voltage semiconductor devices using a dielectric isolation structure have been proposed. FIG. 51 shows a conventional example of a lateral high breakdown voltage diode using a dielectric isolation structure. An n ⁻ type silicon layer (active layer) 3 is formed on a semiconductor substrate 1 with an isolation insulating film 2 interposed therebetween. In addition, the active layer 3
A p-type anode layer 5 and an n-type cathode layer 6 separated from the p-type anode layer 5 by a predetermined distance are formed on the surface of, and an anode electrode 7 and a cathode electrode 8 are formed on each.

In such a lateral diode, for example, consider a reverse bias state in which the substrate 1 and the anode electrode 7 are grounded, and a positive voltage is applied to the cathode electrode 8. At this time, the voltage applied to the n-type cathode layer 6 is shared by the depletion layer spreading in the active layer 3 below the n-type cathode layer 6 and the isolation insulating film 2. Therefore, when the thickness of the active layer portion under the n-type cathode layer 6 is thin, a large electric field is shared here, and electric field concentration occurs at the edge portion (near the curved surface portion of the bottom portion) of the n-type cathode layer 6, Avalanche breakdown occurs at low applied voltage. In order to avoid this and realize a sufficiently high breakdown voltage, conventionally, the thickness of the active layer 3 has been set to 20 μm or more.

However, if the thickness of the active layer is large, V
When element isolation is performed in the lateral direction using a groove or the like, a deep isolation groove is required, and the area of the isolation groove region becomes large. Therefore, not only the processing becomes difficult, but also the effective area of the element on the wafer becomes small, and as a result, the cost of the integrated circuit of the high breakdown voltage element increases.

On the other hand, the dielectric isolation structure enables the high breakdown voltage element and the logic circuit to be formed on the same substrate.
In that case, according to the SOI (Silicon on insulator) technique of forming an element in a semiconductor layer (active layer) formed on an insulating film, a high breakdown voltage element and a logic circuit can be completely separated.

It is known that in a semiconductor device using such an SOI substrate, even if the thickness of the active layer is reduced to 0.3 μm or less, a high breakdown voltage can be obtained in the vertical direction because of the insulating film. In addition, since element isolation can be performed using the trench groove, this element isolation structure is a powerful structure in power ICs.

However, when the active layer is thin as described above, the impurity doping concentration of the n drift region in the active layer must be lowered in order to increase the lateral withstand voltage. The length of the n drift region of 200 μm or more is required. In order to avoid this, for example, FIG.
As shown in, the SIPOS (semi
a method for making the electric field strength in the lateral direction uniform by forming a -insulating silicon layer 18;
As disclosed in Japanese Patent Application Laid-Open No. 4-309234, a method of forming a linear doping concentration distribution in the lateral direction can be considered. However, these methods require special steps and are difficult to implement.

[0008]

As described above, in the conventional high breakdown voltage semiconductor element having the dielectric isolation structure, a sufficient breakdown voltage cannot be obtained when the active layer is thin, and lateral element isolation is caused when the active layer is thickened. There was a problem that it became difficult.

In the drift region, if the active layer is thin, the impurity doping concentration of the n drift region in the active layer must be lowered in order to increase the lateral breakdown voltage. However, it is necessary to increase the length of the n drift region, which makes it difficult to miniaturize the device.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a high breakdown voltage semiconductor device having a dielectric isolation structure capable of obtaining a sufficiently high breakdown voltage characteristic with a thin active layer. To provide.

Another object of the present invention is to provide a high withstand voltage semiconductor element having a dielectric isolation structure which can obtain a sufficiently high withstand voltage characteristic without increasing the length of the drift region.

[0012]

The essence of the present invention is to relieve the electric field concentration at the edge portion (especially near the curved surface portion of the bottom) of the diffusion layer by devising the shape of the diffusion layer.

That is, a first aspect of the invention is to form an active layer made of a high-resistance first-conductivity-type semiconductor on a semiconductor substrate via an insulating film, and to form a first conductive-type impurity layer at a predetermined distance from the active layer. And a high withstand voltage semiconductor element in which an impurity layer of the second conductivity type is formed, the impurity layer of the first conductivity type is formed of a double or more diffusion layer in which at least one of the width and the diffusion depth of the diffusion window is different. It is characterized by

The following are preferred embodiments of the first invention.

(1) An impurity layer of the first conductivity type and a second conductivity type is formed to a depth reaching the insulating film. (2) Between the impurity layers of the first conductivity type and the second conductivity type,
A high resistance film is formed on the active layer.

(3) The total amount of impurities in the active layer is 1 × 10 ¹⁰ c
It is set within the range of m ^{−2 to} 2 × 10 ¹² cm ⁻² .

A second invention is a high breakdown voltage semiconductor comprising a semiconductor substrate and an active layer formed on the semiconductor substrate via an insulating film and made of a high resistance semiconductor and having a thickness of 0.3 μm or less. In the device, the active layer has a stepwise distribution of impurity concentration distribution in the lateral direction of 2 to 10 steps, each having a Gaussian distribution, and an interval between the steps is twice or more a diffusion length. .

[0018]

[Operation] In a high breakdown voltage semiconductor element having a dielectric isolation structure,
It is assumed that a high voltage, which is a reverse bias, is applied to the first conductivity type impurity layer while the second conductivity type impurity layer and the substrate are grounded. At this time, the voltage applied to the first conductivity type impurity layer is vertically shared by the active layer and the insulating film. Here, if electric field concentration occurs near the curved surface of the bottom of the first conductivity type impurity layer, avalanche breakdown occurs at a low voltage.

According to the first aspect of the present invention, the impurity layer of the first conductivity type is formed in the double or more diffusion layers while changing the width and the diffusion depth of the diffusion window, so that the diffusion layer bottom portion near the curved surface portion is formed. The electric field concentration can be relaxed. That is, the electric field concentration inside the active layer, particularly the electric field concentration near the curved surface of the bottom of the diffusion layer can be alleviated, and an unprecedented high breakdown voltage element can be realized. Furthermore, since the thickness of the active layer can be reduced, lateral element isolation is facilitated.

Further, by forming the impurity layers of the first conductivity type and the second conductivity type to the depth reaching the insulating film, the voltage applied to the impurity layer of the first conductivity type can be shared only by the insulating film. Therefore, the vertical electric field of the active layer can be suppressed small. Further, by providing the high resistance film on the surface of the active layer, the lateral potential distribution on the surface of the active layer can be made uniform according to the uniform potential distribution formed in the film. As a result, the electric field concentration inside the active layer can be effectively mitigated, and it is possible to realize a thin and high withstand voltage element which has not been heretofore available.

In the second invention, the general impurity diffusion technique is carried out a plurality of times to make the lateral concentration distribution of the active layer stepwise, so that the active layer has a thickness of 0.3 μm.
Even in the following cases, there is provided a dielectric isolation semiconductor element capable of achieving a high breakdown voltage without increasing the length of the drift region.

It is considered that the dielectric isolation semiconductor element according to the second invention exhibits a high breakdown voltage based on the following principle.

The horizontal direction is the x-axis and the vertical direction is the y-axis. When the thickness of the active layer is 0.3 μm or less, it is considered that the impurity concentration distribution in the vertical direction when the impurities are diffused is almost uniform. Therefore, assuming that the lateral impurity concentration distribution is a Gaussian distribution, it is given by the following equation.

[0024] n (x, y) = n o exp (-x 2 / a 2) wherein a is the diffusion length ^{_{(a = 2D t 1/2, n}} 0 represents the difference of the impurity concentration in the stepped portion. The Then, the maximum value Δn _max of the concentration gradient is obtained at x = a · 2 ^−1/2 ,
It becomes as shown in the following formula.

[0025] _{Δn max = | dn / dx (} x = a -1/2 | = | -2 × exp (-1/2) × n 0 / a | = 0.85776 × n 0 / a transverse and longitudinal The electric field strength in the direction is obtained by solving the Poisson equation: n (x) = (ε _s / q) (d
E _x / d _x + dE _y / d _y ) Here, ε _s is the dielectric constant with respect to Si, and q is the elementary charge.
In order to obtain the avalanche breakdown voltage of the device, ionization integration is performed as shown in Equation 2 below.

I = ∫α (E) dX where α (E) is an ionization coefficient, which is obtained by the following equation.

Α (E) = A · exp (−B / E) where A and B are constants. Generally, Poisson's equation and ionization integral cannot be analytically obtained,
Perform numerical calculations. As a result, it was found that n ₀ and a have a relationship represented by the following equation.

N ₀ / a ^1/2 ≤1 × 10 ¹⁹ Therefore, the maximum value Δn _max of the concentration gradient must satisfy the following equation.

Δn _max ≦ 0.85776 × 10 ¹⁹ / a ^1/2 On the other hand, in the step portion of the stairs, the electric field strength in the lateral direction is much smaller than that in the step portion, so it is better to reduce the interval between the steps. However, if the stairs are too close,
Interference occurs between adjacent stairs and the electric field becomes strong. Therefore, the interval between the steps should be twice or more, preferably about 3 to 4 times the diffusion length.

FIG. 52 shows the breakdown voltage when the diffusion length is changed, and FIG. 53 shows the breakdown voltage when the diffusion number is changed. From these figures, according to the sixth aspect of the present invention, it is possible to realize a dielectric isolation semiconductor element having a high breakdown voltage without increasing the length of the drift region.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the element structure of a high breakdown voltage diode according to the first embodiment of the present invention. An n ⁻ type high resistance silicon layer (active layer) 12 is formed on a silicon substrate 10 with a silicon oxide film (isolation insulating film) 11 interposed therebetween. This structure is formed, for example, by forming a silicon oxide film 11 on the surface of a silicon substrate 10, directly adhering another silicon substrate having a mirror-polished surface to the silicon oxide film 11, and thinning the substrate. The silicon oxide film 11 has a thickness of about 1 to 5 μm. The n ⁻ type active layer 12 has a total impurity amount of 1 × 10 ¹⁰ cm ⁻² to 2 × 10 ¹² c.
m ⁻² , more preferably 0.5 to 1.8 × 10 ¹² c
The thickness is set in the range of m ⁻² and the thickness thereof is set to about 10 μm.

A p-type anode layer 13 and an n-type cathode layer 14 are formed on the active layer 12 at a predetermined distance. p
The type anode layer 13 and the n-type cathode layer 14 are diffused to a depth reaching the silicon oxide film 11 at the bottom of the active layer as shown in the figure. Further, the n-type cathode layer 14 is formed by changing the width and the diffusion depth of the diffusion window so as to form the triple diffusion layers 14a and 14a.
b and 14c. The total amount of impurities in the diffusion layers other than 14a, that is, the diffusion layers 14b and 14c here is 1 × 10.
^It is set in the range of ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ⁻² . An anode electrode 15 and a cathode electrode 16 are formed on the p-type anode layer 13 and the n-type cathode layer 14, respectively. A high resistance film 18 is provided on the active layer 12 between the electrodes 15 and 16 with a silicon oxide film 17 interposed therebetween. The high resistance film 18 is, for example, a SIPOS (Semi-Insul)
ating Polycrystalline Silicom), and both ends of the high resistance film 18 are connected to the electrodes 15 and 16, respectively. The surface of the high resistance film 18 is covered with a silicon oxide film 19 as a protective film.

Consider the case where the p-type anode layer 13 and the substrate 10 are grounded and a positive high voltage is applied to the n-type cathode layer 14 in such a structure. Since the n-type cathode layer 14 is formed to a depth reaching the bottom of the active layer, all the voltage applied to the n-type cathode layer 14 is shared by the silicon oxide film 11 in the vertical direction. Here, the silicon oxide film 11 has a sufficiently higher breakdown voltage than the active layer 12.

Further, depending on the voltage between the anode and the cathode,
A minute current flows through the high resistance film 18 formed on the surface of the active layer 12 to form a uniform potential distribution in the lateral direction.
Due to the influence of the potential distribution in the high resistance film 18, a uniform potential distribution is formed in the lateral direction also on the surface of the active layer immediately below the high resistance film. Furthermore, by diffusing the n-type cathode layer 14 in three layers, the impurity concentration gradient at the curved surface portion at the bottom of the diffusion layer is alleviated, and this influence widens the equipotential lines and prevents extreme electric field concentration. As a result, the electric field concentration inside the element is relaxed and a high breakdown voltage is realized.

In the above structure, when the total amount of impurities in the active layer 12 is changed, the breakdown voltage also changes. FIG. 23
FIG. 4 is a characteristic diagram showing the relationship between the total amount of impurities in the active layer 12 and the breakdown voltage. When the total amount of impurities is 1 × 10 ¹⁰ cm ⁻² or more, the higher the total amount of impurities is, the higher the breakdown voltage becomes, and when the total amount of impurities exceeds 3 × 10 ¹² cm ⁻² , the breakdown voltage sharply decreases. Therefore, the total amount of impurities in the active layer 12 is 1 × 10 ¹⁰ cm
The range of ^{−2 to} 2 × 10 ¹² cm ⁻² is desirable.

As described above, according to this embodiment, the n-type cathode layer 14 is formed by triple diffusion and is formed to a depth reaching the silicon oxide film 11, and the high resistance film 18 is further formed on the active layer 12. By forming the above, the electric field concentration inside the element can be relaxed, and a high breakdown voltage diode can be realized even if the active layer 12 is thinned.

Modifications of the first embodiment are shown in FIGS. In FIG. 2, the p-type anode layer 13 is formed shallower than the silicon oxide film 11 in the first embodiment. In FIG. 3, the n-type cathode layer 14 is formed shallower than the silicon oxide film 11. In FIG. 4, the p-type anode layer 13 and the n-type cathode layer 14 are both formed shallower than the silicon oxide film 11. Even with such a configuration, electric field concentration at the edge portion of the n-type cathode layer 14 is alleviated, so that the same effect as that of the first embodiment can be obtained.

In FIG. 5, the depth of the n-type cathode layer 14 is constant at the depth reaching the silicon oxide film 11, and the length of the lateral diffusion window in triple diffusion is changed. Here, the impurity concentrations of 14a, 14b, and 14c are sequentially reduced. Even with such a configuration, it is possible to prevent extreme electric field concentration by expanding the interval between the equipotential lines in the lateral direction, and the same effect as in the first embodiment can be obtained. In addition, instead of performing multiple diffusions with different impurity concentrations,
The impurity concentration may be continuously changed.

FIG. 6 applies the idea of FIG. 2 in addition to the configuration of FIG. FIG. 7 shows the n-type cathode layer 14 as three layers.
It is formed by double diffusion instead of double diffusion.

In FIG. 8, the high resistance film 18 is formed on the electrodes 15 and 16.
In addition, it is directly connected to the p-type anode layer 13 and the n-type cathode layer 14. In FIG. 9, the high resistance film 18 is directly formed on the active layer 12. Even in this case, since the resistance of the high resistance film 18 is sufficiently high, the anode layer 13 and the cathode layer 14 are not short-circuited, and the potential distribution between them can be made uniform.

In FIG. 10, only the protective insulating film 19 is formed on the active layer 12 without using the high resistance film 18. In this case, the potential distribution cannot be made uniform by the high resistance film 18, but the n-type cathode layer 14 is formed by triple diffusion, and the diffusion depth is formed to reach the silicon oxide film 11. Therefore, the effect of alleviating the electric field concentration due to these is obtained.

FIG. 11 is a sectional view showing the element structure of a high voltage MOS transistor according to the second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The structure in which the n ^-- type active layer 12 is formed on the substrate 10 via the silicon oxide film 11 is similar to that shown in FIG. The total amount of impurities in the active layer 12 is also the same as in the first embodiment. In the active layer 12, a p-type base layer 23 and an n-type drain layer 24 corresponding to the p-type anode layer 13 and the n-type cathode layer 14 in the first embodiment are formed.

The n-type source layer 22 is formed in the p-type base layer 23.
Are formed, and the n-type source layer 22 and the n ⁻ -type active layer 12 are formed.
The gate electrode 21 is formed on the surface of the p-type base layer 23 sandwiched by the above as a channel region with a gate oxide film of about 60 nm interposed therebetween.

On the surface of the active layer sandwiched by the p-type base layer 23 and the n-type drain layer 24, the high resistance film 18 is formed via the silicon oxide film 17 as in the first embodiment. The silicon oxide film 19 is formed on the high resistance film 18.
Is covered with.

The source electrode 25 is formed on the n-type source layer 22 and the p-type base layer 23 so as to be simultaneously in contact therewith, and the drain electrode 26 is formed on the n-type drain layer 24. The ends of the high resistance film 18 are connected to the gate electrode 21 and the drain electrode 26, respectively. Here, the gate electrode 21 is 0 V at the time of OFF, which is the same as the ground, and the voltage is sufficiently lower than the high voltage applied to the drain electrode 26 even at the time of ON. Therefore, the high resistance film 18 has the gate electrode 21 and the drain electrode 26. The same function as in the first embodiment can be achieved even if it is connected between the two.

The MOSFET of this embodiment is as excellent as the diode of the first embodiment due to the triple diffusion of the n-type drain layer 24, the diffusion reaching the silicon oxide film 11, and the action of the high resistance film 18. High breakdown voltage characteristics can be obtained.

A modification of the second embodiment is shown in FIGS.
It shows in FIG. In FIG. 12, the n-type source layer 22 is formed on the oxide film 1
It is formed to a depth of 1. In FIG. 13, the high resistance film 18 is directly formed on the active layer 12. In FIG. 14, the high resistance film 18 is connected to the source electrode 25 instead of the gate electrode 21.

In FIG. 15, the drain side end of the high resistance film 18 is connected to the drain electrode 26 via an impurity-doped polycrystalline silicon film 28. Here, although the contact resistance between the high resistance film 18 and the drain electrode 26 is large, the high resistance film 18 and the impurity-doped polycrystalline silicon film 2
The contact resistance between the drain electrode 26 and the impurity-doped polycrystalline silicon film 28 is also extremely small. Therefore, by interposing the impurity-doped polycrystalline silicon film 28, the high resistance film 18 and the drain are formed. The contact resistance with the electrode 26 can be reduced.

In FIG. 16, the high resistance film 18 is omitted. Although not shown in the drawing, the p-type base layer 23, the n-type drain layer 24, etc. may be formed shallower than the silicon oxide film 11, as in FIGS. 2 to 4 in the first embodiment. Further, similarly to the example of FIG. 5, the n-type drain layer 24
Alternatively, the diffusion depth may be constant by changing the length of the lateral diffusion window in triple diffusion.

FIG. 17 is a sectional view showing the element structure of an IGBT (Insulated Gate Bipolar Transistor) according to the third embodiment of the present invention. The same parts as those in FIG. 11 are designated by the same reference numerals, and detailed description thereof will be omitted.

The basic structure is the same as that of FIG. 11, but in this embodiment, the n-type base layer 34 corresponds to the n-type drain layer 24 of FIG. The mold drain layer 36 is formed.

With such a structure, it is possible to realize a lateral IGBT in which a bipolar transistor and a power MOSFET are monolithically combined in one chip. In this case, as in the first embodiment, the triple diffusion of the n-type base layer 34, the diffusion reaching the silicon oxide film 11, and the action of the high resistance film 18 cause the edge portion of the n-type base layer 34 to move. The electric field concentration can be relaxed and the breakdown voltage can be improved.

A modification of the third embodiment is shown in FIGS.
It shows in FIG. 18, the n-type source layer 22 and the p-type drain layer 36 are the same as in the example of FIG.
The active layer 12 is thinned so that the depth reaches. At this time, since the p-type drain layer 36 is in contact with the silicon oxide film 11, a channel may be formed by the p-type inversion layer at the bottom of the active layer. To prevent this, n
It is necessary to set the impurity concentration of the type base layer 34 to be high, and specifically, the impurity concentration of the n-type base layer 34 is 1 × 1.
It may be 0 ¹⁷ cm ⁻³ or more. Alternatively, if the p-type drain layer 36 does not reach the silicon oxide film 11 as in the example of FIG. 17, channel formation by the p-type inversion layer at the bottom of the active layer can be avoided.

In FIG. 19, the high resistance film 18 is directly formed on the active layer 12. FIG. 20 shows the high resistance film 18
Is connected to the source electrode 25 instead of the gate electrode 21.

In FIG. 21, the drain side end of the high resistance film 18 is connected to the drain electrode 26 via an impurity-doped polycrystalline silicon film 28. Also in this case, FIG.
Similar to the example of 5, the contact resistance between the high resistance film 18 and the drain electrode 26 can be reduced by interposing the impurity-doped polycrystalline silicon film 28.

In FIG. 22, the high resistance film 18 is omitted. Although not shown in the drawing, the p-type base layer 23, the n-type base layer 34, etc. may be formed shallower than the silicon oxide film 11 as in FIGS. 2 to 4 in the first embodiment. Further, similarly to the example of FIG. 5, the n-type base layer 34 is
The length of the lateral diffusion window in triple diffusion may be changed to make the diffusion depth constant.

Next, another embodiment of the present invention will be described. FIG. 24 is a sectional view showing a schematic configuration of the fourth embodiment. This embodiment is an example of a lateral IGBT. A thickness of 5 μm is formed on the silicon substrate 50 through the silicon oxide film 51.
An n ⁻ type high resistance silicon layer (active layer) 52 of m or less is formed.

The silicon oxide film 51 has a thickness of about 1 to 5 μm. In the active layer 52, a p base 53 layer and an n base layer (buffer layer) 54 are formed by diffusion with a depth reaching the silicon oxide film 51 at a predetermined distance. Further, an n ⁺ type source layer 55 is formed in the p base layer 53, and a p ⁺ type drain layer 56 is formed in the n base layer 54 by diffusion. The surface portion of the p base layer 53 sandwiched by the n ⁺ type source layer 55 and the n ⁻ type active layer 52 is used as a channel region and 60
A gate electrode 57 is formed via a gate oxide film of about nm. The source electrode 58 is composed of the n ⁺ type source layer 55 and p
Is formed so as to contact the base layer 53 at the same time,
The drain electrode 59 is formed so as to contact the p-type drain layer 56. An insulating protective film 60 is formed on the active layer 52 between the electrodes 58 and 59.

FIG. 25 shows the structure of FIG.
Of the n-type active layer 5 on the bottom of the n-type buffer layer 54.
2 is left. An n-type buffer layer 54 is formed on the surface of the n-type active layer 52, and a p-type drain layer 56 is formed therein. The n-type buffer layer 54 functions to prevent punch through and increase the breakdown voltage. Further, since it has a function of lowering the efficiency of injecting holes from the p-type drain layer 56, the turn-off speed is increased at the same time the ON resistance of the device is increased.

FIG. 26 shows the relationship between the thickness of the n-type active layer 52 of the device having this structure and the on-resistance, the on-resistance when a current of 100 A / cm ² is passed, and the fall time at turn-off.
Shown in. The broken line shows the simulation result. n
Although the ON resistance gradually increases as the type active layer 52 becomes thinner, the turn-off speed increases significantly. Especially thickness 10
When the thickness is less than μm, the effect is remarkable. On the other hand, if the thickness is made too thin, the on-resistance will rapidly increase, so it is desirable to set the thickness of the n-type active layer 52 in the range of 4 μm to 10 μm.

FIG. 27 shows an embodiment in which the n-type impurity layer 61 is diffused from the entire surface of the active layer 52 based on the structure of FIG. The thickness of the active layer 52 is 10 μm or less, preferably 5 μm or less. In this structure, a concentration gradient in the vertical direction is formed in the active layer 52, the electric field concentration at the bottom of the active layer is effectively alleviated, and the trade-off is improved and a higher breakdown voltage is obtained.

[0064] Figure 28 is, n in the structure of FIG. 27 ^- -type active layer 5
This is an example in which a p ⁻ type active layer 62 is used instead of 2, and the n type impurity layer 61 is diffused from the entire surface of the active layer 62. Also in this case, a high breakdown voltage can be obtained for the same reason as in the embodiment of FIG.

FIG. 29 shows an embodiment in which the n-type impurity layer 63 is diffused from the entire bottom surface of the active layer 52 based on the structure of FIG. Also in this structure, a concentration gradient in the vertical direction is formed in the active layer 52, the electric field concentration at the bottom of the active layer is alleviated, and the trade-off is improved and a high breakdown voltage is obtained.

FIG. 30 is based on the structure of FIG.
This is an embodiment in which the width of the diffusion window of the base layer 54 is changed and the diffusion is double or more. Even in this structure, the diffusion layers 54 ', 5 of double or more
Due to the effect of 4 ″, the electric field in the lateral direction is relaxed, and similar to the embodiment of FIG. 27, the trade-off is improved and a high breakdown voltage is obtained.

31 to 33 show an embodiment in which the active layer is modified in the same manner as in the example of FIGS. 27 to 29, based on the structure of FIG. With these structures as well, similar to the embodiment of FIG. 30, it is possible to improve the trade-off and obtain a high breakdown voltage.

FIG. 34 shows an embodiment of the thyristor partly modified in the structure of FIG. Note that in FIG.
Reference numeral 77 is a gate, 78 is a cathode, and 79 is an anode. The present invention is directed to another lateral high-voltage device,
For example, it can be applied to EST, MCT, GTO, and the like.

FIG. 35 shows an example of a lateral IGBT in which the drain portion is modified in the embodiment of FIG. A high-concentration n-type layer 65 and a p-type layer 66 are formed on the surface of the p-type drain layer 56, and the drain electrode 59 is in contact with both of them. The n-type layer 65 is provided to limit the hole injection efficiency, and has the function of speeding up the turn-off. In plan view, the n-type layer 65 may have a single stripe shape or a plurality of island shapes. The p-type layer 66 is provided to improve the contact with the drain, but it may be omitted. Also in this embodiment, the n-type active layer 52 is thin,
By being preferably set to 10 μm or less,
The turn-off speed is even faster.

FIG. 36 is also a modification of the drain portion of the embodiment of FIG. A part of the n-type buffer layer 54 is an anode short type IGBT in which the drain electrode 59 is in contact, and the turn-off speed is high. Further, since the n-type active layer 52 is set thin, the turn-off speed becomes faster. In this embodiment, a high-concentration n-type layer for reducing the contact resistance may be provided at the contact portion between the n-type buffer layer 54 and the drain electrode 59.

FIG. 37 is a modification of the embodiment shown in FIG. An n-type layer 67 having an impurity concentration higher than that of the n-type active layer 52 is formed on the bottom of the n-type active layer 52. Generally, when the thickness of the n-type active layer 52 is reduced, the vertical electric field under the drain is increased when a voltage is applied, and the breakdown voltage is reduced. In the element of FIG. 37, space charge generated by depletion of the n-type layer 67 relaxes the electric field in the active layer 52 instead of increasing the electric field in the oxide film 51, so that a high breakdown voltage is maintained. Also in this embodiment, the thin n-type active layer 52 provides a high turn-off speed.

FIG. 38 is a modification of the embodiment shown in FIG. On the oxide film 51 is a p-type silicon layer 68,
An n-type active layer 52 is diffused and formed on the surface, and an element is formed therein. By setting the thickness of the p-type semiconductor layer 68 including the n-type active layer 52 to be thin, preferably 10 μm or less, a lateral IGBT having a high turn-off speed is obtained.

FIG. 39 is a modification of the embodiment shown in FIG. Similarly to the example of FIG. 38, the n-type active layer 52 is diffused and formed on the surface of the p-type silicon layer 68 separated from the silicon substrate (supporting substrate) 50 by the oxide film 51, and an element having the same configuration as that of FIG. 35 is formed there. Has been done.

FIG. 40 is a modification of the embodiment of FIG. 25, but uses a dielectric isolation substrate different from those of the modifications so far. The n-type active layer 52 has a high breakdown voltage.
The SIPOS film 69 is provided between the oxide film 51 and the oxide film 51. This may be a high resistance film or a high dielectric constant film other than the SIPOS film 69. Also in this embodiment, the n-type active layer 52
The turn-off speed is faster due to the thin setting.

Incidentally, in the embodiments of FIGS. 24, 25 and 27 to 40, the p-channel lateral IG having the opposite conductivity types is used.
Of course, it can be applied to BT.

Next, a fifth embodiment of the present invention will be described. FIG. 41 is a sectional view of the element structure showing the high breakdown voltage diode according to the fifth embodiment. An n ⁻ type high resistance silicon active layer 12 is formed on a silicon substrate 10 via a silicon oxide film 11. A p ⁺ -type layer 13 having a high impurity concentration, which serves as an anode region, and an n ⁺ -type layer 14, which is a high impurity concentration layer, serving as a cathode region, are formed on the silicon active layer 12 at a predetermined distance. An anode electrode 15 is formed on the p ⁺ type layer 13, and a cathode electrode 16 is formed on the n ⁺ type layer 14. An n-type buffer layer 71 is formed on the bottom of the silicon active layer 12.

In the high breakdown voltage diode thus constructed, when the substrate 10 and the electrode 15 are grounded and a positive potential is applied to the electrode 16, the pn junction is reverse biased and the depletion layer spreads in the silicon active layer 12. . A depletion layer spreads upward from the interface between the oxide film 11 and the silicon active layer 12. When the applied voltage exceeds a certain value, the silicon active layer 1
2 is filled with the depletion layer, and the silicon active layer 1
In 2, a strong electric field is generated downward from the n ⁺ type layer 13.

Further, when the n-type buffer layer 71 formed at the bottom of the silicon active layer 12 is reverse biased and the buffer layer 71 is depleted, positive space charges are generated here. As a result of the space charges functioning to relax the electric field in the silicon active layer 12, a larger applied voltage is shared by the intermediate oxide film at the bottom of the silicon active layer and a high breakdown voltage characteristic is obtained. The total amount of impurities in the buffer layer 71 is set to 3 × 10 ¹² cm ⁻² or less, and more preferably 5 × 10 ¹¹ to 2 × 10 ¹² cm ⁻² .

FIG. 43 shows the relationship between the diffusion length 2 × (Dt) ^{1/2 of the} n-type buffer layer 71 and the breakdown voltage of the device. The impurity doping amount is optimized for each diffusion length. There is. This is a curve obtained by determining the total amount of impurities in the n-type buffer layer 71. Diffusion length is 1/2000
In the range smaller than cm, the breakdown voltage is improved as the diffusion length is shortened, and a high breakdown voltage is obtained. Also, 2
To operate in a 00V system, a withstand voltage of 500V must be guaranteed, but a high withstand voltage of 500V or more can be obtained if the diffusion length is in the range of less than 1/4000 cm.

In FIG. 42, the n-type buffer layer 71 at the bottom of the silicon active layer 12 is selectively formed based on the structure of FIG. Since the applied voltage is greatly applied to the silicon active layer 12 immediately below the drain, a high breakdown voltage can be obtained by selectively forming the n-type buffer layer 72 only in this portion and relaxing the electric field.

FIG. 44 shows an active layer 1 for the structure of FIG.
This is an example when the thickness of 2 is thin. N when the active layer 12 is thin
The type impurity layer reaches the oxide film below the active layer, but in this case as well, higher breakdown voltage can be obtained by forming the n-type buffer layer at the bottom of the active layer.

FIG. 45 shows an active layer 1 for the structure of FIG.
This is an example when the thickness of 2 is thin. Even in the structure in which the n-type impurity layer reaches the oxide film, the same effect can be obtained by selectively inserting the n-type buffer layer.

As described above, according to this embodiment, by forming the n-type buffer layer having a short diffusion length at the bottom of the active layer, it is possible to obtain a sufficiently high breakdown voltage with a thin active layer. The configuration in which the n-type buffer layer is provided under the active layer as in this embodiment can be applied to the first embodiment shown in FIGS. 1 to 10.

Next, another embodiment of the present invention will be described. In this embodiment, a high speed diode is formed on a dielectric isolation substrate.

FIG. 46 is a sectional view of the element structure showing the high speed diode according to the sixth embodiment. An insulating film 83 is formed between the semiconductor substrate 81 and the high-resistance n-type semiconductor substrate 82 to form a dielectric isolation substrate. The p-type anode layer 8 is formed on the surface of the high-resistance n-type semiconductor substrate 82 of the dielectric isolation substrate.
4, n-type cathode layer 85 is formed, and anode layer 84 is formed.
An anode electrode 86 is formed on the surface of, and a cathode electrode 87 is formed on the surface of the cathode layer 85.

[0086] Although the same as the conventional structure so far, in addition to this in the present embodiment, the impurity layer 88 of n ⁺ -type are selectively formed on the anode layer 84, the cathode layer 85 of the p ⁺ -type impurity A layer 89 is selectively formed, the anode electrode 86 makes ohmic contact with both the anode layer 84 and the n ⁺ -type impurity layer 88, and the cathode electrode 87 has the cathode layer 85.
And ohmic contact with both the p ⁺ -type impurity layer 89. The thickness of the semiconductor substrate 82 on which the anode layer 84 and the cathode layer 85 are formed is 2 to
It is set to 10 μm.

FIG. 47 shows the relationship between the ON voltage Vf and reverse recovery time trr of the diode formed on the dielectric isolation substrate and the thickness ts of the semiconductor substrate 82. The reverse recovery time trr is the substrate 8
2 becomes shorter as the thickness ts becomes thinner, and ts ≦ 10 μm
Then, it was confirmed that trr ≦ 0.3 μsec was satisfied. However, it has been found that the on-voltage Vf rises sharply when ts≤2 μm. Therefore, if the thickness ts of the semiconductor substrate 82 is set to 2 to 10 μm, it is possible to realize a diode with a fast reverse recovery time without controlling the lifetime such as electron beam irradiation.

Next, a seventh embodiment of the present invention will be described. This embodiment relates to a dielectric isolation semiconductor substrate having an insulating film layer in the middle of the semiconductor substrate. FIG. 48 shows the structure of a dielectric isolation semiconductor substrate according to the seventh embodiment,
(A) is a plan view seen from the back surface, and (b) is a sectional view taken along the line AA '. Two silicon substrates 91 and 93 are oxide films 92
And the surface of the silicon substrate 91 is polished to a predetermined thickness. Then, the silicon substrate 93 is formed with lattice-shaped grooves 94, and the oxide film 95 is formed in the grooves 94.
It has a structure in which is embedded.

FIG. 49 shows a manufacturing process of this dielectric isolation semiconductor substrate. After direct silicon bonding, a width of several μm, preferably 1 μm, is applied to the silicon substrate 93 as shown in FIG.
Hereinafter, the grid-like grooves 94 having a depth of several μm to several tens of μm are formed. Subsequently, as shown in FIG. 49B, the groove 94 is filled with an oxide film 95. At this time, if the groove width is set to about 1 μm or less, the groove 94 can be completely filled by thermal oxidation. Then, as shown in FIG. 49B, the surface of the silicon substrate 91 is polished to a predetermined thickness.

In this dielectric isolation semiconductor substrate, the oxide film 92 and the oxide film 95 are formed so as to sandwich the silicon substrate 93, so that the warp of the substrate can be suppressed to a small level. Further, also in the step of removing the oxide film formed on the surface of the substrate during element formation, the oxide film 95 is removed only on the surface, and the oxide film 95 remains in the trench 94. Therefore, there is no need to provide a protective film to prevent the oxide film on the back surface from being removed as in the conventional case, and the process can be simplified.

As described above, according to this embodiment, it is possible to realize a dielectric isolation semiconductor substrate having a small warpage even if the thickness of the intermediate oxide film is increased, the process is simplified, and the cost is reduced. It becomes possible to contribute to the realization of the power IC.

FIG. 50 shows a modification of the embodiment shown in FIG. The difference from FIG. 48 is that a reduced pressure CV is applied to the surface of the oxide film 95.
That is, the polysilicon 96 is formed by the D method. This embodiment is effective when the width of the groove 94 is 1 μm or more. When the width of the groove 94 is 1 μm or more, it becomes difficult to fill the groove 94 only by thermal oxidation. Therefore, the portion where the filling is insufficient is filled with the polysilicon 96. Further, in this embodiment, since the back surface of the substrate is made of polysilicon 96, there is an advantage that the oxide film 95 is not removed at all even in the step of removing the oxide film during element formation.

In the seventh embodiment, the semiconductor substrate is made of silicon and the insulating film is made of an oxide film. However, the present invention is not limited to this, and other materials may be used. Further, in this embodiment, the dielectric isolation semiconductor substrate obtained by directly joining two semiconductor substrates is used, but it is also effective to use the dielectric isolation semiconductor substrate obtained by another method. FIG. 54 is a sectional view showing an example of a dielectric isolation semiconductor device according to the eighth embodiment of the present invention. An n ⁻ type high resistance silicon layer (active layer) 103 is formed on a silicon substrate 101 with a silicon oxide film (isolation insulating film) 102 interposed therebetween. The thickness of the silicon oxide film 102 is 3μ
The thickness of the m, n ⁻ type active layer 103 is 0.1 μm. n
^- the impurity concentration of the type active layer 103 is 1.0 × 10 ¹⁷ / cm
^{Is 3} . The n ⁻ -type active layer 103 has a drain region 10
4, a source region 105 is formed, and a drain electrode 106 and a source electrode 107 are formed on the drain region 104 and the source region 105, respectively. Reference numerals 108 and 109 are insulating films,
It is a gate electrode.

The lateral impurity concentration distribution of the n ^-- type active layer 103 has a three-step staircase shape. This stepwise impurity concentration distribution can be obtained as follows.

That is, a first mask is formed on the n ^-- type active layer 103, and phosphorus is ion-implanted with a dose amount of 2 × 10 ¹² cm ^-2 . Next, phosphorus is ion-implanted with a dose amount of 2 × 10 ¹² cm ⁻² using a second mask having lateral openings wider than the first mask. Further, using a third mask having a lateral opening wider than the second mask, 2 × 1
Phosphorus is ion-implanted at a dose of 0 ¹² cm ^-2 . The difference between the openings in the lateral direction of the mask is at least twice the diffusion length, preferably 3 to 4 times.

Then, heat treatment is performed at about 1200 ° C. to diffuse the ion-implanted phosphorus, so that an impurity concentration distribution having three steps in the lateral direction as shown in FIG. 55 is obtained. When the avalanche breakdown voltage of the dielectric isolation semiconductor element shown in FIG. 54 was measured, it was 700V.

In the example shown in FIG. 54, the number of steps of the stepwise impurity concentration distribution is three, but it can be appropriately changed within the range of 2 to 10. When the number of stages is increased, the same breakdown voltage can be obtained even if the diffusion length is reduced. on the other hand,
When the number of stages is reduced, it is necessary to increase the diffusion length.

FIG. 55 is a graph showing the relationship between the number of steps and the corresponding diffusion length when the breakdown voltage of the semiconductor element is set as a parameter. The curve in the figure is represented by the following formula.

(N + 1) [a + (V _b / 200) +1.
5] = _{V b} ^2/13600 formula, _{V b} is the breakdown voltage (V), a diffusion length (μm), n represents the number of stages.

As described above, the sixth aspe of the present invention
According to ct, even if the thickness of the active layer is 0.3 μm or less, it is possible to realize a lateral dielectric isolation semiconductor element having a high breakdown voltage without increasing the length of the drift region.

[0101]

As described above in detail, according to the first invention, the electric field at the edge portion (especially in the vicinity of the curved surface portion of the bottom) of the diffusion layer is improved by devising the shape of the diffusion layer by diffusing more than twice. Concentration can be relaxed, which makes it possible to realize a high withstand voltage semiconductor element having a dielectric isolation structure that can obtain a sufficiently high withstand voltage characteristic with a thin active layer.

Further, according to the second aspect of the invention, even if the thickness of the active layer is 0.3 μm or less, the lateral impurity concentration distribution of the active layer has a Gaussian distribution of 2 to 10 steps. By setting the interval of each stair to be twice the diffusion length or more, without increasing the length of the drift region,
It is possible to realize a high breakdown voltage lateral dielectric isolation semiconductor element.

[Brief description of drawings]

FIG. 1 is a sectional view showing an element structure of a high breakdown voltage diode according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing an example in which a p-type anode layer is formed shallower than an oxide film in the first embodiment.

FIG. 3 is a sectional view showing an example in which an n-type cathode layer is formed shallower than an oxide film in the first embodiment.

FIG. 4 is a sectional view showing an example in which a p-type anode layer and an n-type cathode layer are formed shallower than an oxide film in the first embodiment.

FIG. 5 is a sectional view showing an example in which the triple diffusion depth of the n-type cathode layer is made constant in the first embodiment.

6 is a cross-sectional view showing an example in which a p-type anode layer is formed shallower than an oxide film in the example of FIG.

FIG. 7 is a sectional view showing an example in which an n-type cathode layer is formed by double diffusion in the first embodiment.

FIG. 8 is a sectional view showing an example in which a high resistance film is connected to a p-type anode layer and an n-type cathode layer in the first embodiment.

FIG. 9 is a sectional view showing an example in which a high resistance film is directly formed on an active layer in the first embodiment.

FIG. 10 is a sectional view showing an example in which the high resistance film is omitted in the first embodiment.

FIG. 11 is a high breakdown voltage MOS according to a second embodiment of the present invention.
Sectional drawing which shows the element structure of FET.

FIG. 12 is a sectional view showing an example in which an n-type source layer is formed so as to reach an oxide film in the second embodiment.

FIG. 13 is a sectional view showing an example in which a high resistance film is directly formed on an active layer in the second embodiment.

FIG. 14 is a cross-sectional view showing an example in which both ends of the high resistance film are connected to electrodes in the second embodiment.

FIG. 15 is a sectional view showing an example in which one end of a high resistance film is connected to an electrode via an impurity-doped polycrystalline silicon film in the second embodiment.

FIG. 16 is a sectional view showing an example in which a high resistance film is omitted in the second embodiment.

FIG. 17 is a sectional view showing an element structure of a lateral IGBT according to a third embodiment.

FIG. 18 is a sectional view showing an example in which an n-type source layer and a p-type drain layer are formed to a depth reaching an oxide film in the third embodiment.

FIG. 19 is a sectional view showing an example in which a high resistance film is directly formed on an active layer in the third embodiment.

FIG. 20 is a sectional view showing an example in which both ends of the high resistance film are connected to electrodes in the third embodiment.

FIG. 21 is a sectional view showing an example in which one end of a high resistance film is connected to an electrode via an impurity-doped polycrystalline silicon film in the third embodiment.

FIG. 22 is a sectional view showing an example in which the high resistance film is omitted in the third embodiment.

FIG. 23 is a characteristic diagram showing the relationship between the total amount of impurities in the active layer and the breakdown voltage.

FIG. 24 is a lateral IGBT according to a fourth embodiment of the present invention.
3 is a cross-sectional view showing the element structure of FIG.

FIG. 25 is a cross-sectional view showing an example in which the active layer is formed thick with the configuration of FIG. 24.

FIG. 26 is a characteristic diagram showing the relationship between the ON voltage and the switching OFF time with respect to the active layer thickness.

27 is a sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire surface of the active layer based on the structure of FIG.

FIG. 28 shows a structure of FIG. 27 in which p ⁻ instead of the n ⁻ type active layer is used.
Sectional drawing which shows the Example which used the active layer of a mold.

29 is a sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire bottom surface of the active layer based on the structure of FIG.

30 is a sectional view showing an embodiment in which the n base layer is diffused into double or more layers by changing the width of the diffusion window based on the structure of FIG. 24.

31 is a sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire surface of the active layer based on the structure of FIG.

32 shows a structure of FIG. 31 in which p ⁻ is used instead of the n ⁻ type active layer.
Sectional drawing which shows the Example which used the active layer of a mold.

33 is a sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire bottom surface of the active layer based on the structure of FIG.

34 is a cross-sectional view showing an embodiment of a thyristor which is partially modified by the structure of FIG.

FIG. 35 is a sectional view showing an example of a lateral IGBT in which the drain portion is modified in the embodiment of FIG. 25.

FIG. 36 is a sectional view showing an example in which the drain portion of the embodiment of FIG. 25 is modified.

FIG. 37 is a sectional view showing a modification of the embodiment of FIG. 25.

FIG. 38 is a sectional view showing a modification of the embodiment of FIG. 25.

FIG. 39 is a sectional view showing a modification of the embodiment of FIG. 25.

FIG. 40 is a sectional view showing a modification of the embodiment of FIG. 25.

FIG. 41 is a sectional view of the element structure showing the high breakdown voltage diode according to the fifth embodiment of the present invention.

42 is based on the structure of FIG. 41 and has n at the bottom of the active layer.
Sectional drawing which shows the example which formed the type | mold buffer layer selectively.

FIG. 43 is a characteristic diagram showing the relationship between the diffusion length 2 × (Dt) ^{1/2 of the} buffer layer and the device breakdown voltage.

44 is a cross-sectional view showing an example in which a buffer layer at the bottom of the active layer is selectively formed based on the structure of FIG. 41.

45 is a sectional view showing an example in which the thickness of the active layer is smaller than that of the structure of FIG. 41.

FIG. 46 is a sectional view of a device structure showing a high speed diode according to a sixth embodiment of the present invention.

FIG. 47 is a characteristic diagram showing the relationship between the on-voltage Vf and reverse recovery time trr of the diode formed on the dielectric isolation substrate and the thickness ts of the semiconductor substrate.

48A and 48B are a plan view and a sectional view showing a schematic configuration of a dielectric isolation semiconductor substrate according to a seventh embodiment of the present invention.

FIG. 49 is a cross-sectional view showing the manufacturing process of the dielectric isolation semiconductor substrate of FIG. 48.

50 is a sectional view showing a modification of the embodiment of FIG. 48.

FIG. 51 is a cross-sectional view showing a conventional example of a lateral high withstand voltage diode using a dielectric isolation structure.

FIG. 52 is a characteristic diagram showing the relationship between the diffusion length and the breakdown voltage.

FIG. 53 is a characteristic diagram showing the relationship between the number of steps and the breakdown voltage.

FIG. 54 is a sectional view showing an example of a dielectric isolation semiconductor device according to an eighth embodiment of the present invention.

FIG. 55 is a characteristic diagram showing a lateral impurity concentration distribution of the active layer when the active layer is diffused three times.

FIG. 56 is a characteristic diagram showing the relationship between the number of steps and the diffusion length when the breakdown voltage of the device is set as a parameter.

FIG. 57 is a cross-sectional view showing a conventional example of a lateral high withstand voltage diode using a dielectric isolation structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 11 ... Silicon oxide film (isolation insulating film) 12 ... N ^- type high resistance silicon layer (active layer) 13 ... P-type anode layer (2nd conductivity type impurity layer) 14 ... N-type cathode layer (1st) Conductive type impurity layer) 15 ... Anode electrode 16 ... Cathode electrode 18 ... High resistance film 21 ... Gate electrode 23 ... P-type base layer 24 ... N-type drain layer 25 ... Source electrode 26 ... Drain electrode 28 ... Impurity-doped polycrystalline silicon Film 34 ... N-type base layer 36 ... P-type drain layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshihiro Yamaguchi No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center (72) Inventor Ichiro Omura Komukai, Kawasaki-shi, Kanagawa Toshiba Town No. 1 Corporate Research & Development Center, Toshiba (72) Inventor Hideyuki Funaki No. 1 Komukai Toshiba Town, Kouki-ku, Kawasaki-shi, Kanagawa Corporate Research & Development Center

Claims (2)

[Claims] 1. A semiconductor substrate, an active layer made of a high-resistance first-conductivity-type semiconductor formed on the substrate via an insulating film, and a first conductive layer formed at a predetermined distance from the active layer. Type impurity layer and a second conductivity type impurity layer, and the first conductivity type impurity layer is a double or more diffusion layer in which at least one of the width and the diffusion depth of the diffusion window is different. A high breakdown voltage semiconductor device characterized by the above. 2. A semiconductor substrate and a high resistance semiconductor of 0.3 .mu.m formed on the semiconductor substrate with an insulating film interposed therebetween.
And an active layer having a thickness of
A high withstand voltage semiconductor device in which the impurity concentration distribution in the lateral direction has a stepwise shape of 2 to 10 steps, each of which is a Gaussian distribution, and the interval between the steps is at least twice the diffusion length.