JP4088263B2 - High voltage semiconductor element - Google Patents

Description

  The present invention relates to a high breakdown voltage semiconductor element having a dielectric isolation structure, and more particularly to a high breakdown voltage semiconductor element having an improved diffusion layer shape.

Conventionally, various high voltage semiconductor elements using a dielectric isolation structure have been proposed. FIG. 51 shows a conventional example of a lateral type high voltage diode using a dielectric isolation structure. An n ⁻ type silicon layer (active layer) 3 is formed on the semiconductor substrate 1 with an isolation insulating film 2 interposed therebetween. In addition, a p-type anode layer 5 and an n-type cathode layer 6 spaced apart from the p-type anode layer 5 are formed on the surface portion of the active layer 3, and an anode electrode 7 and a cathode electrode 8 are formed respectively.

  In such a horizontal diode, consider a reverse bias state in which, for example, the substrate 1 and the anode electrode 7 are grounded and a positive voltage is applied to the cathode electrode 8. At this time, the voltage applied to the n-type cathode layer 6 is shared by the depletion layer extending to the active layer 3 below the n-type cathode layer 6 and the isolation insulating film 2. Therefore, if the thickness of the active layer portion under the n-type cathode layer 6 is thin, a large electric field is shared here, and electric field concentration occurs at the edge portion (near the curved portion at the bottom) of the n-type cathode layer 6. Avalanche breakdown occurs at low applied voltage. In order to avoid this and realize a sufficiently high breakdown voltage, conventionally, the thickness of the active layer 3 has been set to 20 μm or more.

  However, if the thickness of the active layer is large, a deep isolation groove is required when element isolation in the lateral direction is performed by a V-shaped groove or the like, and the area of the isolation groove region is large. Therefore, not only is the processing difficult, but the effective area of the element on the wafer is reduced, resulting in an increase in the cost of the integrated circuit of the high breakdown voltage element.

  On the other hand, the dielectric isolation structure makes it possible to create a high voltage element and a logic circuit on the same substrate. In that case, according to SOI (Silicon on insulator) technology for forming an element in a semiconductor layer (active layer) formed on an insulating film, it is possible to completely separate a high voltage element and a logic circuit.

  Such a semiconductor device using an SOI substrate is known to be able to obtain a high breakdown voltage in the vertical direction because of an insulating film even if the thickness of the active layer is reduced to 0.3 μm or less. Since element isolation using a groove is possible, this element isolation structure is a powerful structure in a power IC.

However, when the active layer is thin like this, in order to increase the lateral breakdown voltage, the impurity doping concentration of the n drift region in the active layer has to be lowered. The length of the n drift region is necessary. In order to avoid this, for example, as shown in FIG. 57, a method of uniforming the electric field strength in the lateral direction by forming a SIPOS (semi-insulating doped silicon) layer 18 along the drift region, For example, a method of forming a linear doping concentration distribution (see, for example, Patent Document 1) can be considered. However, these methods require special steps and are difficult to implement.
JP-A-4-309234

  As described above, the conventional high breakdown voltage semiconductor element having a dielectric isolation structure has a problem that a sufficient breakdown voltage cannot be obtained if the active layer is thin, and lateral isolation becomes difficult if the active layer is thick. It was.

  In the drift region, when the active layer is thin, the impurity doping concentration of the n drift region in the active layer must be lowered in order to increase the lateral breakdown voltage. There is a problem that it is necessary to increase the length of the drift region, which makes it difficult to miniaturize the element.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high breakdown voltage semiconductor element having a dielectric isolation structure capable of obtaining a sufficiently high breakdown voltage characteristic with a thin active layer. There is.

  Another object of the present invention is to provide a high breakdown voltage semiconductor element having a dielectric isolation structure that can obtain a sufficiently high breakdown voltage characteristic without increasing the length of the drift region.

  The gist of the present invention is to alleviate the electric field concentration at the edge portion (especially near the curved surface portion of the bottom portion) of the diffusion layer by devising the shape of the diffusion layer.

That is, according to one embodiment of the present invention, a semiconductor substrate, an insulating layer formed over the semiconductor substrate, and a high-conductivity semiconductor of the first conductivity type formed over the insulating layer is 0.3 μm or less. An active layer having a thickness, a first impurity layer of a first conductivity type formed in the active layer, and formed in the active layer and formed at a predetermined distance from the first impurity layer A second conductivity type second impurity layer; a first electrode formed on the first impurity layer; and a second electrode formed on the second impurity layer. The first impurity layer has a stepwise shape of 2 to 10 steps in which the lateral impurity concentration distribution is a Gaussian distribution, and the interval between the steps is at least twice the diffusion length. A high voltage semiconductor device is provided.

  In the high breakdown voltage semiconductor element having a dielectric isolation structure, it is assumed that a high voltage with a reverse bias is applied to the first conductivity type impurity layer in a state where the second conductivity type impurity layer and the substrate are grounded. At this time, the voltage applied to the first conductivity type impurity layer is shared by the active layer and the insulating film in the vertical direction. Here, when electric field concentration occurs in the vicinity of the curved surface portion at the bottom of the first conductivity type impurity layer, avalanche breakdown occurs at a low voltage.

  In one aspect of the present invention, by performing a general impurity diffusion technique a plurality of times, the lateral concentration distribution of the active layer is stepped, so that even if the thickness of the active layer is 0.3 μm or less, Provided is a dielectric isolation semiconductor element capable of achieving a high breakdown voltage without increasing the length of the drift region.

  It is considered that the dielectric isolation semiconductor device according to one aspect of the present invention exhibits a high breakdown voltage based on the following principle.

  The horizontal direction is the x axis and the vertical direction is the y axis. If the thickness of the active layer is 0.3 μm or less, it is considered that the impurity concentration distribution in the vertical direction when impurities are diffused is substantially uniform. Thus, assuming that the lateral impurity concentration distribution is a Gaussian distribution, the following expression is given.

n (x, y) = n o exp (-x 2 / a 2)
Here, a represents the diffusion length (a = 2D _t ^1/2 , n ₀ represents the difference in impurity concentration in the staircase portion. At this time, the maximum value of the concentration gradient Δn _max is given by x = a · 2 ^−1/2 . As a result, the following formula is obtained.

Δn _max = | dn / dx _{(x = a} ^−1/2 | = | −2 × exp (−1/2) × n ₀ /a|=0.85776×n ₀ / a
The electric field strength in the horizontal direction and the vertical direction can be obtained by solving the Poisson equation.

n (x) = (ε _s / q) (dE _x / d _x + dE _y / d _y )
Here, ε _s is a dielectric constant with respect to Si, and q is an elementary charge. In order to obtain the avalanche breakdown voltage of the element, ionization integration is performed as shown in the following formula 2.

I = ∫α (E) dX
Here, α (E) is an ionization coefficient and is obtained by the following equation.

α (E) = A · exp (−B / E)
Here, A and B are constants. In general, the Poisson equation and the ionization integral cannot be obtained analytically, so numerical calculation is performed. As a result, it was found that there is a relationship represented by the following equation between n ₀ and a.

n ₀ / a ^1/2 ≦ 1 × 10 ¹⁹
Therefore, it is necessary that the maximum value Δn _max of the concentration gradient satisfies the following formula.

Δn _max ≦ 0.85776 × 10 ¹⁹ / a ^1/2
On the other hand, in the step portion of the staircase, the electric field strength in the lateral direction is much smaller than that of the step portion, so it is better to reduce the interval between the staircases. However, if the interval between the steps is too small, interference occurs between adjacent steps and the electric field becomes strong. Therefore, the interval between steps should be at least twice the diffusion length, preferably about 3 to 4 times.

  FIG. 52 shows a breakdown voltage when the diffusion length is changed, and FIG. 53 shows a breakdown voltage when the diffusion number is changed. From these drawings, according to one embodiment of the present invention, it is possible to realize a high breakdown voltage dielectric isolation semiconductor element without increasing the length of the drift region.

  According to one aspect of the present invention, even if the thickness of the active layer is 0.3 μm or less, the lateral impurity concentration distribution of the active layer has a step shape of 2 to 10 steps each having a Gaussian distribution. By setting the interval between steps to be twice or more the diffusion length, it is possible to realize a high breakdown voltage lateral dielectric isolation semiconductor element without increasing the length of the drift region.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing an element structure of a high voltage diode according to a first embodiment of the present invention. An n ⁻ -type high-resistance silicon layer (active layer) 12 is formed on the silicon substrate 10 via a silicon oxide film (isolation insulating film) 11. This structure is formed, for example, by forming a silicon oxide film 11 on the surface of the silicon substrate 10, directly bonding another silicon substrate having a mirror-polished surface, and processing the substrate thinly. The silicon oxide film 11 has a thickness of about 1 to 5 μm. The n ⁻ type active layer 12 has a total impurity amount set in the range of 1 × 10 ¹⁰ cm ⁻² to 2 × 10 ¹² cm ⁻² , more preferably in the range of 0.5 to 1.8 × 10 ¹² cm ^−2. The thickness was about 10 μm.

A p-type anode layer 13 and an n-type cathode layer 14 are formed on the active layer 12 at a predetermined distance. The p-type anode layer 13 and the n-type cathode layer 14 are diffused to a depth that reaches the silicon oxide film 11 at the bottom of the active layer as shown in the figure. Further, the n-type cathode layer 14 has triple diffusion layers 14a, 14b, and 14c by changing the width and diffusion depth of the diffusion window. The total amount of impurities in the diffusion layers other than 14a, that is, the diffusion layers 14b and 14c here, is set in the range of 1 × 10 ¹¹ cm ^{−2 to} 3 × 10 ¹² cm ⁻² . An anode electrode 15 and a cathode electrode 16 are formed on the p-type anode layer 13 and the n-type cathode layer 14, respectively. A high resistance film 18 is disposed on the active layer 12 between these electrodes 15 and 16 via a silicon oxide film 17. The high resistance film 18 is, for example, SIPOS (Semi-Insulating Polycrystalline Silicon), and both ends of the high resistance film 18 are connected to the electrodes 15 and 16, respectively. The surface of the high resistance film 18 is covered with a silicon oxide film 19 as a protective film.

  In this configuration, consider a case where the p-type anode layer 13 and the substrate 10 are grounded and a positive high voltage is applied to the n-type cathode layer 14. Since the n-type cathode layer 14 is formed to a depth reaching the bottom of the active layer, all voltages applied to the n-type cathode layer 14 are shared by the silicon oxide film 11 in the vertical direction. Here, the silicon oxide film 11 has a sufficiently high breakdown voltage compared to the active layer 12.

  In addition, a minute current flows through the high resistance film 18 formed on the surface of the active layer 12 due to the anode-cathode voltage, and a uniform potential distribution is formed in the lateral direction. Under the influence of the potential distribution in the high resistance film 18, a uniform potential distribution is also formed in the lateral direction on the surface of the active layer immediately below the high resistance film. Further, by diffusing the n-type cathode layer 13 in a triple manner, the impurity concentration gradient at the curved surface portion at the bottom of the diffusion layer is alleviated, and as a result, the equipotential lines are widened and extreme electric field concentration can be prevented. As a result, the electric field concentration inside the device is relaxed and a high breakdown voltage is realized.

In the configuration as described above, the breakdown voltage also changes when the total amount of impurities in the active layer 12 is changed. FIG. 23 is a characteristic diagram showing the relationship between the total amount of impurities in the active layer 12 and the breakdown voltage. When the total amount of impurities is 1 × 10 ¹⁰ cm ⁻² or more, the breakdown voltage increases as the total amount of impurities increases, and when the total amount of impurities exceeds 3 × 10 ¹² cm ⁻² , the breakdown voltage decreases rapidly. Therefore, the total amount of impurities in the active layer 12 is preferably in the range of 1 × 10 ¹⁰ cm ⁻² to 2 × 10 ¹² cm ⁻² .

  As described above, according to this embodiment, the n-type cathode layer 14 is formed by triple diffusion, is formed to a depth reaching the silicon oxide film 11, and the high resistance film 18 is formed on the active layer 12. As a result, the electric field concentration inside the device can be alleviated, and a high breakdown voltage diode can be realized even if the active layer 12 is thinned.

  Modifications of the first embodiment are shown in FIGS. FIG. 2 shows the p-type anode layer 13 formed shallower than the silicon oxide film 11 in the first embodiment. In FIG. 3, the n-type cathode layer 14 is formed shallower than the silicon oxide film 11. In FIG. 4, the p-type anode layer 13 and the n-type cathode layer 14 are both formed shallower than the silicon oxide film 11. Even with such a configuration, since the electric field concentration at the edge portion of the n-type cathode layer 14 is relaxed, the same effect as in the first embodiment can be obtained.

  In FIG. 5, the depth of the n-type cathode layer 14 is constant at the depth reaching the silicon oxide film 11, and the length of the lateral diffusion window in triple diffusion is changed. Here, the impurity concentration of 14a, 14b, and 14c decreases in order. Even with such a configuration, by increasing the interval between the equipotential lines in the lateral direction, extreme electric field concentration can be prevented, and the same effect as in the first embodiment can be obtained. Note that the impurity concentration may be continuously varied instead of performing multiple diffusions with different impurity concentrations.

  FIG. 6 applies the idea of FIG. 2 to the configuration of FIG. In FIG. 7, the n-type cathode layer 14 is formed by double diffusion instead of triple diffusion.

  In FIG. 8, the high resistance film 18 is directly connected to the p-type anode layer 13 and the n-type cathode layer 14 together with the electrodes 15 and 16. In FIG. 9, the high resistance film 18 is formed directly on the active layer 12. Even in this case, since the resistance of the high-resistance film 18 is sufficiently high, the anode layer 13 and the cathode layer 14 are not short-circuited, and the potential distribution between them can be made uniform.

  In FIG. 10, only the protective insulating film 19 is formed on the active layer 12 without using the high resistance film 18. In this case, the potential distribution cannot be made uniform by the high resistance film 18, but the n-type cathode layer 14 is formed by triple diffusion and the diffusion depth is formed to a depth reaching the silicon oxide film 11. Therefore, the effect of reducing the electric field concentration by these can be obtained.

  FIG. 11 is a cross-sectional view showing the element structure of a high voltage MOS transistor according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

The structure in which the n ⁻ -type active layer 12 is formed on the substrate 10 via the silicon oxide film 11 is the same as in FIG. The total amount of impurities in the active layer 12 is the same as in the first embodiment. In the active layer 12, a p-type base layer 23 and an n-type drain layer 24 corresponding to the p-type anode layer 13 and the n-type cathode layer 14 in the first embodiment are formed.

An n-type source layer 22 is formed in the p-type base layer 23, and a surface portion of the p-type base layer 23 sandwiched between the n-type source layer 22 and the n ⁻ -type active layer 12 is used as a channel region. A gate electrode 21 is formed through a gate oxide film of about 60 nm.

  A high resistance film 18 is formed on the surface of the active layer sandwiched between the p-type base layer 23 and the n-type drain layer 24 via the silicon oxide film 17 as in the first embodiment. The resistor film 18 is covered with a silicon oxide film 19.

  The source electrode 25 is formed on the n-type source layer 22 and the p-type base layer 23 so as to be in contact with each other simultaneously, and the drain electrode 26 is formed on the n-type drain layer 24. The ends of the high resistance film 18 are connected to the gate electrode 21 and the drain electrode 26, respectively. Here, the gate electrode 21 is 0 V when off and is the same as the ground, and even when it is on, the voltage is sufficiently lower than the high voltage applied to the drain electrode 26. Even if they are connected to each other, the same function as in the first embodiment is achieved.

  The MOSFET of this embodiment also has excellent high breakdown voltage characteristics similar to the diode of the first embodiment due to the triple diffusion of the n-type drain layer 24, the diffusion reaching the silicon oxide film 11, and the action of the high resistance film 18. Is obtained.

  Modifications of the second embodiment are shown in FIGS. In FIG. 12, the n-type source layer 22 is formed to a depth that reaches the oxide film 11. In FIG. 13, the high-resistance film 18 is formed directly on the active layer 12. In FIG. 14, the high resistance film 18 is connected to the source electrode 25 instead of the gate electrode 21.

  In FIG. 15, the drain side end portion of the high resistance film 18 is connected to the drain electrode 26 through the impurity-doped polycrystalline silicon film 28. Here, the contact resistance between the high-resistance film 18 and the drain electrode 26 is large, but the contact resistance between the high-resistance film 18 and the impurity-doped polycrystalline silicon film 28 is extremely small, and the drain electrode 26 and the impurity-doped polycrystalline film. Since the contact resistance with the silicon film 28 is also extremely small, the contact resistance between the high resistance film 18 and the drain electrode 26 can be reduced by interposing the impurity-doped polycrystalline silicon film 28.

  In FIG. 16, the high resistance film 18 is omitted. Although not shown in the drawing, the p-type base layer 23, the n-type drain layer 24, etc. may be formed shallower than the silicon oxide film 11 as in FIGS. 2 to 4 in the first embodiment. Further, similarly to the example of FIG. 5, the n-type drain layer 24 may have a constant diffusion depth by changing the length of the lateral diffusion window in triple diffusion.

  FIG. 17 is a sectional view showing the element structure of an IGBT (Insulated Gate Bipolar Transistor) according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 11 and an identical part, and the detailed description is abbreviate | omitted.

  The basic configuration is the same as that of FIG. 11, but in this embodiment, the n-type base layer 34 corresponds to the n-type drain layer 24 of FIG. 36 is formed.

  With such a configuration, it is possible to realize a lateral IGBT in which a bipolar transistor and a power MOSFET are monolithically combined in one chip. In this case, as in the first embodiment, the triple diffusion of the n-type base layer 34, the diffusion reaching the silicon oxide film 11, and the action of the high resistance film 18 cause the edge portion of the n-type base layer 34. Electric field concentration can be relaxed and breakdown voltage can be improved.

Modifications of the third embodiment are shown in FIGS. 18, the active layer 12 is thinned so that the n-type source layer 22 and the p-type drain layer 36 reach the silicon oxide film 11 as in the example of FIG. At this time, since the p-type drain layer 36 is in contact with the silicon oxide film 11, a channel of the p-type inversion layer may be formed at the bottom of the active layer. In order to prevent this, the impurity concentration of the n-type base layer 34 needs to be set high. Specifically, the impurity concentration of the n-type base layer 34 may be 1 × 10 ¹⁷ cm ⁻³ or more. Alternatively, if the p-type drain layer 36 does not reach the silicon oxide film 11 as in the example of FIG. 17, channel formation by the p-type inversion layer at the bottom of the active layer can be avoided.

  In FIG. 19, the high resistance film 18 is formed directly on the active layer 12. In FIG. 20, the high resistance film 18 is connected to the source electrode 25 instead of the gate electrode 21.

  In FIG. 21, the drain side end of the high resistance film 18 is connected to the drain electrode 26 through the impurity-doped polycrystalline silicon film 28. Also in this case, the contact resistance between the high resistance film 18 and the drain electrode 26 can be reduced by interposing the impurity-doped polycrystalline silicon film 28 as in the example of FIG.

  In FIG. 22, the high resistance film 18 is omitted. Although not shown in the drawing, the p-type base layer 23, the n-type base layer 34, and the like may be formed shallower than the silicon oxide film 11 as in FIGS. 2 to 4 in the first embodiment. Further, similarly to the example of FIG. 5, the n-type base layer 34 may have a constant diffusion depth by changing the length of the lateral diffusion window in triple diffusion.

Next, reference examples of the present invention will be described. FIG. 24 is a cross-sectional view showing a schematic configuration of the first reference example . This reference example is an example of a lateral IGBT. An n ⁻ -type high-resistance silicon layer (active layer) 52 having a thickness of 5 μm or less is formed on the silicon substrate 50 via a silicon oxide film 51.

The silicon oxide film 51 has a thickness of about 1 to 5 μm. A p base 53 layer and an n base layer (buffer layer) 54 are formed by diffusion in the active layer 52 at a depth reaching the silicon oxide film 51 at a predetermined distance. Further, an n ⁺ type source layer 55 is formed in the p base layer 53 and a p ⁺ type drain layer 56 is formed in the n base layer 54 by diffusion. A surface portion of the p base layer 53 sandwiched between the n ⁺ type source layer 55 and the n ⁻ type active layer 52 is used as a channel region, and a gate electrode 57 is formed thereon via a gate oxide film of about 60 nm. The source electrode 58 is formed to contact the n ⁺ -type source layer 55 and the p base layer 53 simultaneously, and the drain electrode 59 is formed to contact the p-type drain layer 56. An insulating protective film 60 is formed on the active layer 52 between the electrodes 58 and 59.

  FIG. 25 shows the structure of FIG. 24 in which the n-type active layer 52 is formed thick and the n-type active layer 52 remains at the bottom of the n-type buffer layer 54. An n-type buffer layer 54 is formed on the surface of the n-type active layer 52, and a p-type drain layer 56 is formed therein. The n-type buffer layer 54 functions to prevent punch-through and increase the breakdown voltage. In addition, since the hole injection efficiency from the p-type drain layer 56 is lowered, the turn-off speed is increased instead of increasing the on-resistance of the element.

FIG. 26 shows the relationship between the thickness of the n-type active layer 52 of the element having this structure, the on-resistance, the on-resistance when a current of 100 A / cm ² is passed, and the fall time at turn-off. The broken line part is the simulation result. As the n-type active layer 52 becomes thinner, the on-resistance gradually increases, but the turn-off speed is remarkably increased. In particular, when the thickness is 10 μm or less, the effect is remarkable. On the other hand, if the thickness is too thin, the on-resistance increases rapidly, so it is desirable to set the thickness of the n-type active layer 52 in the range of 4 μm to 10 μm.

FIG. 27 is a reference example in which the n-type impurity layer 63 is diffused from the entire bottom surface of the active layer 52 based on the structure of FIG. Even in this structure, there is a vertical concentration gradient in the active layer 52, the electric field concentration at the bottom of the active layer is relaxed, and a high breakdown voltage is obtained with an improved trade-off.

FIG. 28 is a reference example in which a p ⁻ type active layer 62 is used instead of the n ⁻ type active layer 52 in the structure of FIG. 27, and the n type impurity layer 61 is diffused from the entire surface of the active layer 62. . Also in this case, a high breakdown voltage can be obtained for the same reason as in the reference example of FIG.

FIG. 29 is a reference example in which an n-type impurity layer 63 is diffused from the entire bottom surface of the active layer 52 based on the structure of FIG. Even in this structure, there is a vertical concentration gradient in the active layer 52, the electric field concentration at the bottom of the active layer is relaxed, and a high breakdown voltage is obtained with an improved trade-off.

FIG. 30 shows an embodiment in which the n base layer 54 is diffused twice or more by changing the width of the diffusion window based on the structure of FIG. Even in this structure, the electric field in the lateral direction is relaxed by the effect of the double or more diffusion layers 54 ′ and 54 ″, and a high breakdown voltage is obtained with an improved trade-off as in the reference example of FIG.

  FIGS. 31 to 33 are examples in which the active layer is modified in the same manner as the examples of FIGS. 27 to 29 on the basis of the structure of FIG. Even in these structures, a high breakdown voltage can be obtained with an improved trade-off as in the embodiment of FIG.

FIG. 34 is a reference example of a thyristor partially modified with the structure of FIG. In FIG. 34, reference numeral 77 different from FIG. 24 is a gate, 78 is a cathode, and 79 is an anode. The present invention can also be applied to other lateral structure high voltage devices such as EST, MCT, GTO and the like.

FIG. 35 is an example of a lateral IGBT in which the drain portion is modified in the reference example of FIG. A high-concentration n-type layer 65 and a p-type layer 66 are formed on the surface of the p-type drain layer 56, and the drain electrode 59 is in contact with both of them. The n-type layer 65 is provided to limit the hole injection efficiency and has a function of speeding up the turn-off. In plan view, the n-type layer 65 may be a single stripe or a plurality of islands. The p-type layer 66 is provided to improve the drain contact, but may not be provided. Also in this reference example , since the n-type active layer 52 is thin and preferably set to 10 μm or less, the turn-off speed is further increased.

FIG. 36 is also a modification of the drain portion of the reference example of FIG. An anode short type IGBT in which a part of the n-type buffer layer 54 is in contact with the drain electrode 59, and the turn-off speed is high. Further, since the n-type active layer 52 is set thin, the turn-off speed is higher. In this reference example , a high-concentration n-type layer for reducing contact resistance may be provided at the contact portion between the n-type buffer layer 54 and the drain electrode 59.

FIG. 37 is a modification of the reference example of FIG. An n-type layer 67 having an impurity concentration higher than that of the n-type active layer 52 is formed at the bottom of the n-type active layer 52. Generally, when the thickness of the n-type active layer 52 is reduced, the vertical electric field under the drain is increased when a voltage is applied, and the breakdown voltage is reduced. In the element of FIG. 37, the space charge generated by depletion of the n-type layer 67 relaxes the electric field in the active layer 52 instead of increasing the electric field in the oxide film 51, so that a high breakdown voltage is maintained. Also in this reference example , since the n-type active layer 52 is thin, a fast turn-off speed can be obtained.

FIG. 38 is a modification of the reference example of FIG. Above the oxide film 51 is a p-type silicon layer 68, on which an n-type active layer 52 is diffused to form an element. By making the thickness of the p-type semiconductor layer 68 including the n-type active layer 52 thin, preferably 10 μm or less, a lateral IGBT having a high turn-off speed is obtained.

FIG. 39 is a modification of the reference example of FIG. As in the example of FIG. 38, the n-type active layer 52 is diffused and formed on the surface of the p-type silicon layer 68 separated from the silicon substrate (support substrate) 50 by the oxide film 51, and an element having the same configuration as that of FIG. Has been.

FIG. 40 is a modification of the reference example of FIG. 25, but uses a dielectric isolation substrate different from the previous modification. In order to increase the breakdown voltage, a SIPOS film 69 is provided between the n-type active layer 52 and the oxide film 51. This may be a high resistance film or a high dielectric constant film other than the SIPOS film 69. Also in this reference example , the turn-off speed is increased by setting the n-type active layer 52 thin.

Of course, the embodiment of FIG. 24 and the reference examples of FIGS. 25 and 27 to 40 can be applied to a p-channel lateral IGBT having all conductivity types reversed.

Next, a second reference example will be described. FIG. 41 is an element structure cross-sectional view showing a high voltage diode according to a second reference example . An n ⁻ -type high-resistance silicon active layer 12 is formed on the silicon substrate 10 via a silicon oxide film 11. A high impurity concentration p ⁺ -type layer 13 serving as an anode region and a high impurity concentration layer n ⁺ -type layer 14 serving as a cathode region are formed in the silicon active layer 12 at a predetermined distance. An anode electrode 15 is formed on the p ⁺ type layer 13, and a cathode electrode 16 is formed on the n ⁺ type layer 14. An n-type buffer layer 71 is formed at the bottom of the silicon active layer 12.

In the high breakdown voltage diode configured as described above, when the substrate 10 and the electrode 15 are grounded and a positive potential is applied to the electrode 16, the pn junction is reverse-biased and a depletion layer spreads in the silicon active layer 12. A depletion layer also spreads upward from the interface between the oxide film 11 and the silicon active layer 12. When the applied voltage exceeds a certain value, the silicon active layer 12 is filled with the depletion layer, and a strong electric field is generated in the silicon active layer 12 from the n ⁺ -type layer 13 downward.

Further, when the n-type buffer layer 71 formed at the bottom of the silicon active layer 12 is applied with a reverse bias and the buffer layer 71 is depleted, positive space charges are generated here. As a result of the space charge acting to relax the electric field in the silicon active layer 12, more applied voltage is shared by the intermediate oxide film at the bottom of the silicon active layer, and high breakdown voltage characteristics are obtained. The total amount of impurities in the buffer layer 71 is set to 3 × 10 ¹² cm ⁻² or less, more desirably 5 × 10 ¹¹ to 2 × 10 ¹² cm ⁻² .

FIG. 43 shows the relationship between the diffusion length 2 × (Dt) ^{1/2 of the} n-type buffer layer 71 and the breakdown voltage of the element, and the impurity doping amount is optimized for each diffusion length. This is a curve obtained when the total amount of impurities in the n-type buffer layer 71 is determined. In the range where the diffusion length is smaller than 1/2000 cm, the breakdown voltage is improved as the diffusion length is shortened, and a high breakdown voltage is obtained. In order to operate in the 200V system, a withstand voltage of 500V must be guaranteed, but a high withstand voltage of 500V or more can be obtained if the diffusion length is in a range smaller than 1/4000 cm.

  FIG. 42 shows a structure in which an n-type buffer layer 71 at the bottom of the silicon active layer 12 is selectively formed based on the structure of FIG. Since the applied voltage is greatly applied to the silicon active layer 12 immediately below the drain, a high breakdown voltage can be obtained by selectively forming the n-type buffer layer 72 only in this portion and relaxing the electric field.

  FIG. 44 shows an example in which the active layer 12 is thinner than the structure of FIG. If the active layer 12 is thin, the n-type impurity layer reaches the oxide film below the active layer. In this case, a higher breakdown voltage can be obtained by forming the n-type buffer layer at the bottom of the active layer.

  FIG. 45 shows an example in which the active layer 12 is thinner than the structure of FIG. Even in the structure in which the n-type impurity layer reaches the oxide film, the same effect can be obtained by selectively inserting the n-type buffer layer.

As described above, according to this reference example , by forming the n-type buffer layer with a short diffusion length at the bottom of the active layer, a sufficiently high breakdown voltage can be obtained with a thin active layer. The configuration in which the n-type buffer layer is provided below the active layer as in this reference example can also be applied to the first embodiment shown in FIGS.

Next, another reference example of the present invention will be described. In this reference example , a high-speed diode is formed on a dielectric isolation substrate.

FIG. 46 is a sectional view of an element structure showing a high speed diode according to a third reference example . An insulating film 83 is formed between the semiconductor substrate 81 and the high resistance n-type semiconductor substrate 82 to form a dielectric isolation substrate. A p-type anode layer 84 and an n-type cathode layer 85 are formed on the surface of a high-resistance n-type semiconductor substrate 82 of the dielectric isolation substrate. An anode electrode 86 is formed on the surface of the anode layer 84, and a surface of the cathode layer 85 is formed. Is formed with a cathode electrode 87.

Up to this point, the structure is the same as that of the conventional structure, but in this reference example , in addition to this, an n ⁺ type impurity layer 88 is selectively formed on the anode layer 84 and a p ⁺ type impurity layer 89 is formed on the cathode layer 85. The anode electrode 86 is in ohmic contact with both the anode layer 84 and the n ⁺ -type impurity layer 88, and the cathode electrode 87 is in ohmic contact with both the cathode layer 85 and the p ⁺ -type impurity layer 89. It has become. The thickness of the semiconductor substrate 82 on which the anode layer 84 and the cathode layer 85 are formed is set to 2 to 10 μm.

  FIG. 47 shows the relationship between the on-voltage Vf and reverse recovery time trr of the diode formed on the dielectric isolation substrate and the thickness ts of the semiconductor substrate 82. The reverse recovery time trr was shortened as the thickness ts of the substrate 82 was decreased. It was confirmed that trr ≦ 0.3 μsec was satisfied when ts ≦ 10 μm. However, it has been found that the on-voltage Vf increases rapidly when ts ≤ 2 µm. From this, if the thickness ts of the semiconductor substrate 82 is set to 2 to 10 μm, a diode capable of increasing the reverse recovery time without performing lifetime control such as electron beam irradiation can be realized.

Next, a fourth reference example of the present invention will be described. This reference example relates to a dielectric isolation semiconductor substrate having an insulating film layer in the middle of a semiconductor substrate. 48A and 48B show the configuration of the dielectric isolation semiconductor substrate according to the fourth reference example , in which FIG. 48A is a plan view seen from the back surface, and FIG. 48B is a cross-sectional view taken along line AA ′. Two silicon substrates 91 and 93 are integrated via an oxide film 92, and the surface of the silicon substrate 91 is polished to a predetermined thickness. A lattice-like groove 94 is formed in the silicon substrate 93, and an oxide film 95 is buried in the groove 94.

  FIG. 49 shows a manufacturing process of this dielectric isolation semiconductor substrate. After silicon direct bonding, as shown in FIG. 49A, a lattice-shaped groove 94 having a width of several μm, preferably 1 μm or less and a depth of several μm to several tens of μm is formed in the silicon substrate 93. Subsequently, as shown in FIG. 49B, the trench 94 is filled with an oxide film 95. At this time, if the groove width is about 1 μm or less, the groove 94 can be completely embedded by thermal oxidation. Thereafter, as shown in FIG. 49C, the surface of the silicon substrate 91 is polished to a predetermined thickness.

  In this dielectric isolation semiconductor substrate, since the oxide film 92 and the oxide film 95 are formed so as to sandwich the silicon substrate 93, the warpage of the substrate can be suppressed small. In the step of removing the oxide film formed on the substrate surface at the time of element formation, the oxide film 95 is removed only on the surface, and the oxide film 95 remains in the trench 94. Therefore, it is not necessary to provide a protective film so that the oxide film on the back surface is not removed as in the prior art, and the process can be simplified.

As described above, according to this reference example , even if the thickness of the intermediate oxide film is increased, it is possible to realize a dielectric-isolated semiconductor substrate having a small warp, simplifying the process, and reducing the cost of the power IC. It becomes possible to contribute to realization.

FIG. 50 is a modification of the reference example of FIG. The difference from FIG. 48 is that polysilicon 96 is formed on the surface of oxide film 95 by low pressure CVD. This reference example is effective when the width of the groove 94 is 1 μm or more. When the width of the groove 94 is 1 μm or more, it becomes difficult to fill the groove 94 only by thermal oxidation. Therefore, the portion where the embedding is insufficient is buried with polysilicon 96. Further, in this reference example , since the back surface of the substrate is polysilicon 96, there is an advantage that the oxide film 95 is not removed at all in the step of removing the oxide film at the time of element formation.

In the fourth reference example , the silicon substrate is used as the semiconductor substrate and the oxide film is used as the insulating film. However, the present invention is not limited to this, and other materials can be used. In this reference example , the dielectric isolation semiconductor substrate obtained by directly joining two semiconductor substrates is used. However, it is also effective when a dielectric isolation semiconductor substrate obtained by another method is used. FIG. 54 is a cross-sectional view showing an example of a dielectric isolation semiconductor device according to a fifth reference example . An n ⁻ type high-resistance silicon layer (active layer) 103 is formed on the silicon substrate 101 with a silicon oxide film (isolation insulating film) 102 interposed therebetween. The thickness of the silicon oxide film 102 is 3 μm, and the thickness of the n ⁻ -type active layer 103 is 0.1 μm. The impurity concentration of the n ⁻ -type active layer 103 is 1.0 × 10 ¹⁷ / cm ³ . A drain region 104 and a source region 105 are formed in the n ⁻ -type active layer 103, and a drain electrode 106 and a source electrode 107 are formed on the drain region 104 and the source region 105, respectively. Has been. Reference numerals 108 and 109 denote an insulating film and a gate electrode, respectively.

The impurity concentration distribution in the lateral direction of the n ⁻ -type active layer 103 has a three-step shape. This step-like impurity concentration distribution can be obtained as follows.

That is, a first mask is formed on the n ⁻ -type active layer 103 and phosphorus is ion-implanted with a dose of 2 × 10 ¹² cm ⁻² . Next, phosphorus is ion-implanted with a dose of 2 × 10 ¹² cm ⁻² using a second mask having a lateral opening wider than the first mask. Further, phosphorus is ion-implanted with a dose amount of 2 × 10 ¹² cm ⁻² by using a third mask having a lateral opening wider than the second mask. Note that the difference between the openings in the lateral direction of the mask is at least twice the diffusion length, preferably 3 to 4 times.

  Next, heat treatment is performed at about 1200 ° C. to diffuse the ion-implanted phosphorus, thereby obtaining a three-stage stepwise impurity concentration distribution in the horizontal direction as shown in FIG. The avalanche breakdown voltage of the dielectric isolation semiconductor element shown in FIG. 54 was measured and found to be 700V.

  In the example shown in FIG. 54, the number of steps of the stepped impurity concentration distribution is three, but can be appropriately changed within a range of 2 to 10 steps. When the number of stages is increased, the same breakdown voltage can be obtained even if the diffusion length is reduced. On the other hand, when the number of stages is reduced, it is necessary to increase the diffusion length.

  FIG. 55 is a graph showing the relationship between the number of steps and the corresponding diffusion length when the breakdown voltage of the semiconductor element is a parameter. The curve in the figure is represented by the following formula.

_{(N + 1) [a +} (V b /200)+1.5]=V b ^2/13600 formula, _{V b} is the breakdown voltage (V), a diffusion length (μm), n represents the number of stages.

As described above, according to the fifth reference example , even if the thickness of the active layer is 0.3 μm or less, the high withstand voltage lateral dielectric isolation semiconductor element can be obtained without increasing the length of the drift region. It is possible to realize.

Sectional drawing which shows the element structure of the high voltage | pressure-resistant diode concerning the 1st Example of this invention. Sectional drawing which shows the example which formed the p-type anode layer shallower than the oxide film in the 1st Example. Sectional drawing which shows the example which formed the n-type cathode layer shallower than the oxide film in the 1st Example. Sectional drawing which shows the example which formed the p-type anode layer and the n-type cathode layer shallower than the oxide film in the 1st Example. Sectional drawing which shows the example which made the triple diffusion depth of the n-type cathode layer constant in the 1st Example. Sectional drawing which shows the example which formed the p-type anode layer shallower than the oxide film in the example of FIG. Sectional drawing which shows the example which formed the n-type cathode layer by double diffusion in the 1st Example. Sectional drawing which shows the example which connected the high resistance body film | membrane to the p-type anode layer and the n-type cathode layer in 1st Example. Sectional drawing which shows the example which formed the high resistance body film | membrane directly on the active layer in the 1st Example. Sectional drawing which shows the example which abbreviate | omitted the high resistance body film | membrane in 1st Example. Sectional drawing which shows the element structure of the high voltage | pressure-resistant MOSFET concerning the 2nd Example of this invention. Sectional drawing which shows the example which formed the n-type source layer in the 2nd Example so that an oxide film might be reached. Sectional drawing which shows the example which formed the high resistance body film | membrane directly on the active layer in the 2nd Example. Sectional drawing which shows the example which connected the both ends of the high resistive film to the electrode in 2nd Example. Sectional drawing which shows the example which connected the end of the high resistance body film | membrane to the electrode through the impurity dope polycrystalline silicon film in the 2nd Example. Sectional drawing which shows the example which abbreviate | omitted the high resistive film in 2nd Example. Sectional drawing which shows the element structure of the horizontal type IGBT concerning a 3rd Example. Sectional drawing which shows the example which formed the n-type source layer and p-type drain layer to the depth which reaches an oxide film in the 3rd Example. Sectional drawing which shows the example which formed the high resistance body film | membrane directly on the active layer in the 3rd Example. Sectional drawing which shows the example which connected the both ends of the high resistance body film | membrane to the electrode in the 3rd Example. Sectional drawing which shows the example which connected the end of the high resistance body film | membrane to the electrode through the impurity dope polycrystalline silicon film in the 3rd Example. Sectional drawing which shows the example which abbreviate | omitted the high resistance body film | membrane in the 3rd Example. The characteristic view which shows the relationship between the impurity total amount of an active layer, and a proof pressure. Sectional drawing which shows the element structure of the horizontal IGBT concerning a 1st reference example . FIG. 25 is a cross-sectional view showing a reference example in which an active layer is formed thick with the configuration of FIG. 24. The characteristic view which shows the relationship between ON voltage and switching OFF time with respect to active layer thickness. 25 is a cross-sectional view showing a reference example in which an n-type impurity layer is diffused from the entire surface of the active layer based on the structure of FIG. FIG. 28 is a cross-sectional view showing a reference example using a p ⁻ type active layer instead of an n ⁻ type active layer in the structure of FIG. 27. FIG. 25 is a cross-sectional view showing a reference example in which an n-type impurity layer is diffused from the entire bottom surface of the active layer based on the structure of FIG. 24. FIG. 25 is a cross-sectional view showing an embodiment in which an n base layer is diffused twice or more by changing the width of a diffusion window based on the structure of FIG. 24. FIG. 31 is a cross-sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire surface of the active layer based on the structure of FIG. 30. FIG. 32 is a cross-sectional view showing an example in which a p ⁻ -type active layer is used instead of an n ⁻ -type active layer in the structure of FIG. 31. FIG. 31 is a cross-sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire bottom surface of the active layer based on the structure of FIG. 30. FIG. 25 is a cross-sectional view showing a reference example of a thyristor partially deformed with the structure of FIG. 24. FIG. 26 is a cross-sectional view showing an example of a lateral IGBT in which the drain portion is modified in the reference example of FIG. FIG. 26 is a sectional view showing an example in which the drain portion of the reference example of FIG. 25 is modified. FIG. 26 is a cross-sectional view showing an example in which the reference example of FIG. 25 is modified. FIG. 26 is a cross-sectional view showing an example in which the reference example of FIG. 25 is modified. FIG. 26 is a cross-sectional view showing an example in which the reference example of FIG. 25 is modified. FIG. 26 is a cross-sectional view showing an example in which the reference example of FIG. 25 is modified. The element structure sectional view showing the high voltage diode concerning the 2nd reference example . FIG. 42 is a cross-sectional view showing an example in which an n-type buffer layer at the bottom of the active layer is selectively formed based on the structure of FIG. The characteristic view which shows the relationship between the diffusion length 2 * (Dt) ^{1/2 of a} buffer layer, and element breakdown voltage. FIG. 42 is a cross-sectional view showing an example in which the buffer layer at the bottom of the active layer is selectively formed based on the structure of FIG. 41. FIG. 42 is a cross-sectional view showing an example in which the active layer is thin with respect to the structure of FIG. The element structure sectional view showing the high voltage diode concerning the 3rd reference example . The characteristic view which shows the relationship between ON voltage Vf and reverse recovery time trr of the diode formed in the dielectric isolation substrate, and thickness ts of the semiconductor substrate. The top view and sectional drawing which show schematic structure of the dielectric material isolation semiconductor substrate concerning a 4th reference example . FIG. 49 is a cross-sectional view showing a manufacturing step of the dielectric isolation semiconductor substrate of FIG. 48. FIG. 49 is a cross-sectional view showing a modification of the reference example of FIG. 48. Sectional drawing which shows the prior art example of the horizontal type | mold high voltage | pressure-resistant diode using a dielectric isolation structure. The characteristic view which shows the relationship between a diffusion length and a breakdown voltage. The characteristic view which shows the relationship between the number of steps, and a breakdown voltage. Sectional drawing which shows an example of the dielectric isolation semiconductor element which concerns on a 5th reference example . The characteristic view which shows the impurity concentration distribution of the horizontal direction of an active layer when performing diffusion 3 times in an active layer. FIG. 5 is a characteristic diagram showing the relationship between the number of steps and the diffusion length when the breakdown voltage of the element is a parameter. Sectional drawing which shows the prior art example of the horizontal type | mold high voltage | pressure-resistant diode using a dielectric isolation structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... Silicon oxide film (isolation insulating film), 12 ... n ^- type high resistance silicon layer (active layer), 13 ... p-type anode layer (second conductivity type impurity layer), 14 ... n-type cathode Layer (first conductivity type impurity layer), 15 ... anode electrode, 16 ... cathode electrode, 18 ... high resistance film, 21 ... gate electrode, 23 ... p-type base layer, 24 ... n-type drain layer, 25 ... source electrode 26 ... Drain electrode, 28 ... Impurity-doped polycrystalline silicon film, 34 ... N-type base layer, 36 ... P-type drain layer.

Claims (5)

A semiconductor substrate, an insulating layer formed on the semiconductor substrate , an active layer made of a first resistance type high-resistance semiconductor formed on the insulating layer and having a thickness of 0.3 μm or less, and A first impurity layer of a first conductivity type formed in the active layer; and a second impurity of a second conductivity type formed in the active layer and formed at a predetermined distance from the first impurity layer. A first electrode formed on the first impurity layer, and a second electrode formed on the second impurity layer, wherein the first impurity layer comprises: A high withstand voltage semiconductor element characterized in that the lateral impurity concentration distribution is in the form of 2 to 10 steps each having a Gaussian distribution, and the interval between the steps is at least twice the diffusion length . 2. The high breakdown voltage semiconductor element according to claim 1 , wherein at least one of the first impurity layer and the second impurity layer reaches a bottom of the active layer . A third impurity layer of a second conductivity type formed in the first impurity layer is further provided, and the first electrode is formed on the third impurity layer. Item 3. The high breakdown voltage semiconductor element according to Item 1 or 2. 4. The high withstand voltage semiconductor element according to claim 1, further comprising a high resistance layer on a portion of the active layer located between the first and second impurity layers. The fourth impurity layer of the first conductivity type formed in the second impurity layer at a predetermined distance from the active layer, and the active layer and the fourth impurity layer positioned between the active layer and the fourth impurity layer. 4. The high electrode according to claim 1, further comprising an insulator formed on the second impurity layer and a third electrode formed on the insulator. 5. Withstand voltage semiconductor element.

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