JP4891288B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which a high breakdown voltage MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a low breakdown voltage MISFET are formed on the same semiconductor substrate.

  The high withstand voltage MISFET is used for a driver of a liquid crystal display device, a motor control driver that performs high current control, or a nonvolatile memory that requires a high voltage for programming.

  In this high voltage MISFET, in addition to forming a thick gate insulating film, various measures are taken to increase the voltage resistance.

  For example, in Japanese Patent Laid-Open No. 11-177047, among a plurality of types of field effect transistors having different gate insulating film thicknesses, a gate insulating film 10 of one transistor is formed by a laminated film of a thermal oxide film 8 and a deposited film 9. The technology to form is described (refer patent document 1).

Japanese Laid-Open Patent Publication No. 2000-68385 discloses a field stopper region NW (FD) of a high breakdown voltage NMOS transistor, a well region NW of a low breakdown voltage PMOS transistor, and a channel stopper NW of a well HNW region of a high breakdown voltage PMOS transistor. A technique of forming simultaneously with (CS) is described (see Patent Document 2).
JP-A-11-177047 JP 2000-68385 A

  As shown in FIG. 40, the present inventors have studied to improve the drain withstand voltage by providing the electric field relaxation layers 9 and 8 around the source and drain regions 17 and 18 of the high withstand voltage MISFET (Qn2, Qp2). .

  However, in the structure of the MISFET shown in FIG. 40, since the gate insulating film 5 under the gate electrode FG is thin, the gate insulating film is cut at the end portion, and a problem arises that the withstand voltage cannot be secured. Further, since the electric field relaxation layers 9 and 8 are separated at both ends of the source and drain regions 17 and 18, electric field concentration is likely to occur at the boundary between the electric field relaxation layer and the source and drain regions. As a result, problems such as a decrease in drain breakdown voltage and a decrease in electrostatic breakdown strength occurred.

  Among these problems, a structure as shown in FIG. 41 in which the source and drain regions 17 and 18 are covered with the electric field relaxation layers 9 and 8 in order to relax electric field concentration at the boundary between the electric field relaxation layer and the source and drain regions. Although it has been studied, the problem of a decrease in breakdown voltage due to the cutting of the gate insulating film 5 at the end of the gate electrode has not been solved.

  On the other hand, as shown in FIG. 42, it has been studied to improve the breakdown voltage by providing the field oxide film 4a at the end of the gate electrode FG. In this case, the electric field relaxation layers 9 and 8 and the source and drain regions 17 are used. , 18 could not alleviate the electric field concentration at the boundary.

  It should be noted that the functions and the like of each part in FIGS. 40 to 42 will be clarified by the embodiment of the invention, and detailed description thereof will be omitted.

  An object of the present invention is to provide a miniaturized structure of a high breakdown voltage MISFET and a manufacturing method thereof.

  Another object of the present invention is to provide a structure of a high-breakdown-voltage MISFET that suppresses the influence of a parasitic MOS and a manufacturing method thereof.

  Another object of the present invention is to provide a high-performance, high-breakdown-voltage MISFET structure and a method for manufacturing the same.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a MISFET formed on a semiconductor substrate, wherein (a) a first insulating film formed on the semiconductor substrate, and (b) on the semiconductor substrate. A gate insulating film of the formed MISFET; (c) a gate electrode of the MISFET formed on the gate insulating film; and (d) a source and drain region of the MISFET formed on the semiconductor substrate. A first semiconductor region that is a part; and (e) a second semiconductor region that has a higher impurity concentration than the first semiconductor region, is formed in the semiconductor substrate, and is a part of the source and drain regions of the MISFET. The first semiconductor region is formed so as to surround the second semiconductor region, and a junction position with the semiconductor substrate is the first insulation region. The first insulating film is formed so as to be embedded in a groove formed in the semiconductor substrate by polishing, and the gate insulating film is formed to the deeper position than the film. A second insulating film formed on the semiconductor substrate; and a third insulating film formed on the second insulating film and thicker than the second insulating film; and in a gate length direction of the MISFET The third insulating film is formed so that an end portion thereof is positioned on the first insulating film, and both end portions of the gate electrode are formed on the third insulating film in the gate length direction of the MISFET. And located on the first insulating film.

  The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a MISFET formed on a semiconductor substrate, wherein (a) a first insulating film formed on the semiconductor substrate, and (b) on the semiconductor substrate. A gate insulating film of the formed MISFET; (c) a gate electrode of the MISFET formed on the gate insulating film; and (d) a source and drain region of the MISFET formed on the semiconductor substrate. A first semiconductor region that is a part; and (e) a second semiconductor region that has a higher impurity concentration than the first semiconductor region, is formed in the semiconductor substrate, and is a part of the source and drain regions of the MISFET. A semiconductor region, wherein the first semiconductor region is formed so as to surround the first insulating film and the second semiconductor region, and the first insulating film includes: The gate insulating film is formed so as to be embedded in a groove formed in the semiconductor substrate, and the gate insulating film includes a second insulating film formed on the semiconductor substrate and the second insulating film. And a third insulating film that is thicker than the second insulating film. In the gate length direction of the MISFET, the end of the third insulating film is the first insulating film. It is formed so as to be located above, and in the gate length direction of the MISFET, both end portions of the gate electrode are located on the first insulating film via the third insulating film.

  The method for manufacturing a semiconductor integrated circuit device according to the present invention includes a step of forming a first insulating film between first MISFET formation regions and a second MISFET formation region, and second and third steps on a semiconductor substrate surface between the first insulating films. Forming an insulating film; forming a first conductive film on the third insulating film in the second region where the second MISFET is formed; and third and second insulating layers in the first region where the first MISFET is formed. After removing the film, the method includes a step of forming a fourth insulating film in the first region and a step of forming a second conductive film on the fourth insulating film. The third insulating film remains.

  According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a first insulating film between first MISFET formation regions and a second MISFET formation region, and forming a first semiconductor region in the first region where the first MISFET is formed Forming a second semiconductor region in the second region where the second MISFET is to be formed; forming a second and third insulating film in the first and second regions; Removing the second insulating film, removing a part of the second and third insulating films on the second semiconductor region in the second region, and forming a first opening; and a third region in the second region Forming a first conductive film to be the gate electrode of the second MISFET on the insulating film; forming a fourth insulating film in the first region; and a second to be the gate electrode of the first MISFET on the fourth insulating film. Step of forming a conductive film and before the first region A third semiconductor region having a conductivity type opposite to that of the first semiconductor region is provided on both sides of the gate electrode, and a fourth conductivity type having the same conductivity type as that of the second semiconductor region is provided below the first opening in the second region. Introducing impurities into the surface of the semiconductor substrate to form a semiconductor region.

  According to a method of manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a first insulating film in a first region where a first MISFET is formed and a second region where a second MISFET is formed; Depositing a first conductive film on the first insulating film; removing the first insulating film and the first conductive film in the first region; and the first region on the semiconductor substrate. And a step of forming a second insulating film, a step of depositing a second conductive film in the first and second regions, and an energy reaching the substrate in the first region in the first and second regions. And implanting impurities from above the second conductive film.

  The semiconductor integrated circuit device of the present invention includes a first insulating film located between the first MISFET formation regions of the first region where the first MISFET is formed and between the second MISFET formation regions of the second region where the second MISFET is formed, A second insulating film formed in the second region, a third insulating film formed on the first insulating film in the second region and the second insulating film, and a first conductivity on the third insulating film in the second region. A film, a fourth insulating film formed in the first region, and a second conductive film formed on the fourth insulating film in the first region.

  The semiconductor integrated circuit device according to the present invention includes a second semiconductor region formed in the semiconductor substrate in the second region and having a conductivity type opposite to the first semiconductor region formed in the first region, and the second semiconductor. A third insulating film having a first opening on the second semiconductor region in the region and formed on the first and second insulating films; and below the first opening, And a fourth semiconductor region of the conductivity type formed in the second semiconductor region.

  The semiconductor integrated circuit device according to the present invention includes a first insulating film located between each MISFET formation region of the first region where the first MISFET is formed and the second region where the second MISFET is formed, and the semiconductor in the second region. A second insulating film formed on a substrate surface; a third insulating film formed in a second region; a first conductive film on the third insulating film in a second region; and the semiconductor substrate in a first region A fourth insulating film formed on the surface; and a second conductive film formed on the fourth insulating film in the first region.

  The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.

  According to the present invention, since the silicon oxide film 5c (third insulating film) is formed on the field oxide film 4 and the silicon oxide film 104 (first insulating film) formed in the trench, the field oxide film 4 and the like. The threshold potential of the parasitic MOS formed on the substrate can be increased.

  Further, according to the present invention, the low withstand voltage MISFET threshold value is obtained when the conductive film (second conductive film) constituting the gate electrode of the low withstand voltage MISFET is present on the gate electrode (first conductive film) of the high withstand voltage MISFET. Since the adjustment impurity is implanted, the occurrence of the NBT phenomenon can be suppressed.

  In addition, according to the present invention, a miniaturized high-performance semiconductor integrated circuit device can be formed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
A method for manufacturing the semiconductor integrated circuit device of this embodiment will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 1, a semiconductor substrate 1 made of p-type single crystal silicon is prepared. The semiconductor substrate 1 includes a region LN where a low breakdown voltage n-channel type MISFET Qn1 is formed, a region LP where a low breakdown voltage p-channel type MISFET Qp1 is formed, a region HN where a high breakdown voltage n-channel type MISFET Qn2 is formed, and a high breakdown voltage p-channel type. It has a region HP where the MISFET Qp2 is formed and a region CA where the capacitive element C is formed.

  A silicon oxide film 2 is formed by subjecting the surface of the semiconductor substrate 1 to an oxidation treatment. Subsequently, after the silicon nitride film 3 is selectively formed on the silicon oxide film, as shown in FIG. 2, the silicon nitride film 3 is used as a mask to perform a thermal oxidation process to thereby form a field having a thickness of about 300 nm. An oxide film 4 (first insulating film) is formed. The field oxide film 4 separates the MISFET formation regions LN, LP, HN, and HP. Here, in the high breakdown voltage MISFETs Qn2 and Qp2 formation regions (HN, HP), field oxide films 4a are also formed below both ends of the gate electrode FG, which will be described later. This field oxide film 4a is formed to improve the breakdown voltage of the high breakdown voltage MISFETs Qn2 and Qp2. Subsequently, the silicon nitride film 3 on the semiconductor substrate 1 is removed by wet etching using hot phosphoric acid.

  Next, as shown in FIG. 3, a resist film R1 is formed on the high breakdown voltage n-channel MISFET formation region HN and the capacitor element formation region CA. Next, phosphorus is ion-implanted using the resist film R1 as a mask. The ion implantation energy at this time is also lower than the field oxide films 4 and 4a in the low breakdown voltage n-channel MISFET formation region LN, the low breakdown voltage p-channel MISFET formation region LP, and the high breakdown voltage p-channel MISFET formation region HP. Set to be typed in. Next, the resist film R1 is removed (FIG. 4).

Next, as shown in FIG. 4, a resist film R2 is formed on the low breakdown voltage n-channel MISFET formation region LN, the low breakdown voltage p-channel MISFET formation region LP, and the high breakdown voltage p-channel MISFET formation region HP. Next, boron is ion-implanted using the resist film R1 as a mask. The ion implantation energy at this time is set so that boron is also implanted under the field oxide films 4 and 4a in the high breakdown voltage n-channel MISFET formation region HN and the capacitor element formation region CA.
Next, after removing the resist film R2, an n-type isolation region 6 (n-type well 6) and a p-type well 7 are formed by performing heat treatment at 1200 ° C. (FIG. 5). In the present embodiment, the p-type well 7 is formed under the field oxide films 4 and 4a in the capacitive element formation region CA. However, the n-type well 6 may be formed.

  Next, as shown in FIG. 5, a resist film R3 is formed on the region other than the vicinity of the source and drain regions of the high breakdown voltage p-channel type MISFET Qp2. Next, boron is ion-implanted using the resist film R3 as a mask. The ion implantation energy at this time is set so that boron is also implanted under the field oxide films 4 and 4a in the high breakdown voltage p-channel type MISFET formation region HP.

  Next, the resist film R3 is removed, and a resist film R4 is formed on a region other than the vicinity of the source and drain regions of the high breakdown voltage n-channel type MISFET Qn2 as shown in FIG. Next, phosphorus is ion-implanted using the resist film R4 as a mask. The ion implantation energy at this time is set so that phosphorus is also implanted under the field oxide films 4 and 4a in the high breakdown voltage n-channel MISFET formation region HN.

  Next, by removing the resist film R4 and performing heat treatment, the p-type field relaxation layer 8 is formed in the vicinity of the source and drain regions of the high breakdown voltage p-channel type MISFET Qp2, and the p-type field relaxation layer 8 is disposed in the vicinity of the source and drain regions of the high breakdown voltage n-channel type MISFET Qn2. Then, the n-type electric field relaxation layer 9 is formed.

  Next, as shown in FIG. 7, a resist film R5 is formed on a region other than the low breakdown voltage p-channel type MISFET Qp1 formation region LP. Next, phosphorus is ion-implanted using the resist film R5 as a mask, and heat treatment is performed to form an n-type well 9b. At the time of this ion implantation, an n-type well 9c may be formed by ion implantation under the field oxide film 4 in the high breakdown voltage p-channel type MISFET formation region HP (FIG. 8). The n-type well 9c is formed to raise the threshold potential Vt of a parasitic MOS (Metal Oxide Semiconductor) formed on the field oxide film 4. In particular, the n-type isolation region 6 and the p-type well 7 are set so that the impurity concentration thereof becomes lower as it approaches the surface of the semiconductor substrate 1 in order to ensure the breakdown voltage of the high breakdown voltage MISFETs Qn2 and Qp2 formed on the main surface. Has been. As a result, the threshold potential Vt of the parasitic MOS tends to decrease. Here, the parasitic MOS means that when the first layer wiring is formed on the field oxide film 4 via the interlayer insulating film SZ (see FIG. 22B), the field oxide film 4 and the interlayer insulating film SZ are gated. An undesired MOS having an insulating film and a first layer wiring as a gate electrode. When the threshold potential Vt of the MOS is low, current easily flows under the field oxide film 4.

  Next, as shown in FIG. 8, a resist film R6 is formed on a region other than the low breakdown voltage n-channel MISFET Qn1 formation region LN. Next, boron is ion-implanted using the resist film R6 as a mask, and heat treatment is performed to form a p-type well 8b (FIG. 9). At the time of this ion implantation, the p-type well 8c may be formed by ion implantation of boron also under the field oxide film 4 in the high breakdown voltage n-channel type MISFET formation region HN. The p-type well 8c is also formed in order to raise the threshold potential Vt of the parasitic MOS formed on the field oxide film 4, similarly to the n-type well 9c.

  Next, as shown in FIG. 9, impurities are ion-implanted on the semiconductor substrate 1. This impurity is used to adjust the threshold potential Vt of the high breakdown voltage MISFETs Qn2 and Qp2. In FIG. 9, ion implantation is performed on the entire surface of the semiconductor substrate 1, but by implanting desired impurities into the high breakdown voltage n-channel type MISFET formation region HN and the high breakdown voltage p channel type MISFET formation region HP, respectively. The threshold voltage Vt of the high voltage MISFETs Qn2 and Qp2 may be adjusted.

  Next, after removing the thin silicon oxide film 2 on the surface of the semiconductor substrate 1, a silicon oxide film 5a (second insulating film) which becomes a part of the gate insulating film 5 is formed by thermal oxidation. Next, a silicon oxide film 5b (third insulating film) is deposited on the semiconductor substrate 1 by low pressure chemical vapor deposition (LPCVD). The film thickness of the silicon oxide film 5b is set larger than the film thickness of the silicon oxide film 5a.

  Next, as shown in FIG. 11A, the gate electrode formation scheduled region of the high breakdown voltage MISFETs Qn2, Qp2, the high breakdown voltage n channel type MISFET formation region HN, the high breakdown voltage p channel type MISFET formation region HP, and the capacitor element formation region CA are formed. The silicon oxide film 5 b is patterned so that the silicon oxide film 5 b remains on the field oxide film 4. Here, the low breakdown voltage n channel type MISFET formation region LN and the field oxide film 4 on the low breakdown voltage p channel type MISFET formation region LP (the boundary between the high breakdown voltage portion and the low breakdown voltage portion, in the figure, the p channel type MISFET formation region LP). A silicon oxide film 5b on the high breakdown voltage n-channel MISFET formation region HN and the low breakdown voltage p-channel MISFET formation region LP (except for the field oxide film 4 on the boundary). Does not remain. The reason why the silicon oxide film 5b is left on the field oxide film 4 in the capacitive element formation region CA is to reduce parasitic capacitance with the substrate (p-type well 7).

  As shown in FIG. 11, the field oxide film 4 on these regions (LN, LP) is formed with a width of 1 μm or less for high integration of elements (MISFETs Qn1, Qn2, etc.) formed in the low withstand voltage portion. Is done. Therefore, it is difficult to pattern the silicon oxide film 5b so that the silicon oxide film 5b remains on the narrow field oxide film 4 formed in the low withstand voltage portion, and mask displacement is likely to occur. When this mask displacement occurs, the silicon oxide film 5b may extend over the source / drain formation planned region and the gate electrode formation planned region of the MISFETs Qn1, Qn2. As a result, there arises a problem that the widths of the source and drain regions and gate electrodes of the MISFETs Qn1 and Qn2 are reduced. In order to avoid such a problem, the silicon oxide film 5b on the field oxide film 4 in the low breakdown voltage portion is removed.

  Further, as shown in FIG. 11B, a semiconductor region (first semiconductor region 9d or 8d) for supplying a power supply potential or a ground potential (fixed potential) to the n-type isolation region 6 and the p-type well 7 (4 semiconductor region), the silicon oxide film 5b is also removed (opening according to claim). The semiconductor region 9d or 8d has the same conductivity type as the n-type isolation region 6 or p-type well 7 in which it is formed. At least one semiconductor region 9d or 8d is formed inside the n-type isolation region 6 and the p-type well 7, and a power supply potential and a ground potential are applied to each.

  Further, since the silicon oxide film 5b on the source and drain regions of the MISFETs Qn1, Qp1, Qp2, and Qn2 has been removed, it becomes possible to simultaneously ion-implant regions of the same conductivity type among these regions. The number can be reduced, and the process can be shortened.

  Next, the film quality of the silicon oxide film 5b is improved by performing a heat treatment at 900 ° C., preferably 1000 ° C. or higher. The silicon oxide film after the heat treatment is designated as 5c (FIG. 12). The silicon oxide film 5c on the gate electrode formation scheduled region of the high breakdown voltage MISFETs Qn2 and Qp2 becomes a part of the gate insulating film 5. That is, the silicon oxide film 5c and the silicon oxide film 5a constitute the gate insulating films of the high voltage MISFETs Qn2 and Qp2. As described above, by performing high-temperature heat treatment on the silicon oxide film 5b, the film quality of the silicon oxide film 5b can be made to be equivalent to that of the thermal oxide film. When the silicon oxide film 5b is not subjected to heat treatment and is used as a gate insulating film, the silicon oxide film 5b contains a large number of trap levels, making it difficult to adjust the threshold potential Vt.

  In addition, the high breakdown voltage n-channel MISFET formation region HN, the high breakdown voltage p-channel MISFET formation region HP, and the silicon oxide film 5c on the field oxide film 4 in the capacitive element formation region CA are formed as parasitic MOSs on these regions. The threshold potential Vt can be increased.

  Since the silicon oxide film 5b is formed by LPCVD, the etching ratio with the field oxide films 4 and 4a, which are thermal oxide films, can be increased. Therefore, the surface of the field oxide films 4 and 4a is hardly etched. The silicon oxide film 5b can be etched. As a result, the thickness of the field oxide film 4 can be ensured, and the threshold potential Vt of the parasitic MOS formed on this can be kept large.

  Next, as shown in FIG. 13, a polycrystalline silicon film (polysilicon) 10 is deposited on the semiconductor substrate 1 by the CVD method. Polycrystalline silicon may be reacted in an atmosphere containing phosphorus to contain phosphorus impurities in the polycrystalline silicon film 10. Further, phosphorus may be doped after the polycrystalline silicon film 10 is formed.

  Next, as shown in FIG. 14A, the polycrystalline silicon film 10 is patterned so as to remain on the gate insulating films 5 (5a, 5c) of the high breakdown voltage MISFETs Qn2, Qp2. This polycrystalline silicon film becomes the gate electrode FG (first conductive film) of the high voltage MISFETs Qn2 and Qp2. At this time, the polycrystalline silicon film 10 is also left on the silicon oxide film 5c in the capacitive element formation region CA (third region). This polycrystalline silicon film 10 becomes the lower electrode LE of the capacitive element C. Here, the gate electrodes of the high breakdown voltage MISFETs Qn2 and Qp2 are formed of the polycrystalline silicon film 10 (FG). However, as will be described in detail later, the gate electrodes of the high breakdown voltage MISFETs Qn2 and Qp2 will be described later. 11 (SG). FIGS. 14B and 16B are explanatory diagrams when the gate electrodes of the high breakdown voltage MISFETs Qn2 and Qp2 are formed of the polycrystalline silicon film 11. FIG.

  Next, as shown in FIG. 15, impurities are ion-implanted on the semiconductor substrate 1. This impurity is used to adjust the threshold potential Vt of the low breakdown voltage MISFETs Qn1 and Qp1. The threshold potential Vt of the low breakdown voltage MISFETs Qn1 and Qp1 may be adjusted by ion-implanting desired impurities into the low breakdown voltage n-channel MISFET formation region LN and the low breakdown voltage p-channel MISFET formation region LP, respectively.

  Next, as shown in FIG. 16A, after the thin silicon oxide film 5a on the low breakdown voltage n-channel type MISFET formation region LN and the low breakdown voltage p channel type MISFET formation region LP is removed, the low breakdown voltage MISFETs Qn1, Qp1 A silicon oxide film to be the gate insulating film 5d (fourth insulating film) is formed by thermal oxidation. At this time, the gate electrodes FG of the high breakdown voltage MISFETs Qn2 and Qp2 are also slightly oxidized. Further, the surface of the lower electrode LE is also slightly oxidized to form a silicon oxide film (not shown). This silicon oxide film becomes a capacitive insulating film of the capacitive element C. In order to increase the reliability of the capacitive element C, after depositing the polycrystalline silicon film 10 to be the lower electrode LE, a silicon nitride film is formed in advance on the polycrystalline silicon film 10 so that it can be used as a capacitive insulating film. Good.

  As described above, in the above-described steps, removal of the thin oxide film on the surface of the semiconductor substrate such as removal of the silicon oxide film 2 and the silicon oxide film 5a is repeatedly performed. The surface is also etched and the film thickness decreases. However, according to the present embodiment, since the film thickness can be compensated for by the silicon oxide film 5c on the field oxide film 4, the threshold potential Vt of the parasitic MOS formed on the upper portion can be maintained high, and the element Parasitic generation under the field oxide film due to the interconnects between them can be suppressed. Of course, the threshold potential Vt of the parasitic MOS needs to be higher than the voltage applied to the element. Here, the voltage applied to the MISFETs Qn1 and Qp1 of the low withstand voltage portion is, for example, about 3.6V, and the voltage applied to the MISFETs Qn2, Qp2 of the high withstand voltage portion is, for example, about 20V. It is more effective to make the silicon oxide film 5c thicker than the silicon oxide films 2 and 5d.

  Next, a polycrystalline silicon film 11 is deposited on the semiconductor substrate 1 by a CVD method. Next, the polycrystalline silicon film 11 is patterned so as to remain on the gate insulating films 5d of the low breakdown voltage MISFETs Qn1 and Qp1. The polycrystalline silicon film 11 becomes the gate electrode SG (second conductive film) of the low breakdown voltage MISFETs Qn1 and Qp1. At this time, the polycrystalline silicon film 11 is also left on the capacitive insulating film (not shown) on the lower electrode LE in the capacitive element formation region CA. This polycrystalline silicon film 11 becomes the upper electrode UE of the capacitive element C. The gate electrode SG may be formed by forming a tungsten silicide layer on the surface of the polycrystalline silicon film 11 and then patterning it. The tungsten silicide layer is formed by depositing a metal film such as a tungsten film on the polycrystalline silicon film 11 and performing a heat treatment. This silicide layer is formed to reduce the resistance of the gate electrode SG.

  Next, the source and drain regions of the low breakdown voltage MISFETs Qn1 and Qp1 and the high breakdown voltage MISFETs Qn2 and Qp2 are formed. The formation of these source and drain regions will be described below.

  As shown in FIG. 17, a resist film R7 is formed on the semiconductor substrate 1, and an opening is formed on the low breakdown voltage n-channel MISFET formation region LN. Next, phosphorus is ion-implanted using the resist film R7 and the gate electrode SG of the low breakdown voltage MISFET Qn1 as a mask.

  Next, after removing the resist film R7, as shown in FIG. 18, a resist film R8 is formed on the semiconductor substrate 1, and the low breakdown voltage p-channel type MISFET formation region LP is opened. Next, boron is ion-implanted using the resist film R8 and the gate electrode SG of the low breakdown voltage MISFET Qp1 as a mask.

Next, after removing the resist film R8, the implanted phosphorous and boron are thermally diffused on both sides of the gate electrodes SG of the low breakdown voltage MISFETs Qn1 and Qn2, respectively, thereby causing the p ⁻ type semiconductor region 14 and the n ⁻ type semiconductor region 13 to be diffused. (FIG. 19).

  Next, as shown in FIG. 19, a silicon oxide film is deposited on the semiconductor substrate 1 and then etched back to form a sidewall film 16s on the side walls of the gate electrodes SG of the low breakdown voltage MISFETs Qn1 and Qn2.

Next, as shown in FIG. 20, a resist film R9 is formed on the gate electrode FG of the low breakdown voltage p-channel MISFET formation region LP, the high breakdown voltage p-channel MISFET formation region HP, and the high breakdown voltage n-channel MISFET Qn2. Next, both sides of the gate electrodes (SG, FG) of the low breakdown voltage n-channel type MISFET Qn1 and the high breakdown voltage n-channel type MISFET Qn2 are obtained by ion-implanting arsenic (As) using the resist film R9 as a mask, annealing, and activating. Then, an n ⁺ type semiconductor region 17 (source and drain regions) is formed (FIG. 21).

Next, as shown in FIG. 21, a resist film R10 is formed on the gate electrode FG of the low breakdown voltage n-channel MISFET formation region LN, high breakdown voltage n-channel MISFET formation region HN, and high breakdown voltage p-channel MISFET Qp2. Next, boron is ion-implanted using the resist film R10 as a mask, annealed, and activated, so that p is formed on both sides of the gate electrodes (SG, FG) of the low breakdown voltage p-channel type MISFET Qp1 and the high breakdown voltage p-channel type MISFET Qp2. ^{A +} type semiconductor region 18 (source and drain regions) is formed (FIG. 22A). At this time, boron is not implanted under the field oxide films 4, 4a and the silicon oxide film 5c.

  Here, the reason why the resist films R7 and R8 are left on the gate electrodes FG of the high breakdown voltage MISFETs Qn2 and Qp2 is to prevent the gate electrode FG from being charged by ion implantation and causing dielectric breakdown of the gate oxide film. is there.

Through the steps so far, the source and drain of the LDD (Lightly Doped Drain) structure (n ⁻ type semiconductor region 13 and n ⁺ type semiconductor region 17, p ⁻ type) are formed in the low breakdown voltage portion (LN, LP (first region)). Low breakdown voltage MISFETs Qn1 and Qp1 (first MISFETs) including the semiconductor region 14 and the p ⁺ type semiconductor region 18) are formed. Further, high breakdown voltage MISFETs Qn2 and Qp2 (second MISFETs) are formed in the high breakdown voltage portions (HN, HP (second region)).

  Next, an interlayer insulating film SZ made of a silicon oxide film or the like is deposited on these MISFETs Qn1, Qn2, Qp1, Qp2 and the capacitive element C, and contact holes (not shown) are formed on desired regions, and then contacted A first layer wiring M1 is formed on the interlayer insulating film including the inside of the hole (see FIG. 22B). Further, a multilayer wiring can be formed on the first layer wiring M1 by repeating the formation of the interlayer insulating film and the wiring metal. Further, a protective film covering the entire chip is formed on the uppermost layer wiring, but the drawing and detailed description thereof are omitted.

  In the present embodiment, the gate electrodes SG of the low breakdown voltage MISFETs Qn1 and Qp1 are formed of the polycrystalline silicon film 11, and the gate electrodes FG of the high breakdown voltage MISFETs Qn2 and Qp2 are formed of the polycrystalline silicon film 10. It is also possible to form the gate electrode from the polycrystalline silicon film 11.

  That is, as shown in FIG. 14B, after the deposition of the polycrystalline silicon film 10 of the present embodiment (see FIG. 13), the polycrystalline silicon film 10 is formed only on the silicon oxide film 5c in the capacitor element formation region CA. The lower electrode LE is formed by remaining.

  Next, impurities are ion-implanted on the semiconductor substrate 1 in order to adjust the threshold potential Vt of the low breakdown voltage MISFETs Qn1 and Qp1 (see FIG. 15). Next, as shown in FIG. 16B, the thin silicon oxide film 5a on the low breakdown voltage n-channel type MISFET formation region LN and the low breakdown voltage p channel type MISFET formation region LP is removed, and the gate insulation of the low breakdown voltage MISFETs Qn1 and Qp1 is removed. A silicon oxide film to be the film 5d is formed by thermal oxidation.

  Next, a polycrystalline silicon film 11 is deposited on the semiconductor substrate 1 by a CVD method, and the polycrystalline silicon film 11 is formed on the gate insulating films 5 (5a, 5c) of the high breakdown voltage MISFETs Qn2, Qp2 and the low breakdown voltage MISFETs Qn1, Qp1. Patterning is performed so as to remain on the gate insulating film 5d.

  According to the above process, the gate electrodes of the low breakdown voltage MISFETs Qn1 and Qp1 and the high breakdown voltage MISFETs Qn2 and Qp2 can be formed simultaneously by the polycrystalline silicon film 11 (SG). The gate electrodes of the low breakdown voltage MISFETs Qn1, Qp1 and the high breakdown voltage MISFETs Qn2, Qp2 can be formed of the polycrystalline silicon film 10 (FG). In the subsequent deposition and patterning steps of the polycrystalline silicon film 11, The polycrystalline silicon film 11 remains on the side wall of the gate electrode, which affects the characteristics of the MISFET. Therefore, it is desirable to form these gate electrodes with the polycrystalline silicon film 11.

(Embodiment 2)
In the first embodiment, the field oxide film 4 is used for isolation between the MISFET formation regions LN, LP, HN, and HP. However, the isolation may be performed using an oxide film embedded in the trench.

  A method for manufacturing the semiconductor integrated circuit device of the present embodiment will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 23, a semiconductor substrate 1 made of p-type single crystal silicon is prepared. The semiconductor substrate 1 includes a region LN where a low breakdown voltage n-channel type MISFET Qn1 is formed, a region LP where a low breakdown voltage p-channel type MISFET Qp1 is formed, a region HN where a high breakdown voltage n-channel type MISFET Qn2 is formed, and a high breakdown voltage p-channel type. It has a region HP in which the MISFET Qp2 is formed.

  A silicon oxide film 2 is formed by subjecting the surface of the semiconductor substrate 1 to an oxidation treatment. Subsequently, after the silicon nitride film 3 is selectively formed on the silicon oxide film, the semiconductor substrate 1 is etched using the silicon nitride film 3 as a mask to form a trench having a depth of about 300 nm as shown in FIG. U is formed. Here, in the high breakdown voltage MISFETs Qn2 and Qp2 formation regions (HN, HP), grooves are also formed at both lower portions of the gate electrode described later.

  Next, the substrate 1 is thermally oxidized at about 1000 ° C. to form a thin silicon oxide film (not shown) having a thickness of about 10 nm on the inner wall of the groove. This silicon oxide film is formed to recover the damage caused by dry etching on the inner wall of the groove and to relieve stress generated at the interface between the silicon oxide film 104 embedded in the groove and the substrate 1 in the next step. To do.

  Next, as shown in FIG. 25, a silicon oxide film 104 is deposited by CVD on the substrate 1 including the inside of the groove, and the silicon oxide film 104 on the upper part of the groove is formed using the silicon nitride film 3 as a stopper film. The surface is flattened by mechanical and mechanical polishing. Next, by removing the silicon nitride film 3, a silicon oxide film 104a for improving the breakdown voltage of the element isolation 104 and the high breakdown voltage MISFETs Qn2 and Qp2 is completed (FIG. 26A).

  Here, as shown in FIG. 26B, the surfaces of the silicon oxide films 104 and 104a are thin before the cleaning of the semiconductor substrate surface or the formation of the silicon oxide film 5a in the subsequent impurity implantation process or the like during the above-described polishing. Due to the removal of the silicon oxide film 2 or the like, a phenomenon (recess phenomenon) that the surfaces of the silicon oxide films 104 and 104a recede at the end of the groove occurs. As this recess phenomenon occurs, various problems such as deterioration of the breakdown voltage of the MISFET and occurrence of a kink phenomenon may occur as will be described in detail later. In the following drawings, the receding of the surface of the silicon oxide films 104 and 104a is not shown for easy understanding of the drawings.

  Of the subsequent steps, the same steps as those in the first embodiment are avoided, and only the outline is described.

  First, as shown in FIG. 27, boron is ion-implanted under the silicon oxide films 104 and 104a in the high breakdown voltage n-channel MISFET formation region HN to form the p-type well 6.

  Further, phosphorus is ion-implanted under the silicon oxide films 104 and 104a in the high breakdown voltage p-channel type MISFET formation region HP to form the n-type well 7.

  The implantation energy of ions (phosphorus and boron) at this time is set so that ions are also implanted under the silicon oxide films 104 and 104a in the high breakdown voltage n-channel type MISFET formation region HN and the high breakdown voltage p channel type MISFET formation region HP. To do.

  Next, as shown in FIG. 28, p-type electric field relaxation layer 8 is formed by ion implantation of boron in the vicinity of the source and drain regions of high breakdown voltage p-channel type MISFET Qp2. Further, the n-type electric field relaxation layer 9 is formed by ion implantation of phosphorus in the vicinity of the source and drain regions of the high breakdown voltage n-channel type MISFET Qn2. The implantation energy of ions (phosphorus and boron) at this time is set so that ions are implanted also under the silicon oxide films 104 and 104a.

  Next, as shown in FIG. 29, after the thin silicon oxide film 2 on the surface of the semiconductor substrate 1 is removed, a silicon oxide film 5a which becomes a part of the gate insulating film 5 is formed by thermal oxidation. Next, a silicon oxide film 5b is deposited on the semiconductor substrate 1 by a low pressure chemical vapor deposition method. Next, the silicon oxide film 5b remains on the silicon oxide film 104 in the gate electrode formation scheduled region of the high breakdown voltage MISFETs Qn2 and Qp2, the high breakdown voltage n channel MISFET formation region HN, and the high breakdown voltage p channel MISFET formation region HP. The silicon oxide film 5b is patterned. Here, the silicon oxide film 104 on the low breakdown voltage n-channel MISFET formation region LN and the low breakdown voltage p-channel MISFET formation region LP (the boundary between the high breakdown voltage portion and the low breakdown voltage portion, in the drawing, the formation of the high breakdown voltage n channel MISFET). On the boundary between the region HN and the low breakdown voltage p-channel type MISFET formation region LP (except the field oxide film 4), the silicon oxide film 5b does not remain. This is because, as described in the first embodiment, since the width of the silicon oxide film 104 on these regions is narrow, the reduction of the width of the source, drain region or gate electrode of the MISFETs Qn1 and Qn2 due to mask displacement is prevented. Because.

  Next, the film quality of the silicon oxide film 5b is improved by performing a heat treatment at 900 ° C. or higher. The silicon oxide film after the heat treatment is designated as 5c. The silicon oxide film 5c on the gate electrode formation scheduled region of the high breakdown voltage MISFETs Qn2 and Qp2 becomes a part of the gate insulating film 5. That is, the silicon oxide film 5c and the silicon oxide film 5a constitute the gate insulating film 5 of the high voltage MISFETs Qn2 and Qp2.

  Further, the silicon oxide film 5c on the silicon oxide film 104 in the high breakdown voltage n-channel type MISFET formation region HN and the high breakdown voltage p channel type MISFET formation region HP increases the threshold potential Vt of the parasitic MOS formed on these regions. can do.

  In addition, since the silicon oxide film 5b is formed by LPCVD, the etching ratio with the silicon oxide films 104 and 104a can be increased. Therefore, the silicon oxide film 5b is formed without almost etching the surface of the silicon oxide films 104 and 104a. It can be etched. As a result, the thickness of the silicon oxide film 104 can be ensured, and the threshold potential Vt of the parasitic MOS formed on the silicon oxide film 104 can be increased. In addition, the amount of receding of the surface of the silicon oxide films 104 and 104a due to the recess phenomenon described above can be reduced.

  Next, as shown in FIG. 30, a polycrystalline silicon film 10 is deposited on the semiconductor substrate 1 by the CVD method. The polycrystalline silicon film 10 may contain impurities such as phosphorus. Next, the polycrystalline silicon film 10 is patterned so as to remain on the gate insulating films 5 (5a, 5c) of the high breakdown voltage MISFETs Qn2, Qp2. This polycrystalline silicon film 10 becomes the gate electrode FG of the high voltage MISFETs Qn2 and Qp2.

  Next, as shown in FIG. 31, p-type well 8b is formed by ion implantation of boron into low breakdown voltage n-channel MISFET formation region LN. At the time of this ion implantation, the p-type well 8c may be formed by ion implantation of boron also under the silicon oxide film 104 in the high breakdown voltage n-channel type MISFET formation region HN. Further, the n-type well 9b is formed by ion implantation of phosphorus into the low breakdown voltage p-channel type MISFET formation region LP. At the time of this ion implantation, the n-type well 9c may be formed by ion implantation of boron also under the silicon oxide film 104 in the high breakdown voltage p-channel type MISFET formation region HP. The p-type well 8c and the n-type well 9c are formed to increase the threshold potential Vt of the parasitic MOS formed on the silicon oxide film 104.

  Next, as shown in FIG. 32, after removing the thin silicon oxide film 5a on the low breakdown voltage n-channel type MISFET formation region LN and the low breakdown voltage p channel type MISFET formation region LP, the gate insulating films of the low breakdown voltage MISFETs Qn1 and Qp1 5d is formed by thermal oxidation.

  Next, a polycrystalline silicon film 11 is deposited on the semiconductor substrate 1 by a CVD method. Next, the polycrystalline silicon film 11 is patterned so as to remain on the gate insulating films 5d of the low breakdown voltage MISFETs Qn1 and Qp1. This polycrystalline silicon film 11 becomes the gate electrode SG of the low breakdown voltage MISFETs Qn1 and Qp1. The gate electrode SG may be formed by forming a tungsten silicide layer on the surface of the polycrystalline silicon film 11 and then patterning it. This silicide layer is formed to reduce the resistance of the gate electrode SG.

Next, as shown in FIG. 33A, n ⁻ type semiconductor regions 13 are formed by ion implantation of phosphorus on both sides of the gate electrode SG of the low breakdown voltage MISFET Qn1. Further, boron is ion-implanted on both sides of the gate electrode SG of the low breakdown voltage MISFET Qn2, thereby forming the p ⁻ type semiconductor region.

  Next, after forming the silicon oxide film 15 on the gate electrodes FG and SG, a silicon oxide film is deposited on the semiconductor substrate 1 and etched back, whereby a laminated film of the gate electrodes FG and SG and the silicon oxide film 15 is formed. A side wall film 16s is formed on the side wall.

Next, arsenic is ion-implanted on both sides of the gate electrodes (SG, FG) of the low breakdown voltage n-channel type MISFET Qn1 and the high breakdown voltage n-channel type MISFET Qn2, thereby forming the n ⁺ type semiconductor region 17. Further, by implanting boron ions, p ⁺ -type semiconductor regions 18 are formed on both sides of the gate electrodes (SG, FG) of the low breakdown voltage p-channel type MISFET Qp1 and the high breakdown voltage p-channel type MISFET Qp2. At this time, arsenic and boron are not implanted under the silicon oxide films 104 and 104a and the silicon oxide film 5c.

Through the steps up to here, the source and drain of the LDD (Lightly Doped Drain) structure (n ⁻ type semiconductor region 13 and n ⁺ type semiconductor region 17, p ⁻ type semiconductor region 14 and p Low breakdown voltage MISFETs Qn1 and Qp1 having ⁺ type semiconductor regions 18) are formed. Further, high breakdown voltage MISFETs Qn2 and Qp2 are formed in the high breakdown voltage portions (HN, HP).

  As described above, according to the present embodiment, the thickness of the silicon oxide film 104 can be ensured, so that the occurrence of recesses can be reduced. As a result, it is possible to reduce the breakdown voltage and the occurrence of the kink phenomenon due to the recess. Here, the breakdown voltage is reduced by the concentration of the electric field on the stepped portion of the surface of the silicon oxide film 104 generated by the occurrence of the recess. Also. The kink phenomenon is a phenomenon in which the drain current increases in a region where the gate voltage is small in the sub-threshold characteristic of the MISFET (characteristic due to the relationship between the gate voltage (horizontal axis) and the drain current (vertical axis)) and shows a two-stage waveform. Say.

  FIG. 33 (b) is an enlarged view of FIG. 33 (a), and also illustrates the recess described with reference to FIG. 26 (b).

  Next, multilayer wiring is formed by repeating the formation of an interlayer insulating film and wiring metal on these MISFETs Qn1, Qn2, Qp1, and Qp2, and a protective film covering the entire chip is formed on the uppermost layer wiring. Although formed, the drawings and detailed description are omitted.

(Embodiment 3)
A method for manufacturing the semiconductor integrated circuit device of this embodiment will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 34, the semiconductor substrate 1 in which the gate electrode FG is formed on the gate insulating film 5 (5a, 5c) of the high breakdown voltage MISFETs Qn2, Qp2 is prepared. Since the manufacturing process of this semiconductor substrate 1 is the same as the process of Embodiment 1 demonstrated with reference to FIGS. 1-14, the description is abbreviate | omitted. Note that since the semiconductor substrate shown in FIG. 34 includes the silicon oxide film 5c over the silicon oxide films 104 and 104a, the thickness of the silicon oxide film 104 is ensured as in the first embodiment. It is possible to increase the threshold potential Vt of the parasitic MOS formed above this.

  Next, as shown in FIG. 35, after removing the thin silicon oxide film 5a on the low breakdown voltage n-channel type MISFET formation region LN and the low breakdown voltage p channel type MISFET formation region LP, the gate insulating films of the low breakdown voltage MISFETs Qn1 and Qp1 5d is formed by thermal oxidation. At this time, the gate electrodes FG of the high breakdown voltage MISFETs Qn2 and Qp2 are also slightly oxidized (5e). Further, the surface of the lower electrode LE is also slightly oxidized to form a silicon oxide film (5f) (FIG. 35). The silicon oxide film 5f becomes a capacitive insulating film of the capacitive element C. In order to increase the reliability of the capacitive element C, a silicon nitride film may be formed in advance on the polycrystalline silicon film 10 after the deposition of the polycrystalline silicon film 10 to be the lower electrode LE to form a capacitive insulating film.

  Next, the gate insulating film 5d is nitrided by performing heat treatment in a nitrogen atmosphere. In this way, by introducing nitrogen into the interface of the gate insulating film 5d, fluctuations in the threshold potential Vt due to hot carriers generated at the drain end can be suppressed.

  Next, as shown in FIG. 36, a polycrystalline silicon film 111 is deposited on the semiconductor substrate 1 by the CVD method. This polycrystalline silicon film 111 becomes a part of the gate electrode SG of the low breakdown voltage MISFETs Qn1 and Qp1.

  Here, if this nitriding treatment is performed after an impurity implantation step for adjusting a threshold potential Vt, which will be described later, impurities are diffused by this nitriding treatment, making it difficult to adjust the threshold potential Vt. On the other hand, even when the impurity implantation step is performed after the nitriding treatment, when the polycrystalline silicon film 111 is formed after the impurity implantation step, the impurity is implanted with the gate insulating film 5d exposed. As a result, there arises a problem that the gate insulating film 5d is contaminated by heavy metal existing in the ion implantation apparatus.

  Therefore, as will be described below, impurities are ion-implanted onto the semiconductor substrate 1 through the polycrystalline silicon film 111 with the polycrystalline silicon film 111 formed on the gate insulating film 5d.

  First, as shown in FIG. 36, impurities are ion-implanted on the semiconductor substrate 1 in order to adjust the threshold potential Vt of the low breakdown voltage MISFET Qn1. Next, as shown in FIG. 37, impurities are ion-implanted on the low breakdown voltage p-channel type MISFET formation region LP. This impurity is used to adjust the threshold potential Vt of the low breakdown voltage MISFET Qp1. At this time, since the silicon oxide film 5e and the polycrystalline silicon film 111 are formed on the gate electrodes FG of the high breakdown voltage MISFETs Qn2 and Qp2, the impurities remain in these films, and the gate insulating film 5 (5a 5c) can prevent impurities from being implanted.

  When impurities are implanted into the gate insulating film 5, the so-called NBT (negative bias temperature) problem becomes significant. This is a phenomenon in which the threshold potential Vt is increased only by applying a negative potential to the gate electrode of the p-channel type MISFET. This phenomenon is particularly noticeable when the gate electrode is p-type. This phenomenon is considered to be deeply related to the presence of boron in the gate insulating film, and is likely to occur when impurities are included in the gate insulating film.

  However, in the present embodiment, impurities can be prevented from being implanted into the gate insulating film 5, and the occurrence of the NBT phenomenon can be reduced.

  Next, a polycrystalline silicon film 111 b is deposited on the polycrystalline silicon film 111. The polycrystalline silicon films 111 and 111b become the gate electrodes SG of the low breakdown voltage MISFETs Qn1 and Qp1. Therefore, the polycrystalline silicon films 111 and 111b are patterned so as to remain on the gate insulating film 5d (FIG. 38). At this time, the polycrystalline silicon films 111 and 111b are also left on the silicon oxide film 5f on the lower electrode LE in the capacitive element formation region CA. The polycrystalline silicon films 111 and 111b become the upper electrode UE of the capacitive element C. Note that the gate electrode SG may be formed by patterning after forming a tungsten silicide layer on the surface of the polycrystalline silicon film 111b. The tungsten silicide layer is formed by depositing a metal film such as a tungsten film on the polycrystalline silicon film 111b and performing heat treatment. This silicide layer is formed to reduce the resistance of the gate electrode SG.

  In the patterning of the polycrystalline silicon film 10 described above, only the polycrystalline silicon film 10 on the low breakdown voltage portion (LN, LP) is removed, and the polycrystalline silicon film 10 on the high breakdown voltage portion (HN, HP) is removed. Patterning may be performed after forming the gate electrode SG.

  As described above, the gate electrode SG of the low breakdown voltage MISFETs Qn1 and Qp1 is a laminated film of the polycrystalline silicon film 111 and the polycrystalline silicon film 111b because the impurities for adjusting the threshold potential of the low breakdown voltage MISFETs Qn1 and Qp1 are accurately obtained. This is for ion implantation. That is, when ion implantation is performed through the polycrystalline silicon film 111 having a large film thickness before this ion implantation, it is difficult to control impurities, and a desired threshold potential Vt cannot be obtained.

  Further, as described above, when the silicide layer is formed on the gate electrode SG, if the polycrystalline silicon film 111 constituting the gate electrode is thin, the silicon in the lower gate insulating film also undergoes a silicidation reaction. The breakdown voltage of the gate insulating film 5d is lowered.

  However, in the present embodiment, since the gate electrode SG of the low breakdown voltage MISFETs Qn1 and Qp1 is a laminated film of the polycrystalline silicon film 111 and the polycrystalline silicon film 111b, impurities for adjusting the threshold potential are ion-implanted with high accuracy. In addition, the breakdown voltage of the gate insulating film 5d can be ensured.

  Next, the source and drain regions of the low breakdown voltage MISFETs Qn1 and Qp1 and the high breakdown voltage MISFETs Qn2 and Qp2 are formed, but the subsequent steps are the same as those in the first embodiment described with reference to FIGS. The description is omitted.

  In the present embodiment, as shown in FIG. 34, the high breakdown voltage MISFETs Qn2, Qp2, the gate electrode formation scheduled region, the high breakdown voltage n channel type MISFET formation region HN, the high breakdown voltage p channel type MISFET formation region HP, and the capacitive element Although the semiconductor substrate 1 in which the silicon oxide film 5c is formed on the field oxide film 4 in the formation region CA is used, even if the step of forming the silicon oxide film 5c is omitted, boron is present in the gate oxide film 5a. Since the injection can be prevented, the occurrence of the above-described NBT phenomenon can be suppressed.

  FIG. 39 shows a cross-sectional view of the main part of the semiconductor substrate when the silicon oxide film 5c is not formed. The method for manufacturing the semiconductor integrated circuit device is the same as the steps described in the first embodiment (excluding the step of forming the silicon oxide film 5c) and the present embodiment, and the description thereof is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor integrated circuit device and a manufacturing technique thereof, and is particularly suitable for a semiconductor integrated circuit device in which a high breakdown voltage MISFET and a low breakdown voltage MISFET are formed on the same semiconductor substrate and a manufacturing technique thereof.

It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 2 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is principal part sectional drawing of the board | substrate which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is a figure for demonstrating the subject of this invention. It is a figure for demonstrating the subject of this invention. It is a figure for demonstrating the subject of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Silicon oxide film 3 Silicon nitride film 4 Field oxide film 4a Field oxide film 5 Gate insulating film 5a Silicon oxide film 5b Silicon oxide film 5c Silicon oxide film 5d Gate insulating film 5f Silicon oxide film 6 N-type isolation region ( n-type well)
7 p-type well 8 p-type field relaxation layer 8b p-type well 8c p-type well 8d semiconductor region 9 n-type field relaxation layer 9b n-type well 9c n-type well 9d semiconductor region 10 polycrystalline silicon film 11 polycrystalline silicon film 13 n ⁻ Type semiconductor region 14 p ⁻ type semiconductor region 16s side wall film 17 n ⁺ type semiconductor region (source and drain regions)
18 p ⁺ type semiconductor region (source and drain regions)
104 Silicon oxide film 104a Silicon oxide film 111 Polycrystalline silicon film 111b Polycrystalline silicon film FG Gate electrode SG Gate electrode SZ Interlayer insulating film U Groove C Capacitance element UE Upper electrode LE Lower electrode R1 to R10 Resist film M1 First layer wiring CA Capacitance element formation region HN High breakdown voltage n-channel type MISFET formation region HP High breakdown voltage p-channel type MISFET formation region LN Low breakdown voltage n-channel type MISFET formation region LP Low breakdown voltage p-channel type MISFET formation region Qn1 Low breakdown voltage n-channel type MISFET
Qn2 High voltage n-channel MISFET
Qp1 Low breakdown voltage p-channel MISFET
Qp2 high voltage p-channel MISFET

Claims (7)

A semiconductor integrated circuit device having a MISFET formed on a semiconductor substrate,
(A) a first insulating film formed on the semiconductor substrate and made of a silicon oxide film;
(B) a gate insulating film of the MISFET formed on the semiconductor substrate;
(C) a gate electrode of the MISFET formed on the gate insulating film;
(D) a first semiconductor region formed on the semiconductor substrate and serving as part of the source and drain regions of the MISFET;
(E) a second semiconductor region having a higher impurity concentration than the first semiconductor region, formed in the semiconductor substrate, and serving as part of the source and drain regions of the MISFET;
Have
The first semiconductor region is formed so as to surround the second semiconductor region, and a junction position with the semiconductor substrate is formed to a position deeper than the first insulating film,
The first insulating film is formed so as to be polished and embedded in a groove formed in the semiconductor substrate,
The gate insulating film includes a second insulating film formed on the semiconductor substrate, and a third insulating film formed on the second insulating film and thicker than the second insulating film. ,
The second insulating film and the third insulating film are made of a silicon oxide film,
In the gate length direction of the MISFET, the third insulating film is formed so that an end thereof is positioned on the first insulating film,
2. A semiconductor integrated circuit device according to claim 1, wherein both ends of the gate electrode are located on the first insulating film through the third insulating film in the gate length direction of the MISFET. A semiconductor integrated circuit device having a MISFET formed on a semiconductor substrate,
(A) a first insulating film formed on the semiconductor substrate and made of a silicon oxide film;
(B) a gate insulating film of the MISFET formed on the semiconductor substrate;
(C) a gate electrode of the MISFET formed on the gate insulating film;
(D) a first semiconductor region formed on the semiconductor substrate and serving as part of the source and drain regions of the MISFET;
(E) a second semiconductor region having a higher impurity concentration than the first semiconductor region, formed in the semiconductor substrate, and serving as part of the source and drain regions of the MISFET;
Have
The first semiconductor region is formed so as to surround the first insulating film and the second semiconductor region,
The first insulating film is formed so as to be polished and embedded in a groove formed in the semiconductor substrate,
The gate insulating film includes a second insulating film formed on the semiconductor substrate, and a third insulating film formed on the second insulating film and thicker than the second insulating film. ,
The second insulating film and the third insulating film are made of a silicon oxide film,
In the gate length direction of the MISFET, the third insulating film is formed so that an end thereof is positioned on the first insulating film,
2. A semiconductor integrated circuit device according to claim 1, wherein both ends of the gate electrode are located on the first insulating film through the third insulating film in the gate length direction of the MISFET. The semiconductor integrated circuit device according to claim 1 or 2,
The semiconductor integrated circuit device, wherein the MISFET is formed in the order of a channel region, the first semiconductor region, the first insulating film, and the second semiconductor region in the gate length direction. The semiconductor integrated circuit device according to claim 1, 2, or 3,
The semiconductor integrated circuit device, wherein the first semiconductor region and the second semiconductor region are made of an impurity having a p-type conductivity type. The semiconductor integrated circuit device according to claim 1, 2, or 3,
The semiconductor integrated circuit device, wherein the first semiconductor region and the second semiconductor region are made of an n-type conductivity impurity. In the semiconductor integrated circuit device according to claim 1,
The semiconductor integrated circuit device, wherein the MISFET constitutes a part of a circuit for driving a liquid crystal display device. The semiconductor integrated circuit device according to any one of claims 1 to 6,
The semiconductor integrated circuit device, wherein the gate electrode has a structure including a polycrystalline silicon film and a silicide film formed on the polycrystalline silicon film.

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