JPH1197685A - Vertical field-effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical field-effect transistor having a low on-resistance reduced by reducing the cell size and small gate-source capacitance. SOLUTION: This manufacturing method comprises forming a first conductivity-type epitaxial layer 2 on a first conductivity-type semiconductor substrate 1, forming a second conductivity-type base region 3 on the epitaxial layer 2, forming a trench T at least at the base region 3, embedding a conductor 5 for forming a gate via a gate oxide film 4 in the trench T, forming first conductivity-type source regions 6 at both sides of the trench T, forming source electrodes 8 on the source regions 6, and depositing a drain electrode 9 on the substrate 1. The source regions 6 are formed self-alignedly, using an insulation film for forming the trench T and conductor 5 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical field-effect transistor, and more particularly, to a vertical field-effect transistor capable of reducing the size of a cell, reducing operating resistance, and reducing gate-source capacitance, and its manufacture. About the method.

[0002]

2. Description of the Related Art A vertical field effect transistor has been rapidly developed in recent years because it is a voltage-driven device and can operate in a high frequency range. Recently, particularly required characteristics of a device include a reduction in resistance during operation and a reduction in parasitic capacitance.

As a technique for reducing the resistance during operation, a method has recently been proposed in which a groove (trench) is formed in a semiconductor substrate and the side wall of the groove is used as a channel. As an example, IEEE TRANSACTION (198
VOL ED-34 P2329-P2 issued in November 1995
334), this example will be described with reference to FIG.

First, as shown in FIG. 10A, an N + semiconductor substrate 1 doped with arsenic and having a resistivity of about 4 mΩ · cm is prepared, and the surface thereof has a thickness of about 5.5 μm and an impurity concentration of 1 to 5.
After growing the N-epitaxial layer 2 of 3 × 10 ¹⁶ cm ⁻³ , the oxide film 11 and the nitride film 14 are grown. Next, a P base region 3 is formed to a depth of about 2.5 μm by boron ion implantation and heat treatment.
An oxide film 15 is formed sequentially.

[0005] As shown in FIG.
A rectangular trench of m is formed by RIE (reactive ion etching), and a gate oxide film 4 of about 2000 ° is formed. As shown in FIG. 10 (c), after growing polysilicon 5 of about 8000 °, phosphorus is diffused, polysilicon is further grown and the trench is filled with polysilicon 5, and then polysilicon 5 is removed by RIE. Etch back,
Gate polysilicon 5 is formed.

As shown in FIG. 11A, after selectively oxidizing a portion of the polysilicon 5 where no nitride film is present, the nitride film is removed and PR
After patterning by the method described above, a N + source region 6 having a depth of 1 μm is formed by phosphorus ion implantation and heat treatment. FIG.
As shown in FIG. 1B, a source electrode 8 is formed by sputtering aluminum having a thickness of 3 μm, a metal is applied to the back surface, and sintering is performed to form a drain electrode 9.

This plan view is shown in FIG. 12. In order to make the P base region 3 the same potential as the source electrode 8, the N + source region 6 and the P base region 3 are formed so as to be perpendicular to the trench. In the above example, the trench is rectangular, but with recent advances in lithography technology, the trench is formed in a lattice or staggered pattern, thereby increasing the channel width per unit area and further reducing the operating resistance. It is considered that this is the case, but these examples will be described.

The steps are the same up to FIG. As shown in FIG. 13A, after selectively oxidizing a portion of the polysilicon 5 where the nitride film 14 is not present, the nitride film 14 is removed.
After patterning between the lattice-shaped trenches by PR or the like, an N + source region 6 having a depth of 1 μm is formed in an independent cell by phosphorus ion implantation and heat treatment.

As shown in FIG. 13B, the source electrode 8 is formed by sputtering aluminum having a thickness of 3 μm, depositing a metal on the back surface, performing sintering, and forming a drain electrode 9.
This plan view is shown in FIG. FIG. 14A shows an example in which trenches are formed in a lattice shape, and FIG. 14B shows an example in which the trenches are arranged in a staggered manner.

[0010] Since the conventional vertical field effect transistor is configured as described above, it is necessary to consider the deviation of PR (photoresist) because the ion implantation is performed using a mask material such as a resist at the time of ion implantation for forming the source. However, it is difficult to reduce the size of the crystal and the cell, and there is a disadvantage that the on-resistance per unit area increases.

In addition, when the polysilicon serving as the gate is etched back, it is necessary that the source region and the polysilicon overlap with each other. However, it is necessary to allow a margin in the depth of the source region for improving the yield. As a result, there is a disadvantage that the overlapping portion becomes large and the parasitic capacitance between the gate and the source becomes large.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art and to realize a reduction in operating resistance (on-resistance) in a vertical field effect transistor having a trench. Another object of the present invention is to provide a vertical field effect transistor having a low parasitic capacitance and a method of manufacturing the same.

Another object of the present invention is to provide a vertical field effect transistor which is smaller than a conventional cell size. Still another object of the present invention is to provide a vertical field-effect transistor having a reduced _{hfe of} a parasitic transistor parasitic on the vertical transistor and having a high breakdown strength, and a method of manufacturing the same.

[0014]

In order to achieve the above object, the present invention basically employs the following technical configuration. That is, as a first aspect according to the present invention, a first conductivity type epitaxial layer is formed on a first conductivity type semiconductor substrate, a second conductivity type base region is formed on the epitaxial layer, Forming a trench in the region, burying a conductor serving as a gate in the trench via a gate oxide film, forming a first conductivity type source region on both sides of the trench, and forming a source electrode on the source region And a method of manufacturing a vertical field effect transistor in which a drain electrode is attached to the semiconductor substrate, wherein the source region is formed in a self-aligned manner by using an insulating film for forming the trench and the conductor as a mask material. And the second
In one embodiment, a first conductivity type epitaxial layer is formed on a first conductivity type semiconductor substrate, a trench is formed in at least the epitaxial layer, and a conductor serving as a gate is formed in the trench via a gate oxide film. A method of manufacturing a vertical field-effect transistor, wherein the source region is buried, a first conductivity type source region is formed on both sides of the trench, a source electrode is formed on the source region, and a drain electrode is attached to the semiconductor substrate. The base region and the source region are formed in a self-aligned manner by using an insulating film for forming a trench and the conductor as a mask material, and as a third embodiment, A back gate portion of the second conductivity type is formed on the base region.

[0015]

Next, an embodiment of the present invention will be described in detail. Referring to FIG. 1, an embodiment of the present invention uses a semiconductor substrate having an N− type epitaxial layer 2 on an N + type semiconductor substrate 1, and a unit cell is formed on the main surface of the wafer.

In the formation of the U-shaped trench T, a P-type base region 3 is first formed, a CVD oxide film as an insulating film is grown, and the CVD oxide film is patterned by lithography, and this oxide film is used as a mask material. A silicon etch is performed to form a U groove T in the epitaxial layer 2. Thereafter, a gate oxide film 4 is formed, polysilicon 5 is deposited, and the polysilicon 5 is etched back.

At this time, the surface of the polysilicon 5 is slightly lower than the main surface of the wafer. Next, this polysilicon 5 and CVD (chemical vapor deposition) are used.
arsenic As is ion-implanted by rotationally sloping ion implantation using the oxide film as a mask and activated to form the source region 6. After that, BPSG (boron pho
An insulating film 7 such as sporossilicate glass is formed, the main surface of the wafer is etched, and a metal such as aluminum is applied to form a lease electrode 8, and a drain electrode 9 is formed on the back surface of the semiconductor substrate.

FIG. 1A is a sectional view taken along the line AA ′ of FIG.
It is a plane sectional view showing the state seen from the part. According to the vertical transistor of the present invention configured as described above, in the case of an N-channel, when a + potential is applied to the gate, as shown in FIG. When the surface is inverted to the N-type semiconductor (channel 10) and an appropriate potential is applied to the source / drain, electrons are emitted from the source electrode 8, the source region 6, the channel 10, the N-epitaxial layer 2, N
+ The semiconductor substrate 1 and the drain electrode 9 flow. The operating resistance (on-resistance) can be calculated from the relationship between the flowing current and the generated source-drain voltage, and the on-resistance is shown as the sum of the above.

Here, focusing attention on the channel, it is known that the channel resistance is generally expressed by the following equation. Rch = (L / W) · μ · Cox (V−V _T ) (L: channel length, W: channel width, μ: mobility, Co
x capacity V: gate voltage, _VT : gate threshold voltage
According to the present invention, since the unit cell can be reduced, the channel width W per unit area increases, the channel resistance Rch decreases, and the resistance (on-resistance) during operation can be reduced. Become. In addition, a self-alignment (self-alignment) between a conductor serving as a gate electrode and an insulating film is performed.
gment), the overlap between the gate and the source region can be reduced, and the parasitic capacitance between the source and the gate can be reduced.

Further, since the source region is formed in a self-aligned manner, there is no need to consider the loss of PR, so that the size can be reduced, and the overlap between the gate electrode and the source region can be minimized. An accident in which the gate electrode and the source region do not overlap and a channel is not formed can be prevented.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of a vertical field effect transistor according to the present invention will be described in detail with reference to the drawings. 1 to 5, a first conductivity type epitaxial layer 2 is formed on a first conductivity type semiconductor substrate 1 and the epitaxial layer 2
A base region 3 of the second conductivity type is formed thereon, and a trench T is formed in at least the base region 3.
A conductor 5 serving as a gate is buried therein via a gate oxide film 4 and a first conductivity type source region 6 is provided on both sides of the trench T.
And forming a source electrode 8 on the source region 6 and a drain electrode 9 on the semiconductor substrate 1 in the method of manufacturing a vertical field effect transistor. A method for manufacturing a vertical field-effect transistor, characterized in that the source region 6 is formed in a self-aligned manner by using the mask and the conductor 5 as a mask, and FIG. width W _S of the source region 6 is substantially equal to the state depicted relative to the width W _T. In this case W _S / W _T is desirably 0.8 to 1.2.

The embodiment of the present invention will be further described with reference to FIGS. 3 and 4. As shown in FIG.
An N + epitaxial layer 2 doped with about 2 × 10 ¹⁶ cm ⁻³ of phosphorus P on an N + type semiconductor substrate 1 doped with 0 ¹⁹ cm ^−3.
Is used for growing the substrate about 5 μm. As shown in FIG. 3A, first, an oxide film 11 of about 200 ° is grown, the boron ion is 70 keV, and the DOSE amount is 1 to 3 × 10 ¹³ cm.
Ion implantation is performed under the condition of ^-3
Heat treatment is performed for up to 20 minutes to form the P-type base region 3 such that the diffusion depth is about 1 to 1.5 μm. Thereafter, the oxide film may or may not be removed.

As shown in FIG. 3B, the CVD oxide film 12
Is grown on the main surface of the wafer by about 1000 to 5000
The CVD oxide film 12 is etched by a lithography technique, and then Si is etched so as to remove the P-type base region 3. At this time, etching is performed so as to form a lattice shape or a staggered shape with a width of 0.35 to 0.8 μm to form a trench T.

As shown in FIG. 3C, 200 to 1000
A gate oxide film 4 having a thickness of Å is formed,
Growing polysilicon 5 containing a high concentration of phosphorus of 0 °,
A trench T of Si is buried, and the polysilicon 5 is etched back to a depth of 0.3 to 0.6 μm from the semiconductor main surface. The polysilicon 5 may be grown without any impurities, and then formed by ion implantation or diffusion.

As shown in FIG. 4A, ion implantation is performed using the buried polysilicon 5 and the CVD oxide film 12 as a mask for Si etching as a mask material. The ion implantation conditions are such that arsenic As ions are used and the accelerating voltage is about 50 to 10
0 keV, DOSE amount 5 × 10 ¹⁵ -5 × 10 ¹⁶ cm ^-3 ,
The rotation is performed at an angle of about 45 °.

Thereafter, heat treatment is performed at 1000 ° C. for about 10 to 30 minutes to activate the ion-implanted atoms to form the source region 6. As shown in FIG. 4B, an interlayer insulating film 7 such as BPSG is grown, reflowed at a temperature of 800 to 900 ° C., and etched back to the semiconductor main surface. FIG.
As shown in (c), Al is deposited on the main surface to form a source electrode 8 and Au or the like is deposited on the surface to form a drain electrode 9.

Next, the operation of the vertical field effect transistor of the present invention will be described with reference to FIG. FIG. 5 (a) is a sectional view of the present invention, and FIG. 5 (b) is a sectional view of a conventional technique. In the present invention, the gate polysilicon 5 and C
Since the diffusion layer is formed by self-alignment with the VD oxide film 12, the distance (PR margin) between the source region 6 and the contact portion between the source aluminum and the source region 6 may be small. , 5 can be reduced.

As a result, the cell size of the unit can be reduced from 5 μm square to about 3 μm square, and the cell area is reduced by about 60% as compared with the conventional case. The channel width per unit area increases by about 35%, and the channel resistance becomes about 3%.
5% reduction. Further, since the overlap B between the source region 6 and the gate polysilicon 5 can be reduced,
The source-to-source capacitance is reduced by about 20% compared to the conventional case.

FIG. 5 to the indicated W _C, W _T, W _S is the width of each unit cell, the width of the trench T, the width of the source regions 6, but according to the prior art W _C, W _T, W _S is In the vertical field effect transistor of the present invention, 4.5, 0.5, and 1.25, respectively, were 3, 0.5, and 1.25, respectively.
Becomes 0.5, the size of the cell has been shown to have decreased with respect to the width W _c of a unit of a field effect transistor, the source region 6 formed on both sides of the trench T and the trench T The proportion of the total width (W _T + 2W _S ),
That has also been shown that is approximately equal to 1/2 _{(W T + 2W S) /} W C.

In this case, the ratio is 0.4 to 0.6.
Is desirable. Next, a second embodiment of the present invention will be described.
Will be explained. FIG. 6 shows the second conductivity type on the base region 6.
Vertical field effect transistor formed with a back gate portion 13 of FIG.
The star is shown. In this embodiment, as shown in FIG.
After the P base region 3 is formed, BF is
_TwoWith an acceleration voltage of 50 keV and a dose of 5 × 10¹⁴~ 1
× 10¹⁶cm ^-3Ion implantation and back gate
13 are formed.

The back gate portion 13 has a source region 6,
This is useful for preventing cell destruction by an NPN parasitic transistor composed of the base region 3 and the epitaxial layer 2. That is, the source of the above-mentioned vertical field effect transistor
When the breakdown voltage between the drains is exceeded, a current flows in the direction of arrow C, and the cell is destroyed. However, the provision of the back gate 13 reduces the _hfe of the parasitic transistor, thereby suppressing the current in the direction of the arrow. Prevents cell destruction.

The other steps are the same as in the first embodiment. Next, a third embodiment of the present invention will be described. 7 to 9, a first conductivity type epitaxial layer 2 is formed on a first conductivity type semiconductor substrate 1, a trench T is formed at least in the epitaxial layer 2, and a gate oxide film 4 is interposed in the trench T. A conductor 5 serving as a gate is buried, a first conductivity type source region 6 is formed on both sides of the trench T, a source electrode is formed on the source region 6, and a drain electrode is formed on the semiconductor substrate 1. In the method of manufacturing a vertical field effect transistor according to the present invention, the base region 3 and the source region 6 are formed in a self-aligned manner using the insulating film 12 formed on the epitaxial layer 2 and the conductor 5 as a mask material. A transistor is formed.

As shown in FIG. 9A, using the same substrate as in the first embodiment, a CVD oxide film 12 as an insulating film is
The trench T is formed by growing the film by about 0 to 5000 °, patterning the film by lithography, etching the CVD oxide film 12, removing the resist, and performing Si etching.
As shown in FIG. 9B, after forming a gate oxide film 4, a polysilicon 5 is grown, an impurity is introduced into the polysilicon, and a trench T is buried. Etch back to a depth of .6 μm.

As shown in FIG. 9 (a), using a buried polysilicon 5 and a CVD oxide film 12 as a mask material, boron B ions are used as a mask material, and rotational ion implantation is performed at an angle of about 45 °, followed by heat treatment to form a P base. After the formation of the region 3, ion implantation of arsenic As is performed as in the first embodiment, and the source region 6 is formed.
To form As shown in FIG. 9B, 1 × 10 ¹⁴
About 5 × 10 ¹⁵ cm ⁻³ of B is ion-implanted,
The heat treatment is performed for about 10 to 30 minutes, and the back gate portion 1 is formed.
Form 3 At this time, the etching may be performed after removing the oxide film serving as a mask for Si etching, or the ion implantation may be performed using BF ₂ .

The subsequent steps are the same as in the first embodiment. Also, the present invention shows an example of N type (N is the first conductivity type and P is the second conductivity type), but it is obvious that the P type is also effective. In the case of a P-type vertical field effect transistor, phosphorus P ions are ion-implanted to form the base region 3 and BF ₂ ions are ion-implanted to form the source region 6 to form the back gate portion 13. Arsenic As
Ions may be implanted.

[0036]

As described above, the present invention has the following advantages. (1) Since the ion implantation for forming the source region is performed by self-alignment between the polysilicon serving as the conductor and the mask material, there is no need to consider a shift in PR or the like. For this reason, it is possible to reduce the size of the cell, thereby reducing the on-resistance per unit area. (2) Since the ion implantation for forming the source region is performed by self-alignment of the polysilicon and the mask material, the overlap between the gate and the source region is minimized, and furthermore, it is necessary to consider a margin at the time of etching back the polysilicon. Absent.

As a result, it is possible to reduce the gate-source capacitance. (3) Since the back gate portion is provided, the destruction of the cell can be prevented.

[Brief description of the drawings]

FIG. 1A is a plan cross-sectional view of the present invention viewed from an AA ′ portion, and FIG. 1B is a cross-sectional view.

FIG. 2 is a schematic diagram showing the operation of the present invention.

3 (a) to 3 (c) are views showing the steps of the first embodiment of the present invention.

4 (a) to 4 (c) are views showing a step subsequent to FIG. 3;

FIG. 5 is a diagram comparing the present invention with a conventional technology, and FIG.
1 is a cross-sectional view of the present invention, and FIG.

FIG. 6 is a sectional view showing a second embodiment of the present invention.

FIG. 7 is a sectional view showing a third embodiment of the present invention.

FIGS. 8 (a) and (b) are views showing steps of a third embodiment of the present invention.

FIGS. 9A and 9B are views showing a step following FIG. 8;

FIGS. 10A to 10C are views showing a conventional process.

11A and 11B are views showing a step following FIG. 10;

FIG. 12 is a plan view of a conventional technique.

FIGS. 13A and 13B are process diagrams showing another example of the prior art.

14A and 14B are plan views according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 N + type semiconductor substrate 2 N- type epitaxial layer 3 P type base region 4 Gate oxide film 5 Polysilicon 6 N + source region 7 Insulating film 8 Source electrode 9 Drain electrode 10 Channel 11 Oxide film 12 CVD oxide film 13 Back gate part 14 Nitride film

Claims (8)

[Claims] 1. A first conductivity type epitaxial layer is formed on a first conductivity type semiconductor substrate, a second conductivity type base region is formed on the epitaxial layer, and a trench is formed in the at least base region. A conductor serving as a gate is buried in the trench through a gate oxide film, a first conductivity type source region is formed on both sides of the trench, a source electrode is formed on the source region, and a drain electrode is formed on the semiconductor substrate. Wherein the source region is formed in a self-aligned manner using an insulating film for forming the trench and the conductor as a mask material. A method for manufacturing a transistor. 2. A first conductivity type epitaxial layer is formed on a first conductivity type semiconductor substrate, a trench is formed in at least the epitaxial layer, and a conductor serving as a gate is buried in the trench via a gate oxide film. And forming a first conductivity type source region on both sides of the trench, forming a source electrode on the source region, and attaching a drain electrode to the semiconductor substrate. Forming the base region and the source region in a self-aligned manner using an insulating film for forming a gate and the conductor as a mask material. 3. A method for manufacturing a vertical field effect transistor, which is formed from the following steps. (1) a first step of forming a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate; (2) a second step of forming a second conductivity type base region on the epitaxial layer; A) growing an oxide film on the epitaxial layer and patterning the oxide film;
(4) a fourth step of forming a trench in the base region using the patterned oxide film as a mask material;
(5) A fifth step of forming a gate oxide film in the trench.
And (6) depositing a conductor to be a gate electrode in the trench covered with the gate oxide film;
(7) a seventh step of etching back until the upper surface of the conductor is lower than the upper surface of the base region; and (8) ion implantation of impurities using the conductor and the insulating film for forming trenches as a mask material. An eighth step of forming a region by self-alignment; (9) a ninth step of forming an interlayer insulating film on the conductor in the trench; (10) a source electrode contacting a source region; A tenth step of forming the deposited drain electrode. 4. A method for manufacturing a vertical field effect transistor, which is formed from the following steps. (1) a first step of forming a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate; and (2) a second step of growing an oxide film on the epitaxial layer and patterning the oxide film. (3) a third step of forming a trench in the base region using the patterned oxide film as a mask material, (4) a fourth step of forming a gate oxide film in the trench, and (5) the gate A fifth step of depositing a conductor to be a gate electrode in the trench covered with the oxide film; (6) a sixth step of etching back until the upper surface of the conductor is lower than the upper surface of the base region; A seventh step of ion-implanting impurities using the conductor and the oxide film as a mask material to form a base region in a self-aligned manner; and (8) ion-implanting impurities using the conductor and the oxide film as a mask material. Injected, the eighth step of forming a source region by self-alignment, a ninth step of forming an interlayer insulating film on the conductor (9) in the trench,
(10) A first electrode for forming a source electrode in contact with the source region and a drain electrode formed on the semiconductor substrate.
0 steps. 5. A back gate portion of a second conductivity type is formed on the base region.
Or the method of manufacturing a vertical field effect transistor according to 4. 6. A first conductivity type epitaxial layer is formed on a first conductivity type semiconductor substrate, a trench is formed in at least the epitaxial layer, and a conductor serving as a gate is buried in the trench via a gate oxide film. A first conductivity type source region formed on both sides of the trench, a source electrode formed on the source region, and a drain electrode attached to the semiconductor substrate; A vertical field effect transistor, wherein a ratio of a total width of the trench and source regions formed on both sides of the trench to one unit width is about 40 to 60%. 7. A first conductivity type epitaxial layer is formed on a first conductivity type semiconductor substrate, a trench is formed in at least the epitaxial layer, and a conductor serving as a gate is buried in the trench via a gate oxide film. In a vertical field effect transistor, a first conductivity type source region is formed on both sides of the trench, a source electrode is formed on the source region, and a drain electrode is attached to the semiconductor substrate. On the other hand, the width of the source region is about 80 to 12
0%, a vertical field effect transistor. 8. A first conductivity type epitaxial layer is formed on a first conductivity type semiconductor substrate, a trench is formed in at least the epitaxial layer, and a conductor serving as a gate is buried in the trench via a gate oxide film. A vertical field effect transistor in which a first conductivity type source region is formed on both sides of the trench, a source electrode is formed on the source region, and a drain electrode is attached to the semiconductor substrate; A vertical field effect transistor, wherein a back gate portion of a second conductivity type is formed.