JP2002184975A - Power mosfet and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power MOSFET having a small element area and a high avalanche breakdown strength. SOLUTION: Between the gate electrodes 9 of adjacent unit cells, a trench electrode 15 comprising a trench 16 reaching a p+ type silicon substrate 1 from an n+ type source region 5 while penetrating a p- type body region 4 and a p- type silicon layer 2, and a conductive substance 17 filling the trench 16 is formed. The trench electrode 15 is disposed directly under the end of the gate electrode contiguously thereto. According to the structure, the area can be reduced significantly as compared with a connection structure of the n+ type source region 5 and the p+ type silicon substrate 1 employing a deep diffusion layer. Furthermore, avalanche resistance is enhanced because the n+ type source region 5 is formed smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power MOSFET.
T and its manufacturing method

[0002]

2. Description of the Related Art DC-DC incorporated in electronic equipment such as personal computers and other information communication equipment.
Converters are required to have higher efficiency and higher frequency with downsizing of devices, lowering of driving voltage, and increasing of current. For this reason, the DC-DC of the synchronous rectification circuit system is more efficient than the conventional system of rectifying by the Schottky barrier diode.
Converters have received attention in recent years.

In a synchronous rectifier circuit, rectification is performed using a power MOSFET. However, in order to improve the DC-DC power conversion efficiency, the power MOSFET used in the DC-DC converter must have a low on-resistance. At the same time, a small switching loss is required.

A conventional typical power MOSFET of this kind is
T will be described with reference to FIG. FIG. 18 is a sectional view showing a structure of a unit cell portion of a conventional power MOSFET. In the power MOSFET as a whole, many unit cell portions shown in FIG. 18 are repeated in order to increase the channel width.

That is, a low-resistance p + type silicon substrate 101
A p− type silicon layer 102 having a thickness of about 5 μm is formed on the surface of the p− type silicon layer 102 by epitaxial growth. The mold connection region 103 is selectively formed by diffusion.

In the surface of the p- type silicon layer 102, a p-type body region 104 is selectively diffused with one side end thereof in contact with the p + -type connection region 103. The p + type connection region 103 and the p type body region 104
, The n + type source region 105 is selectively formed by diffusion.

On the surface of the p − type silicon layer 102, an n type drift region 106 is provided with the p type body region 1.
03 is selectively diffused and formed opposite the other side surface.
On the surface of the n-type drift region 106, an n + -type drain region 107 is selectively formed by diffusion.

On the surface of the p-type body region 104 sandwiched between the n-type drift region 106 and the n + type source region 105, a gate electrode 109 is formed via a gate insulating film 108. A drain electrode 110 is in ohmic contact with the n + type drain region 107, and extends across the surface of the n + type source region 105 and the p + type region 103.
5 and the short-circuit electrode 112 for electrically short-circuiting the p + type connection region 103 are in ohmic contact.

A source electrode 111 is in ohmic contact with the back surface of the p + silicon type substrate 101. Thus, the n + type source region 105 is connected to the source electrode 1 through the short-circuit electrode 112, the p + type connection region 103, and the p + type silicon substrate 101.
11 is electrically connected.

With this structure, the parasitic capacitance and the parasitic inductance can be reduced, and the power MOSFET can be operated at a low resistance and at a high frequency.

However, since the p + type connection region 103 is formed by diffusion so as to reach the p + type silicon substrate 101, the diffusion in the lateral direction becomes large. Power MOSF
Although depending on the rated voltage of the ET, the p + type connection region 103
Occupies almost half of the entire power MOSFET in some cases. Therefore, the area of the entire power MOSFET becomes large.

Further, the p + type connection region 103 and the gate electrode 109 are formed apart from each other in consideration of a mask shift, and the p type body region 104 located immediately below the n + type source region 105 is horizontally Long in the direction. As a result, since the resistance to holes at this portion is large, the avalanche resistance is small.

[0013]

As described above, the conventional M
In the OSFET, in order to increase the operating frequency, there is a problem that the element area is increased and the cost is increased. In addition, there is a problem that the avalanche resistance is small.

The present invention has been made in view of the above problems, and has as its object to provide a power MOSFET having a small element area and a large avalanche resistance, and a method for manufacturing the same.

[0015]

In order to achieve the above object, a power MOSFET according to a first aspect of the present invention comprises a semiconductor substrate of a first conductivity type having a low resistance and a first substrate formed on a surface of the semiconductor substrate. A conductive semiconductor layer, a trench formed in the semiconductor layer to a depth reaching the semiconductor substrate from the surface, a conductive material provided in the trench, and selectively formed on the semiconductor layer surface. And a first conductivity type body region having one side end in contact with the conductive material, and a body region selectively formed on the surface of the body region, and one side end in contact with the conductive material. A source region of the second conductivity type, a drain region of the second conductivity type selectively formed on the surface of the semiconductor layer and facing across a part of the body region, and sandwiched between the source region and the drain region; Said body territory A gate electrode formed on a surface of the semiconductor substrate via a gate insulating film, a drain electrode electrically connected to the drain region, and a source electrode electrically connected to a back surface of the semiconductor substrate; Is
It is characterized in that the side wall surface of the trench is arranged adjacent to the one side wall surface of the gate electrode so as to be flush with the one side wall surface.

According to another aspect of the present invention, there is provided a power MOSFET according to a second aspect of the present invention, wherein a low-resistance semiconductor substrate of the first conductivity type and a semiconductor substrate of the first conductivity type formed on the surface of the semiconductor substrate A layer, a trench formed in the semiconductor layer to a depth reaching the semiconductor substrate from the surface, a conductive material provided in the trench, and a semiconductor layer selectively formed on the surface of the semiconductor layer; A first conductivity type body region having a side end in contact with the conductive material, and a second conductivity type body selectively formed on the surface of the body region and having one side end in contact with the conductive material; The source area of
A second conductivity type drain region selectively formed on the surface of the semiconductor layer and opposed across a part of the body region; and a gate formed on a surface of the body region between the source region and the drain region. A gate electrode formed through an insulating film and having one side wall surface on the trench side covered with a side wall protective thin film; a drain electrode electrically connected to the drain region; A source electrode connected to the trench, wherein the side wall surface of the trench and one side wall surface of the gate electrode are arranged adjacent to each other with a thickness of the side wall protective thin film separated. According to the configuration, the trench is formed narrower than the p + type connection region formed by diffusion. Therefore, the area of the portion connecting the source region and the semiconductor substrate can be reduced, so that the area of the entire device can be reduced. Further, since the trench is disposed immediately below one end of the gate electrode and adjacent to the gate electrode, the source region is smaller and the avalanche withstand capability is improved as compared with the structure formed by the deep diffusion region.

In the power MOSFET of the first invention, preferred embodiments are as follows. (1) An impurity layer of a first conductivity type and a low resistance is disposed between the trench sidewall surface portion immediately below the source region and one end of the body region, and the body region is interposed via the impurity layer. Is brought into contact with the conductive material. (2) An impurity layer of a first conductivity type and a low resistance is disposed on a side wall surface of the trench between the source region and the semiconductor substrate, and one end of the impurity layer is in contact with the bottom surface of the source region; The other end is provided in contact with the semiconductor substrate. (3) An impurity layer of a first conductivity type and a low resistance is disposed under the body region, and the impurity layer is formed so as to overlap a bottom surface of the body region and is in contact with the conductive material. . (4) The conductive material is made of a metal. In particular, it is most preferable to use tungsten. (5) The conductive material may be a semiconductor of a first conductivity type and low resistance.

Further, in order to achieve the above object, in the method for manufacturing a power MOSFET according to the third invention, the first method is provided.
Forming a semiconductor layer of a first conductivity type on the surface of a semiconductor substrate of a conductivity type and low resistance; and a gate insulating film finally serving as a gate insulating film and a gate electrode film finally serving as a gate electrode on the surface of the semiconductor layer Sequentially, forming a layer, patterning the gate electrode film to form a gate electrode film pattern, and forming an insulating film on the surface of the gate insulating film including the gate electrode film pattern, Patterning the insulating film to form an insulating film pattern having an opening on the gate electrode film pattern,
Forming a gate electrode by etching away at least the gate electrode film in the opening using the insulating film pattern as a mask;
Forming a first conductivity type body region and a second conductivity type source region in the body region on the semiconductor layer surface by introducing a conductivity type impurity and a second conductivity type impurity; Etching the semiconductor layer portion in the opening with the mask as a mask to form a trench that reaches the semiconductor substrate through the source region and the partial region of the body region, and deposits a conductive material in the trench. Embedding, forming a second conductivity type drain region on the surface of the semiconductor layer, forming a drain electrode in contact with the drain region, and forming a source electrode on the back surface of the semiconductor substrate; It is characterized by comprising.

According to the above configuration, the connection between the source region and the semiconductor substrate is made by comparison with the case where the connection is made by the diffusion region.
Since the trench can be formed to be narrow, the area of the connection portion can be reduced, and further, the area of the entire device can be reduced.
Further, the gate electrode and the trench are formed using the same insulating film as a mask, and the trench is arranged adjacent to the side surface of the gate electrode so as to be flush with the side surface of the gate electrode. As a result, the length of the p-type body region immediately below the n + -type source region is extremely small, and the avalanche withstand capability can be improved.

The power MOSFE according to the third invention
In the method of manufacturing T, a preferred embodiment is as follows. (1) The step of forming the source region and the body region includes: an implanting step of implanting first and second conductivity type impurities into the surface of the semiconductor layer through an opening of the insulating film pattern; and And a re-diffusion step of re-diffusion. (2) A first conductivity type impurity and a second conductivity type impurity are introduced from the opening of the insulating film pattern to form a first conductivity type body region on the semiconductor layer surface and a second conductivity type impurity in the body region. The step of forming a source region includes forming an impurity layer under the body region in contact with a bottom of the body region and having a first conductivity type and lower resistance than the body region. (3) The step of forming the source region, the body region, and the impurity layer includes the step of forming the first conductivity type impurity for forming the body region and the second conductivity type for forming the source region from an opening of the insulating film pattern. Implanting an impurity into the surface of the semiconductor layer, implanting the first conductivity type impurity for forming the low-resistance impurity layer deeper than the impurity for the body and the source region; And a re-diffusion step of diffusing.

Further, in order to achieve the above object,
In the method for manufacturing a power MOSFET according to a fourth aspect, a step of forming a semiconductor layer of the first conductivity type on the surface of the semiconductor substrate of the first conductivity type and low resistance, and finally forming a gate oxide film on the surface of the semiconductor layer Forming a gate insulating film and a gate electrode film that will eventually become a gate electrode, sequentially, forming a gate electrode film pattern by patterning the gate electrode film, and forming the gate electrode film pattern. Forming an insulating film on the surface of the gate insulating film, patterning the insulating film to form an insulating film pattern having an opening on the gate electrode film pattern, and using the insulating film pattern as a mask. Etching at least the gate electrode film in the opening to form a gate electrode; and removing the first conductivity type impurity from the opening in the insulating film pattern. Forming a body region of a first conductivity type and a source region of a second conductivity type in the surface of the semiconductor layer by introducing impurities of a second conductivity type, and using the insulating film pattern as a mask. Etching the semiconductor layer portion in the opening to form a trench penetrating the source region and the partial region of the body region and reaching the semiconductor layer; and forming a first conductivity type impurity from the bottom of the trench. Implanting into the semiconductor layer, forming an impurity layer under the body region in contact with the bottom of the body region and having a first conductivity type and lower resistance than the body region; and using the insulating film pattern as a mask. Etching the semiconductor layer below the lower surface of the trench to form a trench that penetrates the impurity layer and reaches the semiconductor substrate; and burying a conductive material in the trench. Forming a drain region of the second conductivity type on the surface of the semiconductor layer, forming a drain electrode in contact with the drain region, and forming a source electrode on the back surface of the semiconductor substrate. It is characterized by comprising.

According to the above structure, the resistance to holes directly under the n + -type source region and the contact resistance between the conductive material in the trench and the p-type body region are further reduced, and the avalanche resistance is further improved. . Further, contact between the body region and the conductive material is facilitated.

The power MOSFE according to the fourth invention
In the method of manufacturing T, a preferred embodiment is as follows. (1) etching and removing at least the gate electrode film in the opening using the insulating film pattern as a mask, and etching the semiconductor layer portion in the opening using the insulating film pattern as a mask; A step of forming a sidewall protective thin film on the side wall of the gate electrode exposed in the opening, between the step of forming a trench in the semiconductor layer. According to this configuration, there is no possibility that the source and the gate are short-circuited by the conductive material, and the conductive material is easily buried in the trench.

Further, in the method for manufacturing a power MOSFET according to the third and fourth aspects, preferred embodiments are as follows. (1) The conductive substance is made of a metal. Among metals, tungsten is most preferable. (2) The conductive material may be a first conductivity type low-resistance semiconductor.

[0025]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.
Note that the entire power MOSFET is formed by repeating a large number of unit cell portions having the same configuration in order to increase the channel width. In each of the following embodiments, a single unit The cell portion will be described. Further, the first conductivity type is described as p-type, and the second conductivity type is described as n-type. (First Embodiment) FIG. 1 is a sectional view schematically showing a structure of a unit portion of an n-channel MOSFET according to a first embodiment of the present invention.

In the present embodiment, a first conductive type semiconductor layer having a thickness of about 3 μm, for example, p-type silicon is formed on the surface of a low-resistance first conductive type semiconductor substrate, for example, a p + type silicon substrate 1 by epitaxial growth. A layer 2 is formed, and a trench electrode 15 extending from the surface of the p− type silicon layer 2 to the p + type silicon substrate 1 is formed in the p− type silicon layer 2. The trench electrode 15 extends from the surface of the p− type silicon layer 2 to the p + type silicon substrate 1.
, And a conductive material 17 embedded in the trench 16 having a width of about 0.5 μm.

In this embodiment, a metal, for example, tungsten (W), a high melting point metal, is formed as the conductive material 17 by a blanket CVD method or a selective growth method. Tungsten is most preferable because it has a good filling property in the trench by the CVD method and is hardly affected by high-temperature treatment such as gettering in a later step. The conductive material is not limited to metal, and may be formed of, for example, a polycrystalline semiconductor doped with p-type impurities at a high concentration. However, when a polycrystalline semiconductor is used, it is necessary to partially form a metal electrode on the surface to short-circuit with the n + -type source region.

A first conductivity type p type body region 4 is selectively formed in the surface of the p − type silicon layer 2 with one end thereof in contact with the conductive material 17. The p
On the surface of the mold body region 4, an n + -type source region 5 of the second conductivity type is selectively formed with one end thereof in contact with the conductive material 17. Thereby, the p-type body region 4
And the n + -type source region 5 is electrically connected to the conductive material 17 in the trench 16, respectively. The p-type body region 4 and the n + -type source region 5 are electrically connected to each other. Is short-circuited.

On the surface of the p − type silicon layer 2, an n type drift region 6 of the second conductivity type is selectively formed by diffusion in contact with the other end of the p type body region 5.
On the surface of the n-type drift region 6, an n + -type drain region 7 as a drain region of the second conductivity type is selectively formed by diffusion.

On the surfaces of the n + -type source region 5 and the p-type body region 4 sandwiched between the trench 16 and the n-type drift region 6, a gate electrode 9 is provided via a gate insulating film 8. Is formed.

In the present embodiment, the gate electrode 9 is disposed adjacent to the trench 16 so that the extended surface on one side surface and the extended surface on the side surface of the trench 16 are flush with each other, and the other end surface is It extends to the surface of n-type drift region 6.

A drain electrode 10 is in ohmic contact with the n + type drain region 7, and the p +
A source electrode 11 is in ohmic contact with the back surface of the silicon type substrate 1. Thus, the n + type source region 5 is electrically connected to the source electrode 11 through the conductive material 17 and the p + type silicon substrate 1.

According to the above configuration, the trench electrode 15
Has a width of about 10 μm in the case of a conventional p + type connection region.
On the other hand, since the width can be formed as extremely narrow as about 0.5 to 1 μm, the area can be significantly reduced as compared with the conventional case. For example, it can be reduced to about 4 mm ² and about 30% smaller than about 6 mm ² .

By making the trench electrode 15 close to one side of the gate electrode 9, the n +
Since the mold source region 5 is formed smaller than before,
The portion of the p-type body region 4 immediately below the n + -type source region 5 is also reduced, and the resistance to holes flowing in the portion in the lateral direction is extremely small, so that the avalanche resistance is increased.

Next, with reference to FIG.
A method for manufacturing T will be described.

FIG. 2 is a process cross-sectional view showing a cross section of a peripheral portion of the trench electrode 9 showing a manufacturing process of the power MOSFET.

First, as shown in FIG. 2A, a p− type silicon layer 2 is epitaxially grown on the surface of a p + type silicon substrate 1, and finally a gate insulating film is formed on the surface of the p− type silicon layer 2. Is formed to a thickness of about 30 nm, and a polycrystalline silicon film 201 is successively formed to a thickness of about 0.4 μm.

Next, after a resist pattern is formed on a predetermined region of the surface of the polycrystalline silicon film 201 by lithography, the polycrystalline silicon film 201 is patterned by lithography using the resist pattern as a mask. A polycrystalline silicon film pattern 202 to be a gate electrode is formed. Next, using the polycrystalline silicon film pattern 202 as a mask, first, an n-type impurity for forming an n-type drift region, for example, phosphorus is ion-implanted to form a phosphorus-implanted layer 6 '.

Next, as shown in FIG. 2B, after a resist is applied to the surface of the silicon oxide film 200 including the polycrystalline silicon film pattern 202, an opening is formed in a region where a drain region is to be formed by lithography. Is formed. Subsequently,
Using the resist pattern 220 as a mask, an n-type impurity for forming an n-type drain region, for example, arsenic is ion-implanted to form an arsenic implanted layer 7 '. Thereafter, the resist pattern 220 is ashed by an O ₂ ashing method.

Next, as shown in FIG. 2C, an insulating film serving as a mask material for reactive ion etching (hereinafter referred to as RIE), for example, a silicon oxide film 203 is formed of the polycrystalline silicon film. About 1.0 μm on the surface of the silicon oxide film 200 including
m. Subsequently, the silicon oxide film 20 on which a trench electrode is formed by lithography
3 is etched to form an opening 204 having a width of about 0.5 μm.

Subsequently, as shown in FIG. 3D, using the silicon oxide film 203 as a mask, the polycrystalline silicon film pattern 202 is formed by RIE using Cl ₂ gas.
Is dry-etched to form a gate electrode 7.

Next, as shown in FIG. 3E, a p-type impurity for forming a p-type body region, for example, boron and an n + type source region are formed from the opening 204 by ion implantation using the silicon oxide film 203 as a mask. An n-type impurity for forming, for example, arsenic is sequentially implanted to form implanted layers 4 'and 5', respectively.

Subsequently, as shown in FIG.
By performing the annealing process at 000 ° C., the impurities in each of the implanted layers 4 ′, 5 ′, 6 ′ and 7 ′ are re-diffused, and p
A type body region 4, an n + type source region 5, an n type drift region 6, and an n + type drain region 7 are respectively formed.

Subsequently, as shown in FIG. 4G, RIE using a mixed gas of CHF ₃ and SF ₆ or a mixed gas of CF ₄ and H 2 using the silicon oxide film 203 as a mask.
The silicon oxide film 200 is dry-etched to form the gate insulating film 8, and further, by RIE using HBr or SF ₆ gas, the surface of the p − -type silicon layer 2 is transferred to the p + -type silicon substrate 1. The trench (groove) 16 which is dry etched toward the p + type silicon substrate 1 is formed with a width of about 0.5 μm. When the oxide film 200 is subjected to RIE etching,
Since the silicon oxide film 203, which is a mask material, is also etched, the silicon oxide film 203 is formed to be thicker in advance.

Next, as shown in FIG. 4H, a tungsten (W) film serving as a conductive material 17 is formed in the trench 1.
6 and deposited on the surface of the silicon oxide film 203 including the inside of the trench 16 and the silicon oxide film 203.
By etching back the excess tungsten film on the surface by CDE or the like, a trench electrode 15 in which a conductive material 17 is embedded in the trench 16 is formed. The conductive material 17 is embedded at a height equal to or lower than the bottom surface of the gate electrode 9 so as not to be electrically short-circuited with the gate electrode 9. Here, if a barrier metal such as TiN is thinly adhered before depositing the tungsten film in the trench 16, the contact property between tungsten and silicon is improved.

Finally, an interlayer insulating film is formed in the trench 16 and on the surface of the silicon oxide film 203, and a void in the trench 16 above the conductive material 17 is filled with the silicon oxide film 203. Thereafter, a contact hole is formed in the silicon oxide film 203 by using a lithography technique, the drain electrode 10 is brought into ohmic contact with the n + type drain region 7, and the p +
Source electrode 11 is formed on the back surface of mold silicon substrate 1, and the power MOSFET shown in FIG. 1 is completed.

According to this manufacturing method, the gate electrode 9
And the trench 16 is made of the same silicon oxide film 2.
Since the trench electrode 15 is formed using the mask 03 as a mask, the side surface of the trench electrode 15 is formed so as to coincide with one end surface of the gate electrode 9. As a result, the n + type source region 5
The length of the p-type body region 4 immediately below can be extremely reduced. Therefore, in the power MOSFET manufactured by this manufacturing method, the n + type source region 5
The resistance to holes flowing in the p-type body region 4 immediately below in the lateral direction is extremely small, and the avalanche resistance is increased. (Modification of Manufacturing Method According to First Embodiment) The power MOSFET according to the first embodiment is
It is also produced by another manufacturing method. FIG. 5 to FIG.
It is a process sectional view showing the other manufacturing method.

First, as shown in FIG.
As in the case of the first embodiment, the silicon oxide film 200 and the polycrystalline silicon film 201 which are finally gate insulating films are formed on the surface of the p- type silicon layer 2 on the p + type silicon substrate 1.
Are sequentially laminated. Next, the polycrystalline silicon film 201 is patterned on a predetermined region of the surface of the polycrystalline silicon film 201 by a lithography technique, so that a polycrystalline silicon film pattern 202 which will eventually become a gate electrode is formed.
Is formed. Next, using the polycrystalline silicon film pattern 202 as a mask, phosphorus as an n-type impurity is ion-implanted to form a phosphorus implanted layer 6 '.

Next, as shown in FIG. 5B, the surface of the silicon oxide film 200 including the polycrystalline silicon film pattern 202 is formed as in the case of the first embodiment.
A resist pattern 220 having an opening in a region where a drain region is to be formed is formed. Subsequently, arsenic as an n-type impurity is ion-implanted using the resist pattern 220 as a mask to form an arsenic implanted layer 7 '. You. Thereafter, the resist pattern 220 is ashed by an O ₂ ashing method.

Next, as shown in FIG.
As in the case of the first embodiment, a silicon oxide film 203 serving as a mask material for RIE is deposited on the surface of the silicon oxide film 200 including the polycrystalline silicon film pattern 202 to a thickness of about 1.0 μm by a CVD method. You. Subsequently, a predetermined portion of the silicon oxide film 203 where a trench electrode is to be formed is etched by a lithography technique to form an opening 204 having a width of about 0.7 μm.

Subsequently, as shown in FIG. 6D, the silicon oxide film 20 is formed in the same manner as in the first embodiment.
RIE using Cl ₂ gas with 3 as a mask
The polycrystalline silicon film pattern 202 is dry-etched to form the gate electrode 9.

Next, as shown in FIG. 6E, boron as a p-type impurity and arsenic as an n-type impurity are sequentially implanted from the opening 204 by ion implantation using the silicon oxide film 203 as a mask. , Injection layers 4 'and 5', respectively, are formed.

Subsequently, as shown in FIG. 6F, as in the case of the first embodiment, an annealing process is performed at about 1000 ° C., so that each of the implanted layers 4 ′, 5 ′,
The impurities of 6 ′ and 7 ′ are rediffused, and the p-type body region 4, the n + type source region 5, the n-type drift region 6 and the n + type
Mold drain regions 7 are each formed. By performing an oxidation process simultaneously with the annealing process, a sidewall protection thin film, for example, an oxide film 205 having a thickness of about 0.1 μm is formed on the sidewall of the gate electrode 9 exposed in the opening 204. By protecting the side wall of the gate electrode 9 with the side wall protective thin film 205 as described above, a short circuit between the source and the gate can be prevented even if the later described etch back of tungsten is insufficient.

The formation of the sidewall protective thin film 205 is performed by
After forming the mold body region 4 and the n + -type source region 5, an insulating film such as a silicon nitride film is deposited on the silicon oxide film 203 including the opening 204, and the insulating film is etched back by an etch-back method. The sidewall protective thin film may be formed on the sidewall of the gate electrode 9 by etching.

Subsequently, as shown in FIG. 7G, RIE using a mixed gas of CHF ₃ and SF ₆ or a mixed gas of CF ₄ and H ₂ using the silicon oxide film 203 as a mask.
As a result, the oxide film 200 is dry-etched to form the gate insulating film 8.
Dry etching is performed from the surface of the p-type silicon substrate 1 toward the p + -type silicon substrate 1 to form a trench (groove) 16 reaching the p + -type silicon substrate 1 with a width of about 0.5 μm.

Next, as shown in FIG. 7H, a tungsten (W) film serving as a conductive material 17 is formed in the trench 1.
6 and deposited on the surface of the silicon oxide film 203 including the inside of the trench 16 and the silicon oxide film 203.
By etching back the excess tungsten film on the surface by CDE or the like, a trench electrode 15 in which a conductive material 17 is embedded in the trench 16 is formed. In the conductive material 17, the side wall of the gate electrode 9 is protected by the side wall protective thin film 205, and there is no fear that the source region 5 and the gate electrode 9 are electrically short-circuited, and the height of the buried layer is not limited. Is free.

Finally, an interlayer insulating film is formed in the trench 16 and on the surface of the silicon oxide film 203, and a void in the trench 16 above the conductive material 17 is filled with the silicon oxide film 203. A contact hole is formed in the silicon oxide film 203 by using a lithography technique, a drain electrode 10 is in ohmic contact with the n + -type drain region 7, and a source electrode 11 is formed on the back surface of the p + -type silicon substrate 1. hand,
The power MOSFET is completed.

According to this manufacturing method, apart from the effect of the manufacturing method according to the first embodiment, the gate electrode 9
Is protected by the side wall protective thin film 205, the etch back of the conductive material 17 buried in the trench 16 is insufficient, so that the source and the gate are short-circuited. Therefore, there is an effect that the embedded height of the conductive material 17 is free. (Second Embodiment) Next, an n-channel MOSFET according to a second embodiment of the present invention will be described with reference to FIG.

FIG. 8 shows a MOSF according to the second embodiment.
It is sectional drawing which shows the structure of the unit part of ET typically. Here, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

This embodiment differs from the first embodiment in that the trench electrode 1 between the n + -type source region 5 and the p + -type silicon substrate 1 in the first embodiment is different from the first embodiment.
5 in that the p + type layer 20 is formed in contact with the side surface of the p. That is, a p + layer 20 having a lower resistance than the p-type body region 4 is disposed on a side wall surface of the trench 16 between the n + -type source region 5 and the p + -type silicon substrate 1. The p + type layer 20 has one end in contact with the bottom surface of the n + type source region 5 and the other end in contact with the p + type silicon substrate 1. That is, the p-type body region 4 has a structure in which the p-type body region 4 is connected to the conductive material 17 via a low-resistance p + -type layer 20.

With this configuration, the resistance of the p-type body region 5 to holes is further reduced as compared with the first embodiment. Further, the contact resistance between the conductive material 17 in the trench 16 and the p-type body region 4 is reduced by the p + -type layer 20. Therefore, the avalanche resistance is further improved.

The power MOSFET of this embodiment is manufactured as follows. That is, basically, the power MOSFET of the first embodiment shown in FIGS.
Is substantially the same as that of the method described above, and different points are as follows.

First, as shown in FIG. 4G, after the trench 16 is formed, a p-type impurity, for example, boron is implanted at a high concentration into the side surface of the trench 16 by oblique ion implantation. By activating the implanted impurities, the p + type layer 20 is formed. Thereafter, the step of FIG. 4H is performed. Third Embodiment Next, an n-channel MOSFET according to a third embodiment of the present invention will be described with reference to FIG.

FIG. 9 shows a MOSF according to the third embodiment.
It is sectional drawing which shows the structure of the unit part of ET typically. Here, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

This embodiment is different from the first embodiment in that ap + -type layer 30 is formed below the p-type body region 4 so as to be continuous with the p-type body region. That is, the p + type layer 30 having a lower resistance than the p type body region 4
Is formed so as to overlap the bottom surface of the p-type body region 4 and is in contact with the conductive material 17.

According to this configuration, similarly to the second embodiment, the resistance to the hole immediately below the n + -type source region 5 and the resistance of the conductive material 17 and the p-type body region 4 in the trench 16 are obtained. The contact resistance is further reduced, and the avalanche resistance is further improved.

Next, a method of manufacturing the power MOSFET will be described with reference to FIGS.

FIGS. 10 to 12 show power MOSFETs.
FIG. 9 is a process cross-sectional view showing a cross section of a peripheral portion of the trench electrode 9, illustrating the manufacturing process of FIG.

First, FIGS. 10A to 11D are the same as those in the first embodiment. That is, as shown in FIG.
A silicon oxide film 200 and a polycrystalline silicon film 201 which ultimately become a gate oxide film on the surface of the-type silicon layer 2;
The layers are sequentially formed. Next, the polycrystalline silicon film 2
01 is patterned by lithography to form a polycrystalline silicon film pattern 202. Thereafter, using the polycrystalline silicon film pattern 202 as a mask, phosphorus as an n-type impurity is ion-implanted to form a phosphorus implanted layer 6 '.

Next, as shown in FIG. 10B, a resist pattern 220 having an opening in a region where a drain region is to be formed is formed on the surface of the silicon oxide film 200 including the polycrystalline silicon film pattern 202. Subsequently, arsenic as an n-type impurity is ion-implanted using the resist pattern 220 as a mask to form an arsenic implanted layer 7 '.
Is formed. Thereafter, the resist pattern 220 is formed.
Is incinerated by the O ₂ ashing method.

Next, as shown in FIG.
A silicon oxide film 203 serving as a mask material is deposited on the surface of the oxide film 200 including the polycrystalline silicon film pattern 202 by a CVD method. Subsequently, a predetermined portion of the silicon oxide film 203 where a trench electrode is to be formed is etched by a lithography technique to form an opening 204.

Subsequently, as shown in FIG. 11D, the silicon oxide film 2 is formed in the same manner as in the first embodiment.
Using the mask 03 as a mask, the polycrystalline silicon film pattern 202 is dry-etched by RIE using Cl ₂ gas to form the gate electrode 9.

Next, as shown in FIG. 11E, a p-type impurity for forming a p-type body region is formed through the opening 204 by ion implantation using the silicon oxide film 203 as a mask.
For example, boron, an n-type impurity for forming an n + -type source region,
For example, arsenic and a p-type impurity for forming ap + type layer, for example, boron are sequentially implanted, and the implanted layers 4 ', 5' and 30 'are implanted.
Are each formed. Here, the injection layer 30 ′
It is formed deeper than the other injection layers 4 'and 5'.

In this embodiment, the injection layers 4 'and 5'
Are implanted at an acceleration voltage of about 60 K and about 50 KV, respectively, and the implanted layer 30 ′ is implanted at a high acceleration voltage of about 500 KV.

Subsequently, as shown in FIG. 11F, as in the case of the first embodiment, annealing is performed at about 1000.degree.
The impurities of 6 ′, 7 ′ and 30 ′ are rediffused, and the p-type body region 4, the n + type source region 5, the n-type drift region 6,
An n + type drain region 7 and a p + type layer 30 are each formed.

Subsequently, as shown in FIG. 12 (g), using the silicon oxide film 203 as a mask, CHF ₃ and SF _{6 are used.}
The silicon oxide film 200 is dry-etched by RIE using a mixed gas of the above to form a gate oxide film 8, and further, the p-type film is formed by RIE using HBr gas.
Dry etching is performed from the surface of the p-type silicon substrate 1 toward the p + -type silicon substrate 1, and penetrates the n + -type source region 5, the p-type body region 5 and a part of the p + -type layer 30, and A trench 16 reaching the silicon substrate 1 is formed. The silicon oxide film 2
Since the silicon oxide film 203 serving as a mask material is also etched when the RIE is performed on the silicon oxide film 00, the silicon oxide film 203 is formed to be thicker in advance.

Next, as shown in FIG. 12H, a tungsten (W) film serving as the conductive material 17 is deposited on the surface of the silicon oxide film 203 including the inside of the trench 16, and Other than the silicon oxide film 2
The excess tungsten film 17 on the surface 03 is etched back by CDE or the like to form a trench electrode 15 in which the conductive material 17 is embedded in the trench 16.

Finally, an interlayer insulating film is formed in the trench 16 and on the surface of the silicon oxide film 203, and a void in the trench 16 above the conductive material 17 is filled with the silicon oxide film 203. A contact hole is formed in the silicon oxide film 203 by using a lithography technique, a drain electrode 10 is in ohmic contact with the n + -type drain region 7, and a source electrode 11 is formed on the back surface of the p + -type silicon substrate 1. hand,
The power MOSFET shown in FIG. 9 is completed. (Modification of Manufacturing Method According to Third Embodiment) The power MOSFET according to the third embodiment can be manufactured by another manufacturing method. 13 to 16 are process cross-sectional views showing another manufacturing method.

FIGS. 13 to 16 show power MOSFETs.
FIG. 9 is a process cross-sectional view showing a cross section of a peripheral portion of the trench electrode 9, illustrating the manufacturing process of FIG.

First, FIG. 13A to FIG. 14F are the same as those in the third embodiment. That is, as shown in FIG.
A silicon oxide film 200 and a polycrystalline silicon film 201 are sequentially formed on the surface of the negative type silicon layer 2, and the polycrystalline silicon film 201 is patterned by lithography to form a polycrystalline silicon film pattern 202. . Thereafter, the polycrystalline silicon film pattern 20 is formed.
2 is used as a mask to form an ion implantation layer 6 'of an n-type impurity by an ion implantation method.

Next, as shown in FIG. 13B, a resist pattern 220 having an opening in a region where a drain region is to be formed is formed on the surface of the silicon oxide film 200 including the polycrystalline silicon film pattern 202. Subsequently, using the resist pattern 220 as a mask, an n-type impurity implanted layer 7 'is formed by ion implantation.
Thereafter, the resist pattern 220 is ashed by an O ₂ ashing method.

Next, as shown in FIG.
The silicon oxide film 203 serving as a mask material for the silicon oxide film 2 including the polycrystalline silicon film pattern 202;
00 is deposited on the surface by a CVD method. Subsequently, a predetermined portion of the silicon oxide film 203 where a trench electrode is to be formed is etched by a lithography technique to form an opening 204.

Subsequently, as shown in FIG. 14D, the silicon oxide film 2 is formed in the same manner as in the first embodiment.
Using the mask 03 as a mask, the polycrystalline silicon film pattern 202 is dry-etched by RIE using Cl ₂ gas to form the gate electrode 9.

Next, as shown in FIG. 14E, a p-type impurity such as boron and an n-type impurity such as arsenic are sequentially implanted from the opening 204 by ion implantation using the silicon oxide film 203 as a mask. , Injection layers 4 'and 5', respectively, are formed.

Subsequently, as shown in FIG. 14 (f), by performing an annealing process at about 1000 ° C., the impurities in each of the implanted layers 4 ′, 5 ′, 6 ′ and 7 ′ are re-diffused,
A p-type body region 4, an n + -type source region 5, an n-type drift region 6, and an n + -type drain region are respectively formed.

Subsequently, as shown in FIG. 15G, using the silicon oxide film 203 as a mask, CHF ₃ and SF _{6 are used.}
The oxide film 200 is dry-etched by RIE using a mixed gas of the above to form a gate insulating film 8. Further, the RIE using HBr gas is used to remove the surface of the p− type silicon layer 2 from the p− type silicon substrate 1. Then, a trench (groove) 16 which penetrates the n + -type source region 5 and a part of the p-type body region 5 and reaches the p − -type silicon layer 2 is formed.

Next, as shown in FIG. 15H, the trench 1 is formed using the silicon oxide film 203 as a mask.
After the p-type impurity for forming a p + type layer, for example, boron is ion-implanted into the p− type silicon layer 2 from the bottom surface of
By performing the annealing process at 000 ° C., the implanted impurities are re-diffused, and a p + -type layer 30 is formed below the p-type body region 4 in contact with the lower portion of the p-type body region 4.

Next, as shown in FIG. 15 (i), the p− type silicon layer 2 under the bottom of the trench 16 is further etched by RIE using HBr gas,
A trench (groove) 16 penetrating through the + type layer 30 and reaching the p + type silicon substrate 1 is formed.

Next, as shown in FIG. 16 (j), a tungsten (W) film serving as the conductive material 17 is deposited on the surface of the silicon oxide film 203 including the inside of the trench 16, and a portion other than the inside of the trench 16 is formed. The silicon oxide film 2
The trench electrode 15 in which the conductive material 17 is buried inside the trench 16 is formed by etching back the excess tungsten film on the surface 03 by the CDE method or the like.

Finally, an interlayer insulating film is formed in the trench 16 and on the surface of the silicon oxide film 203, and a void in the trench 16 above the conductive material 17 is filled with the silicon oxide film 203. A contact hole is formed in the silicon oxide film 203 by using a lithography technique, a drain electrode 10 is in ohmic contact with the n + -type drain region 7, and a source electrode 11 is formed on the back surface of the p + -type silicon substrate 1. hand,
The power MOSFET shown in FIG. 9 is completed. (Fourth Embodiment) Next, an n-channel MOSFET according to a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 17 shows a MOS transistor according to the fourth embodiment.
It is sectional drawing which shows the structure of the unit part of FET typically. Here, the same components as those of the third embodiment are denoted by the same reference numerals, and detailed description is omitted.

This embodiment differs from the third embodiment in that the shape of the p-type body region 4 is different. This p
The mold body region 4 is formed before the gate electrode 9.

According to this configuration, in addition to the effect similar to that of the third embodiment, the channel length is longer than that of the third embodiment, but there is an effect that punch-through is difficult.

The present invention is not limited to the above-described embodiment, but may, of course, be carried out in various modifications without departing from the gist of the invention described in the appended claims.

That is, in the above embodiment, the n-channel MO
Although the case where the present invention is applied to the SFET has been described, the present invention can also be applied to a p-channel MOSFET. In this case, the n-type and p-type may be reversed in the above embodiment.

In the above embodiment, the drift region is provided in order to increase the breakdown voltage of the element. However, if a high breakdown voltage is not required, the drift region may not be provided. In this case, the drain region may be formed so that the end thereof is located immediately below the gate electrode.

In the above embodiment, the drift region and the drain region are formed before the trench forming step, but may be formed after the trench forming step, and there is no particular limitation.

Further, the drift region and the drain region are formed by performing re-diffusion of the impurity-implanted layer in the annealing process for forming the body region and the source region. It may be formed in a processing step.

Further, the gate side wall protective thin film in the first embodiment may be applied to other embodiments.

Further, p in the fourth embodiment described above.
The mold body region structure may be applied to other embodiments.

[0101]

As described above, according to the power MOS of the present invention,
According to FET, power MOSFET with small element area
Is obtained. Also, the avalanche withstand capability can be improved.

[Brief description of the drawings]

FIG. 1 is a power MOSF according to a first embodiment of the present invention.
Sectional drawing which shows the unit cell part of ET typically.

FIG. 2 is a power MOS according to the first embodiment of the present invention.
Sectional drawing which shows the manufacturing method of FET.

FIG. 3 is a power MOS according to the first embodiment of the present invention.
Sectional drawing which shows the manufacturing method of FET.

FIG. 4 is a power MOS according to the first embodiment of the present invention.
Sectional drawing which shows the manufacturing method of FET.

FIG. 5 is a power MOS according to the first embodiment of the present invention.
Sectional drawing which shows another manufacturing method of FET.

FIG. 6 is a power MOS according to the first embodiment of the present invention.
Sectional drawing which shows another manufacturing method of FET.

FIG. 7 is a power MOS according to the first embodiment of the present invention.
Sectional drawing which shows another manufacturing method of FET.

FIG. 8 shows a power MOSF according to a second embodiment of the present invention.
Sectional drawing which shows the unit cell part of ET typically.

FIG. 9 shows a power MOSF according to a third embodiment of the present invention.
Sectional drawing which shows the unit cell part of ET typically.

FIG. 10 shows a power MO according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of SFET.

FIG. 11 shows a power MO according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of SFET.

FIG. 12 shows a power MO according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of SFET.

FIG. 13 shows a power MO according to a third embodiment of the present invention.
Sectional drawing which shows another manufacturing method of SFET.

FIG. 14 shows a power MO according to a third embodiment of the present invention.
Sectional drawing which shows another manufacturing method of SFET.

FIG. 15 shows a power MO according to a third embodiment of the present invention.
Sectional drawing which shows another manufacturing method of SFET.

FIG. 16 shows a power MO according to a third embodiment of the present invention.
Sectional drawing which shows another manufacturing method of SFET.

FIG. 17 shows a power MOS according to a fourth embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically illustrating a unit cell portion of the FET.

FIG. 18 is a sectional view schematically showing a unit cell portion of a conventional power MOSFET.

[Explanation of symbols]

1, 101... P + type silicon substrate (first conductivity type semiconductor substrate) 2, 102... P− type silicon layer (first conductivity type semiconductor layer) 4, 104... P type body region (first conductivity type body) 5, 105 ... n + type source region (source region of second conductivity type) 6, 106 ... n type drift region (drift region of second conductivity type) 7, 107 ... n + type drain region (second conductivity type) 4 ′, 5 ′, 6′7 ′, injection layer 8, 108, gate insulating film 9, 109, gate electrode 10, 110, drain electrode 11, 111, source electrode 15, trench electrode 16, trench 17, etc. Conductive substance 20, 30 ... p + type layer (impurity layer) 30 '... injection layer 103 ... p + type connection region 200 ... silicon oxide film 201 ... polycrystalline silicon film 202 ... polycrystalline silicon film pattern 203 ... oxide film 204: Opening 205: Sidewall protective thin film 220: Resist pattern

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F040 DA20 DC01 EB01 EC07 EF13 EF18 EH01 EH02 EH07 FA05 FC05 FC10 FC13 FC21

Claims (17)

[Claims] A first conductive type semiconductor substrate having a low resistance; a first conductive type semiconductor layer formed on a surface of the semiconductor substrate; and a depth reaching the semiconductor substrate from the surface of the semiconductor layer. A conductive material provided in the trench; a first conductivity type body selectively formed on the surface of the semiconductor layer and having one side end in contact with the conductive material; A source region of a second conductivity type selectively formed on the surface of the body region and having one side end in contact with the conductive material; and a source region of the second conductivity type selectively formed on the surface of the semiconductor layer; A second conductivity type drain region opposed to a part of the body region, a gate electrode formed on a surface of the body region sandwiched between the source region and the drain region via a gate insulating film, Electrically to the drain region A drain electrode connected to the semiconductor substrate, and a source electrode electrically connected to the back surface of the semiconductor substrate. A power MOSFET, which is arranged. 2. A semiconductor substrate of a first conductivity type having a low resistance, a semiconductor layer of a first conductivity type formed on a surface of the semiconductor substrate, and a depth reaching the semiconductor substrate from the surface of the semiconductor layer. A conductive material provided in the trench; a first conductivity type body selectively formed on the surface of the semiconductor layer and having one side end in contact with the conductive material; A source region of a second conductivity type selectively formed on the surface of the body region and having one side end in contact with the conductive material; and a source region of the second conductivity type selectively formed on the surface of the semiconductor layer; A drain region of the second conductivity type opposed to a part of the body region, and a gate insulating film formed on a surface of the body region sandwiched between the source region and the drain region; One side wall is side wall protected A gate electrode covered with a film, a drain electrode electrically connected to the drain region, and a source electrode electrically connected to the back surface of the semiconductor substrate, wherein the trench has a side wall surface of the trench. And a side wall surface of one end of the gate electrode is disposed adjacent to the side wall protective thin film with a separation of the film thickness.
SFET. 3. An impurity layer of a first conductivity type and a low resistance is disposed between the trench side wall surface portion immediately below the source region and one end of the body region, and the impurity layer is disposed via the impurity layer. 3. The power MOSF according to claim 1, wherein a body region is in contact with said conductive material.
ET. 4. An impurity layer having a first conductivity type and a low resistance is disposed on a side wall surface of the trench between the source region and the semiconductor substrate, and one end of the impurity layer is in contact with a bottom surface of the source region. 3. The power MOSFET according to claim 1, wherein the other end is provided in contact with the semiconductor substrate. 5. An impurity layer of a first conductivity type and a low resistance is disposed under the body region, the impurity layer is formed so as to overlap a bottom surface of the body region, and is in contact with the conductive material. The power MOSFET according to claim 1, wherein 6. The power supply according to claim 1, wherein the conductive material is made of a metal.
OSFET. 7. The power MOSFET according to claim 6, wherein the metal is tungsten. 8. The power MOSFET according to claim 1, wherein the conductive material is made of a low-resistance semiconductor of a first conductivity type. 9. A step of forming a semiconductor layer of a first conductivity type on a surface of a semiconductor substrate of a first conductivity type and a low resistance; a gate insulating film finally serving as a gate insulating film on the surface of the semiconductor layer; The gate electrode film to be the gate electrode is
Sequentially forming a stack, patterning the gate electrode film to form a gate electrode film pattern, forming an insulating film on the gate insulating film surface including the gate electrode film pattern, Patterning a film to form an insulating film pattern having an opening on the gate electrode film pattern, and etching away at least the gate electrode film in the opening using the insulating film pattern as a mask to form a gate electrode. Forming a first conductive type impurity and a second conductive type impurity through an opening of the insulating film pattern to form a first conductive type impurity and a second conductive type impurity on the surface of the semiconductor layer;
Forming a conductive type body region and a second conductive type source region in the body region; etching the semiconductor layer portion in an opening using the insulating film pattern as a mask to form the source region and the body; Forming a trench reaching the semiconductor substrate through a partial region of the region, embedding a conductive material in the trench, and forming a second conductivity type drain region on the semiconductor layer surface Forming a drain electrode in contact with the drain region; and forming a source electrode on the back surface of the semiconductor substrate. 10. The step of forming the source region and the body region includes an implantation step of implanting first and second conductivity-type impurities into the surface of the semiconductor layer from an opening of the insulating film pattern, and a step after the implantation step. 10. The method for manufacturing a power MOSFET according to claim 9, comprising a re-diffusion step of re-diffusing the impurity. 11. A first conductivity type body region and a second conductivity type impurity in the body region by introducing a first conductivity type impurity and a second conductivity type impurity from an opening of the insulating film pattern. Forming a source region of a mold, contacting a bottom of the body region below the body region,
The method for manufacturing a power MOSFET according to claim 9, further comprising a step of forming an impurity layer of a conductivity type and lower in resistance than the body region. 12. The step of forming the source region, the body region, and the impurity layer, wherein the step of forming the first conductivity type impurity for forming the body region from the opening of the insulating film pattern and the step of forming the impurity for forming the source region are performed. A two-conductivity-type impurity is implanted into the surface of the semiconductor layer, and a first impurity for forming the low-resistance impurity layer is formed.
12. The power MOSFET according to claim 11, comprising: an implantation step of implanting a conductivity-type impurity deeper than the body and source region impurities; and a re-diffusion step of re-diffusing the impurity after the implantation step. Manufacturing method. 13. A step of forming a semiconductor layer of a first conductivity type on a surface of a semiconductor substrate of a first conductivity type and a low resistance; a gate insulating film which finally becomes a gate insulating film on the surface of the semiconductor layer; The gate electrode film to be the gate electrode is
Sequentially forming a stack, patterning the gate electrode film to form a gate electrode film pattern, forming an insulating film on the gate insulating film surface including the gate electrode film pattern, Patterning a film to form an insulating film pattern having an opening on the gate electrode film pattern, and etching away at least the gate electrode film in the opening using the insulating film pattern as a mask to form a gate electrode. Forming a first conductive type impurity and a second conductive type impurity through an opening of the insulating film pattern to form a first conductive type impurity and a second conductive type impurity on the surface of the semiconductor layer;
Forming a conductive type body region and a second conductive type source region in the body region; etching the semiconductor layer portion in an opening using the insulating film pattern as a mask to form the source region and the body; Forming a trench reaching the semiconductor layer through a partial region of the region; implanting a first conductivity type impurity into the semiconductor layer from a bottom portion of the trench to form a trench of the body region below the body region; Forming an impurity layer in contact with the bottom and having a first conductivity type and lower resistance than the body region; and etching the semiconductor layer below the lower surface of the trench using the insulating film pattern as a mask, thereby forming the impurity layer. Forming a trench that penetrates to reach the semiconductor substrate; burying a conductive material in the trench; and forming a second conductivity type drain region on the semiconductor layer surface. Forming, the forming a drain electrode to contact the drain regions, the method for manufacturing power MOSFET characterized by comprising by and forming a source electrode on the rear surface of the semiconductor substrate. 14. A step of etching and removing at least the gate electrode film in the opening by using the insulating film pattern as a mask, and etching the semiconductor layer portion in the opening by using the insulating film pattern as a mask. Between the step of forming a trench in the semiconductor layer,
14. The power MOSFET according to claim 9, further comprising a step of forming a side wall protective thin film on the side wall of the gate electrode exposed in the opening.
Manufacturing method. 15. The method for manufacturing a power MOSFET according to claim 9, wherein the conductive material is made of a metal. 16. The method according to claim 15, wherein the metal is tungsten. 17. The power MOSFET according to claim 9, wherein said conductive material is made of a low-resistance semiconductor of a first conductivity type.