JP2004146465A - Silicon carbide semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which is prevented from increasing its threshold voltage protected against a punch-through phenomenon, and capable of reducing a channel resistance, and to provide a method of manufacturing the same. <P>SOLUTION: The silicon carbide semiconductor device is equipped with low-concentration well regions 103 formed on the surface layer of an epitaxial region 102, source regions 105 formed inside the low-concentration well regions 103, and a high-concentration well region 104 formed under the source region 105 as bonded to the low-concentration well regions 103. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same, and more particularly, to a silicon carbide semiconductor device for a power FET (field effect transistor) and a method for manufacturing the same.
[0002]
[Prior art]
Silicon carbide (hereinafter, SiC) has a wide band gap, and the maximum breakdown electric field is one digit larger than that of silicon (hereinafter, Si). Furthermore, the natural oxide of SiC is SiO2, and a thermal oxide film can be easily formed on the surface of SiC by the same method as that of Si. For this reason, SiC is expected to be a very excellent material when used as a high-speed / high-voltage switching element of an electric vehicle, especially a high-power uni / bipolar element.
[0003]
FIG. 5 is a cross-sectional view showing a structure of a general SiC power MOSFET described in, for example, the following documents (see Patent Documents 1 and 2). In FIG. 5, an N − -type SiC epitaxial region 502 is formed on a high-concentration N + -type SiC substrate 501. A P-type well region 503 is formed in a predetermined region in a surface portion of the epitaxial region 502, an N + type source region 504 is formed in the P-type well region 503, and an N + type source region 504 in the P-type well region 503 is formed. A contact region 505 is formed between them.
[0004]
A gate electrode 507 is arranged on the P-type well region 503 via a gate insulating film 506, and the gate electrode 507 is covered with an interlayer insulating film 508. A source electrode 509 is formed so as to be in contact with P-type well region 503 and N + -type source region 504, and a drain electrode 510 is formed on the back surface of N + -type SiC substrate 501.
[0005]
The operation of the power MOSFET is as follows. When a positive voltage is applied to the gate electrode 507 while a voltage is applied between the drain electrode 510 and the source electrode 509, the P-type well region facing the gate electrode 507 A channel of an inversion type is formed in the surface layer of 503, and current can flow from the drain electrode 510 to the source electrode 509. In addition, by removing the voltage applied to the gate electrode 507, the drain electrode 510 and the source electrode 508 are electrically insulated, and exhibit a switching function.
[0006]
In the manufacture of such a high breakdown voltage device using SiC, the impurity region is formed by an ion implantation technique because the impurity diffusion coefficient is about one digit smaller than that of Si.
[0007]
Next, an example of a method for manufacturing the above-described SiC power MOSFET using ion implantation will be described with reference to the process cross-sectional views of FIGS.
[0008]
First, in the step of FIG. 6A, an N − -type SiC epitaxial region 502 having, for example, an impurity concentration of 1E14 to 1E18 cm −3 and a thickness of 1 to 100 μm is formed on an N + -type SiC substrate 501.
[0009]
Next, in the step of FIG. 6B, sacrificial oxidation is performed on the epitaxial region 502, and after removing the sacrificial oxide film, aluminum ions 602 are formed at a high temperature of, for example, 100 to 1000 ° C. using a mask material 601. Is implanted at an acceleration voltage of 10 k to 3 MeV to form a P-type well region 503. The total dose is, for example, 1E12 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0010]
Next, in the step of FIG. 6C, phosphorus ions 605 are multi-stage implanted at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV by using two mask materials, that is, a mask material 603 and a mask material 604. Then, an N + type source region 504 is formed. The total dose is, for example, 1E14 to 1E16 / cm2. Note that nitrogen, arsenic, or the like may be used as the N-type impurity in addition to phosphorus.
[0011]
Next, in the step of FIG. 6D, aluminum ions 607 are implanted in multiple stages at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV using the mask material 606 to form a P + type contact region 505. . The total dose is, for example, 1E14 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum. In addition, the order in which the ion implantation for forming each region is performed is not limited to that shown in this example.
[0012]
Next, in the step of FIG. 6E, a heat treatment at, for example, 1000 to 1800 ° C. is performed to activate the implanted impurities.
[0013]
Finally, in the step of FIG. 6F, a gate insulating film 506 is formed by thermal oxidation at about 1200 ° C., and then a gate electrode 507 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as an interlayer insulating film 508.
[0014]
Thereafter, although not particularly shown, a contact hole is formed in the interlayer insulating film 508 on the N + type source region 504 and the P + type contact region 505 to form a source electrode 509. In addition, a metal film is deposited as a drain electrode 510 on the back surface of the substrate 501 and heat-treated at, for example, about 600 to 1400 ° C. to form an ohmic electrode, thereby completing the conventional SiC power MOSFET shown in FIG.
[0015]
[Patent Document 1]
JP-A-10-233503 (page 5, FIG. 1)
[0016]
[Patent Document 2]
JP-A-11-68097 (page 6, FIG. 1)
[0017]
[Problems to be solved by the invention]
As described above, in the conventional SiC power MOSFET in which the P-type well region 503 is formed by ion implantation using SiC having a small impurity diffusion coefficient, the well region 503 is sufficiently deeper than the N + -type source region 504. Difficult to form. Therefore, there is a problem that when a high voltage is applied to the drain electrode 510, punch-through easily occurs in the P-type well region 503.
[0018]
In order to prevent punch-through, it is necessary to sufficiently increase the impurity concentration of the P-type well region 503. However, when the impurity concentration of the P-type well region 503 is increased, the problem that the gate threshold voltage is increased occurs, and the channel mobility is decreased due to the increase in impurity scattering, and the channel resistance is increased. .
[0019]
Accordingly, the present invention has been made in view of the above, and it is an object of the present invention to provide a silicon carbide semiconductor device capable of preventing an increase in threshold voltage and preventing punch-through and achieving a reduction in channel resistance. It is to provide a manufacturing method thereof.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, means for solving the problem of the present invention include a first conductivity type drift region formed on a first conductivity type silicon carbide semiconductor substrate, and a drift region formed in a surface layer portion of the drift region. A low-concentration well region of the second conductivity type, a source region of the first conductivity type formed in the low-concentration well region, and formed immediately below the source region and joined to the low-concentration well region. A second conductive type high-concentration well region; a drain region through which current flows between the source region through a channel formed in the low-concentration well region; and a drain region formed between the source region and the drain region. And a gate electrode formed on the channel region.
[0021]
【The invention's effect】
As described above, according to the present invention, even when a high electric field is applied to the junction between the high-concentration well region and the drift region, the depletion layer does not extend in the high-concentration well region, so that punch-through can be prevented. Can be. Also, the well resistance is reduced, and the avalanche withstand capability can be increased. Further, since the channel is formed in the well region with a low concentration, impurity scattering in the channel is small, so that the gate threshold voltage can be reduced and the channel resistance can be reduced.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 is a sectional view showing a configuration of the silicon carbide semiconductor device according to the first embodiment of the present invention. In FIG. 1, in the silicon carbide semiconductor device of the first embodiment, an N − -type SiC epitaxial region (drift region) 102 is formed on a high-concentration N + -type SiC substrate 101. A P − -type low-concentration well region 103 is formed in a predetermined region in the surface portion of the epitaxial region 102. An N + type source region 105 is formed in the P− type low concentration well region 103, and a P + type high concentration well region 104 is formed immediately below the source region 105. A contact region 106 is formed between the N + type source regions 105 in the P + type high concentration well region 104.
[0024]
A gate electrode 108 is disposed on the P − -type low-concentration well region 103 via a gate insulating film 107, and the gate electrode 108 is covered with an interlayer insulating film 109. A source electrode 110 is formed so as to be in contact with the N + type source region 105, and a drain electrode 111 is formed on the back surface of the N + type SiC substrate 101.
[0025]
The operation of the semiconductor device having the above configuration will be described. The basic operation is the same as that of the conventional SiC power MOSFET shown in FIG.
[0026]
When a positive voltage is applied to the gate electrode 108 in a state where a voltage is applied between the drain electrode 111 and the source electrode 110, a surface layer of the P − -type low concentration well region 103 facing the gate electrode 108 is formed. An inverted channel is formed. As a result, a current flows from the drain electrode 111 to the source electrode 110 via the P− type low concentration well region 103 and the N + type source region 105. On the other hand, when the voltage applied to the gate electrode 108 is removed, the channel formed on the surface layer of the P − -type low concentration well region 103 disappears. As a result, the drain electrode 111 and the source electrode 110 are electrically insulated, and exhibit a switching function.
[0027]
When the drain voltage increases, the depletion layer extending from the junction interface between the P + type high concentration well region 104 and the N− type epitaxial region 102 to the epitaxial region 102 side causes the P− type low concentration well region 103 and the gate insulating film 107 to be formed. The applied electric field is reduced. Since the breakdown voltage of the element is determined by the avalanche breakdown of the PN junction between the P + type high concentration well region 104 and the N− type epitaxial region 102, the drain breakdown voltage is higher than that without the P + type high concentration well region 104. Become.
[0028]
Next, an example of a method for manufacturing the semiconductor device having the configuration shown in FIG. 1 will be described with reference to process cross-sectional views shown in FIGS.
[0029]
First, in the step of FIG. 2A, an N − -type SiC epitaxial region 102 having, for example, an impurity concentration of 1E14 to 1E18 cm −3 and a thickness of 1 to 100 μm is formed on an N + -type SiC substrate 101.
[0030]
Next, in the step of FIG. 2B, sacrificial oxidation is performed on the epitaxial region 102, and after removing the sacrificial oxide film (the sacrificial oxidation does not have to be performed), the mask material 201 is used. For example, at a high temperature of 100 to 1000 ° C., aluminum ions 202 are implanted in multiple stages at an acceleration voltage of 10 k to 3 MeV to form a P − -type low concentration well region 103. The total dose is, for example, 1E12 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0031]
Next, in the step of FIG. 2C, the phosphorus ions 205 are accelerated at a high temperature of, for example, 100 to 1000 ° C. by 10 k to 1 MeV using two mask materials formed at the same time, that is, the mask material 203 and the mask material 204. N + type source regions 105 are formed by multi-stage implantation with a voltage. The total dose is, for example, 1E14 to 1E16 / cm2. Note that nitrogen, arsenic, or the like may be used as the N-type impurity in addition to phosphorus.
[0032]
Next, in the step of FIG. 2D, for example, using a photosensitive material (photoresist) 206, only the mask material 204 is removed while the mask material 203 is left.
[0033]
At this time, the photosensitive material 206 must be formed by patterning by photolithography so as to cover the mask material 203 and not to contact the mask material 204. However, since the space between the mask material 203 and the mask material 204 is several times as large as the minimum design dimension, it is not necessary to design the photolithography in consideration of misalignment. For example, at present, the distance between the mask material 203 and the mask material 204 is determined by other process and device factors such as reduction of contact resistance and side etching when forming a contact hole. However, about 3 μm must be secured. If the thickness is 3 μm, it is sufficiently possible to form the photosensitive material 206 by normal photolithography so as to cover the mask material 203 and not to contact the mask material 204.
[0034]
Next, in the step of FIG. 2E, after removing the photosensitive material (photoresist) 206, the aluminum ions 207 are accelerated by using the mask material 203 at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 3 MeV. Multi-stage implantation is performed to form a P + type high concentration well region 104. The total dose is, for example, 1E14 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0035]
In the above process, by using the mask material 203, the P + type high concentration well region 104 is formed in self-alignment with the N + type source region 105.
[0036]
Next, in the step of FIG. 2F, aluminum ions 209 are implanted in multiple stages at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV using the mask material 208 to form the P + -type contact region 106. The total dose is, for example, 1E14 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0037]
Note that the order of ion implantation for forming each region is not limited to this example.
[0038]
Next, in the step of FIG. 2 (g), for example, heat treatment at 1000 to 1800 ° C. is performed. Activate the implanted impurities.
[0039]
Finally, in the step of FIG. 2H, the gate insulating film 107 is formed by thermal oxidation at about 1200 ° C., and subsequently, the gate electrode 108 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer insulating film 109. Thereafter, although not particularly shown, a contact hole is formed in the interlayer insulating film 109 on the N + type source region 105 and the P + type contact region 106 to form a source electrode 110. In addition, a metal film is deposited on the back surface of the substrate 101 as the drain electrode 111, and is heat-treated at, for example, about 600 to 1400 ° C. to complete the semiconductor device shown in FIG. 1 as an ohmic electrode.
[0040]
Note that the first embodiment is an embodiment corresponding to the invention described in claim 1 or 3.
[0041]
In the first embodiment, since the P + -type high-concentration well region 104 can be formed directly below the N + -type source region 105 in a self-alignment manner, the junction between the P + -type high-concentration well region 104 and the N − -type epitaxial region 102 is formed. Even when a high electric field is applied, the depletion layer does not extend in the P + type high concentration well region 104, so that punch-through can be prevented.
[0042]
In addition, the well resistance is reduced, and the retention of carriers in the P + type high concentration well region 104 is less likely to occur. This makes it possible to increase the so-called avalanche withstand capability, in which the parasitic bipolar transistor formed by the N + type source region 105, the P + type high concentration well region 104 and the N− type epitaxial region 102 becomes difficult to operate. Further, since the channel is formed in the well region 103 having a low concentration, impurity scattering in the channel is reduced, so that the gate threshold voltage can be reduced and the channel resistance can be reduced.
[0043]
The above effects correspond to the effects achieved by the technical contents described in claim 1 or 3.
[0044]
FIG. 3 is a sectional view showing a configuration of the silicon carbide semiconductor device according to the second embodiment of the present invention. In FIG. 3, the feature of the silicon carbide semiconductor device of the second embodiment is that, compared to the configuration of the above-described first embodiment, a P + type high-concentration formed immediately below N + type source region 105. The point is that the well region 301 is covered with the P − type low concentration well region 302. That is, the P + type high concentration well region 301 is
It is formed in a P − type low concentration well region 302 formed in the N − type epitaxial region 102. Other configurations are the same as those of the first embodiment shown in FIG.
[0045]
Next, the operation of the semiconductor device of the second embodiment will be described. The basic operation is the same as that of the first embodiment shown in FIG.
[0046]
When a positive voltage is applied to the gate electrode 108 in a state where a voltage is applied between the drain electrode 111 and the source electrode 110, a surface layer of the P − type low concentration well region 302 facing the gate electrode 108 is formed. An inverted channel is formed. As a result, a current flows from the drain electrode 111 to the source electrode 110 via the P− type low concentration well region 302 and the N + type source region 105. On the other hand, when the voltage applied to the gate electrode 108 is removed, the channel formed on the surface layer of the P − -type low concentration well region 302 disappears. As a result, the drain electrode 111 and the source electrode 110 are electrically insulated, and exhibit a switching function.
[0047]
Since the breakdown voltage of the device is determined by the avalanche breakdown of the PN junction between the P + type high concentration well region 301 formed through the P− type low concentration well region 302 and the N− type epitaxial region 102, the P + type The drain withstand voltage is higher than in the case where the concentration well region 301 is not provided.
[0048]
Next, an example of the method for manufacturing the semiconductor device of the second embodiment shown in FIG. 3 will be described with reference to the process sectional views of FIGS.
[0049]
First, in the step of FIG. 4A, an N − -type SiC epitaxial region 102 having, for example, an impurity concentration of 1E14 to 1E18 cm −3 and a thickness of 1 to 100 μm is formed on an N + -type SiC substrate 101.
[0050]
Next, in the step of FIG. 4B, sacrificial oxidation is performed on the epitaxial region 102, and after removing the sacrificial oxide film (the sacrificial oxidation does not have to be performed), two simultaneously formed sacrificial oxides are formed. Using the mask material, that is, the mask material 401 and the mask material 402, phosphorus ions 403 are implanted in multiple stages at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV to form the N + type source region 105. The total dose is, for example, 1E14 to 1E16 / cm2. Note that nitrogen, arsenic, or the like may be used as the N-type impurity in addition to phosphorus.
[0051]
Next, in the step of FIG. 4C, for example, using a photosensitive material (photoresist) 404, only the mask material 402 is removed while the mask material 401 is left. At this time, the photosensitive material 404 must be formed by patterning by photolithography so as to always cover the mask material 401 and not to contact the mask material 402. However, since the space between the mask material 401 and the mask material 402 is several times as large as the minimum design dimension, it is not necessary to design the photolithography in consideration of misalignment. For example, at present, the distance between the mask material 401 and the mask material 402 is determined by other process and device factors such as reduction of contact resistance and side etching when forming a contact hole. However, about 3 μm must be secured. If the thickness is 3 μm, it is sufficiently possible to form the photosensitive material 404 by normal photolithography so as to cover the mask material 401 and not to contact the mask material 402.
[0052]
Next, in the step of FIG. 4D, after removing the photosensitive material (photoresist) 404, the mask material 401 is used to apply boron ions 405 at a high temperature of, for example, 100 to 1000 ° C. with an acceleration voltage of 10 k to 3 MeV. To form a P + type high concentration well region 301. The total dose is, for example, 1E14 to 1E16 / cm2. In such a process, by using the mask material 401, the P + -type high-concentration well region 301 is formed in self-alignment with the N + -type source region 105.
[0053]
After that, impurities are diffused by the heat treatment performed in the step shown in FIG. 4F to form the P − -type low concentration well region 302. For this purpose, boron is preferable as the P-type impurity forming the P + -type high-concentration well region 301. This is because boron is easily diffused in SiC when heat-treating SiC. By using boron, the P − -type low concentration well region 302 can be easily formed by diffusion. The P − -type low-concentration well region 302 may be formed by implanting boron and aluminum together and diffusing boron during heat treatment.
[0054]
Next, in the step of FIG. 4E, using the mask material 406, aluminum ions 407 are implanted in multiple stages at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV to form the P + type contact region 106. I do. The total dose is, for example, 1E14 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0055]
Note that the order of ion implantation for forming each region is not limited to this example.
[0056]
Next, in the step of FIG. 4F, a heat treatment is performed, for example, at 1000 to 1800 ° C. to activate the implanted impurities. During the heat treatment, the impurity introduced to form the P + type high concentration well region 301 in the step shown in FIG. 4D is diffused to form the P− type low concentration well region 302. Since the N + -type source region 105 and the P + -type high-concentration well region 301 are formed in a self-aligned manner, the P − -type low-concentration well region 302 is also formed in a self-aligned manner with respect to the N + -type source region 105.
[0057]
Finally, in the step of FIG. 4G, the gate insulating film 107 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 108 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer insulating film 109. Thereafter, although not particularly shown, a contact hole is formed in the interlayer insulating film 109 on the N + type source region 105 and the P + type contact region 106 to form a source electrode 110. Further, a metal film is deposited on the back surface of the substrate 101 as the drain electrode 111, and is heat-treated at, for example, about 600 to 1400 ° C. to complete the semiconductor device of the second embodiment shown in FIG. 3 as an ohmic electrode.
[0058]
The second embodiment is an embodiment corresponding to the invention described in claim 2 or 4.
[0059]
In the semiconductor device of the second embodiment, since the P − -type low-concentration well region 302 can be formed in a self-aligned manner with respect to the N + -type source region 105, the effect obtained in the first embodiment can be reduced. In addition, it is necessary to design the mask material 201 and the mask material 203 shown in FIG. 2C for forming the P− type low concentration well region 103 and the N + type source region 105 in consideration of the alignment accuracy. Is eliminated, and the element can be miniaturized. Further, since the step of forming the mask material 201 used in the step shown in FIG. 2B and the step of performing ion implantation shown in FIG. 2B are not required, compared to the first embodiment, The manufacturing process can be simplified.
[0060]
The above effects correspond to the effects achieved by the technical contents described in claim 2 or 4.
[0061]
The polytype of silicon carbide (SiC) used in the first and second embodiments is typically 4H, but may be other polytypes such as 6H and 3C. Further, in the above embodiments, the semiconductor device has a structure in which the drain electrode 111 is formed on the back surface of the SiC substrate 101, and the source electrode 110 is disposed on the surface of the substrate 101, and a current flows vertically inside the element. However, the present invention is also applicable to a semiconductor device having a structure in which, for example, a drain electrode is arranged on the substrate surface in the same manner as a source electrode, and a current flows in a lateral direction.
[0062]
Further, in the above embodiment, for example, the configuration in which the drain region 101 is N-type and the low-concentration well region 103 is P-type has been described. However, the combination of N-type and P-type is not limited thereto. The configuration may be such that 101 is P-type and low-concentration well region 103 is N-type.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention.
2 is a process sectional view illustrating an example of the method for manufacturing the semiconductor device having the configuration illustrated in FIG.
FIG. 3 is a sectional view showing a configuration of a silicon carbide semiconductor device according to a second embodiment of the present invention.
4 is a process sectional view illustrating an example of the method for manufacturing the semiconductor device having the configuration illustrated in FIG.
FIG. 5 is a cross sectional view showing a configuration of a conventional silicon carbide semiconductor device.
6 is a process sectional view illustrating an example of the method for manufacturing the semiconductor device having the configuration illustrated in FIG.
[Explanation of symbols]
Reference Signs List 101 N + type SiC substrate 102 N− type SiC epitaxial region 103, 302 P− type low concentration well region 104, 301 P + type high concentration well region 105 N + type source region 106 P + type contact region 107 Gate insulating film 108 Gate electrode 109 interlayer Insulating film 110 Source electrode 111 Drain electrode 201, 203, 204, 208, 401, 402, 406 Mask material 202, 207, 209 Aluminum ion implantation 205 Phosphorus ion implantation 206, 404 Photoresist 405 Boron ion implantation

Claims (4)

A first conductivity type drift region formed on a first conductivity type silicon carbide semiconductor substrate;
A second-conductivity-type low-concentration well region formed in a surface portion of the drift region;
A first conductivity type source region formed in the low concentration well region;
A second-conductivity-type high-concentration well region formed immediately below the source region and joined to the low-concentration well region;
A drain region through which current flows between the source region through a channel formed in the low-concentration well region;
A silicon carbide semiconductor device, comprising: a gate electrode formed on the channel region formed between the source region and the drain region. The high-concentration well region of the second conductivity type includes:
2. The silicon carbide semiconductor device according to claim 1, wherein said silicon carbide semiconductor device is formed in said second conductivity type low concentration well region. A first step of forming a first conductivity type drift region on a first conductivity type silicon carbide semiconductor substrate;
A second step of forming a second-conductivity-type low-concentration well region in a surface portion of the drift region formed in the first step;
A third step of forming a first mask pattern and a second mask pattern on the drift region formed in the second step;
A fourth step of introducing an impurity into the low-concentration well region through the first and second mask patterns to form a first conductivity type source region in the low-concentration well region;
A fifth step of removing only the second mask pattern;
Impurities are introduced through the first mask pattern, and a high-concentration well region of the second conductivity type is formed directly below the source region and joined to the low-concentration well region in a self-aligned manner with respect to the source region. A sixth step of forming
A seventh step of forming a gate electrode on the channel region formed between the source region and the drain region. A first step of forming a first conductivity type drift region on a first conductivity type silicon carbide semiconductor substrate;
A second step of forming a first mask pattern and a second mask pattern on the drift region formed in the first step;
A third step of introducing an impurity into the drift region through the first and second mask patterns to form a first conductivity type source region in the drift region;
A fourth step of removing only the second mask pattern;
A fifth step of introducing an impurity through the first mask pattern and forming a high-concentration well region of a second conductivity type directly below the source region in a self-aligned manner with respect to the source region;
A sixth step of diffusing the impurities introduced in the fifth step around the high concentration well region by heat treatment to form a second conductivity type low concentration well region around the high concentration well region;
A seventh step of forming a gate electrode on the channel region formed between the source region and the drain region.

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