JP3997886B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide semiconductor device of a power FET (field effect transistor).
[0002]
[Prior art]
Silicon carbide (hereinafter referred to as SiC) has a wide band gap, and the maximum breakdown electric field is an order of magnitude larger than that of silicon (hereinafter referred to as Si). Further, the natural oxide of SiC is SiO2, and a thermal oxide film can be easily formed on the surface of SiC by the same method as Si. For this reason, SiC is expected to be a very excellent material when used as a high-speed / high-voltage switching element of an electric vehicle, particularly as a high-power uni / bipolar element.
[0003]
FIG. 5 is a cross-sectional view showing the structure of a general SiC power MOSFET described in, for example, the following documents (see Patent Document 1 and Patent Document 2). In FIG. 5, an N− type SiC epitaxial region 502 is formed on a high concentration N + type SiC substrate 501. A P type well region 503 is formed in a predetermined region in the surface layer portion of the epitaxial region 502, an N + type source region 504 is formed in the P type well region 503, and an N + type source in the P type well region 503 is formed. A contact region 505 is formed between the regions 504.
[0004]
A gate electrode 507 is disposed on the P-type well region 503 via a gate insulating film 506, and the gate electrode 507 is covered with an interlayer insulating film 508. A source electrode 509 is formed so as to be in contact with the P type well region 503 and the N + type source region 504, and a drain electrode 510 is formed on the back surface of the N + type SiC substrate 501.
[0005]
As an operation of this power MOSFET, when a voltage is applied between the drain electrode 510 and the source electrode 509 and a positive voltage is applied to the gate electrode 507, a P-type well region facing the gate electrode 507. An inversion channel is formed in the surface layer 503 so that current can flow from the drain electrode 510 to the source electrode 509. Further, by removing the voltage applied to the gate electrode 507, the drain electrode 510 and the source electrode 508 are electrically insulated, and exhibit a switching function.
[0006]
In the manufacture of such a high breakdown voltage device using SiC, since the impurity diffusion coefficient is about an order of magnitude smaller than that of Si, the impurity region is formed by an ion implantation technique.
[0007]
Next, an example of a method for manufacturing the SiC power MOSFET using ion implantation will be described with reference to process cross-sectional views in FIGS. 6A to 6F.
[0008]
First, in the process of FIG. 6A, an N − SiC epitaxial region 502 having, for example, an impurity concentration of 1E14 to 1E18 cm −3 and a thickness of 1 to 100 μm is formed on an N + SiC substrate 501.
[0009]
Next, in the process of FIG. 6B, sacrificial oxidation is performed on the epitaxial region 502, and after removing the sacrificial oxide film, aluminum ions 602 are used at a high temperature of, for example, 100 to 1000 ° C. using the mask material 601. Are implanted in multiple stages at an acceleration voltage of 10 k to 3 MeV to form a P-type well region 503. The total dose is, for example, 1E12 to 1E16 / cm @ 2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0010]
Next, in the process of FIG. 6C, using two mask materials, that is, the mask material 603 and the mask material 604, phosphorus ions 605 are implanted at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV. Then, an N + type source region 504 is formed. The total dose is, for example, 1E14 to 1E16 / cm2. As the N-type impurity, nitrogen, arsenic, or the like may be used in addition to phosphorus.
[0011]
Next, in the step of FIG. 6D, using a mask material 606, aluminum ions 607 are implanted at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV to form a P + -type contact region 505. To do. The total dose is, for example, 1E14 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum. Further, the order of ion implantation for forming each region is not limited to that shown in this example.
[0012]
Next, in the process of FIG. 6E, heat treatment is performed at 1000 to 1800 ° C., for example, to activate the implanted impurities.
[0013]
Finally, in the step of FIG. 6F, the gate insulating film 506 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 507 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer insulating film 508.
[0014]
Thereafter, although not particularly shown, a contact hole is formed on the N + type source region 504 and the P + type contact region 505 in the interlayer insulating film 508 to form a source electrode 509. Further, a metal film is deposited on the back surface of the substrate 501 as the drain electrode 510 and heat-treated at, for example, about 600 to 1400 ° C. to form an ohmic electrode, thereby completing the conventional SiC power MOSFET shown in FIG.
[0015]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-233503 (5th page, FIG. 1)
[0016]
[Patent Document 2]
JP-A-11-68097 (page 6, FIG. 1)
[0017]
[Problems to be solved by the invention]
As described above, in the conventional SiC power MOSFET in which the P-type well region 503 is formed by ion implantation using SiC having a small impurity diffusion coefficient, the well region 503 is sufficiently formed with respect to the N + -type source region 504. It is difficult to form deeply. Therefore, when a high voltage is applied to the drain electrode 510, there is a problem that punch-through easily occurs in the P-type well region 503.
[0018]
In order to prevent punch-through, it is necessary to sufficiently increase the impurity concentration of the P-type well region 503. However, when the impurity concentration of the P-type well region 503 is increased, there is a problem that the gate threshold voltage is increased, and channel mobility is lowered due to an increase in impurity scattering, resulting in an increase in channel resistance. .
[0019]
Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a silicon carbide semiconductor device capable of preventing an increase in threshold voltage and punch-through and achieving a reduction in channel resistance. It is to provide a manufacturing method.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, means for solving the problems of the present invention includes a first step of forming a first conductivity type drift region on a first conductivity type silicon carbide semiconductor substrate, and the first step. A second step of forming a second conductivity type low-concentration well region in a surface layer portion of the drift region formed in step 1, and a first mask pattern on the drift region formed in the first step Impurities are introduced into the low concentration well region through the first and second mask patterns, and a source of the first conductivity type is formed in the low concentration well region. A fourth step of forming a region, a fifth step of removing only the second mask pattern, and introducing an impurity deeper than the source region through the first mask pattern, and at least the low concentration Well region A sixth step of forming a second conductivity type high-concentration well region in a self-aligned manner with respect to the source region, and a channel region formed between the source region and the drift region And a seventh step of forming a gate electrode .
[0021]
【The invention's effect】
As described above, according to the present invention, even if a high electric field is applied to the junction between the high-concentration well region and the drift region, the depletion layer does not expand in the high-concentration well region, thereby preventing punch-through. Can do. Further, the well resistance is reduced, and the avalanche resistance can be increased. Further, since the channel is formed in the low concentration well region, the impurity scattering in the channel is small, the gate threshold voltage can be reduced, and the channel resistance can be reduced.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
FIG. 1 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to the first embodiment of the present invention. 1, in the silicon carbide semiconductor device of the first embodiment, an N− type SiC epitaxial region (drift region) 102 is formed on a high concentration N + type SiC substrate 101. A P− type low concentration well region 103 is formed in a predetermined region in the surface layer portion of the epitaxial region 102. An N + type source region 105 is formed in the P − type low concentration well region 103, and a P + type high concentration well region 104 is formed immediately below the source region 105. A contact region 106 is formed between the N + type source regions 105 in the P + type high concentration well region 104.
[0024]
A gate electrode 108 is disposed on the P − -type low-concentration well region 103 via a gate insulating film 107, and the gate electrode 108 is covered with an interlayer insulating film 109. A source electrode 110 is formed in contact with the N + type source region 105, and a drain electrode 111 is formed on the back surface of the N + type SiC substrate 101.
[0025]
The operation of the semiconductor device having the above configuration will be described. The basic operation is the same as that of the conventional SiC power MOSFET shown in FIG.
[0026]
When a positive voltage is applied to the gate electrode 108 in a state where a voltage is applied between the drain electrode 111 and the source electrode 110, the surface layer of the P − -type low concentration well region 103 facing the gate electrode 108 is An inverted channel is formed. As a result, a current flows from the drain electrode 111 to the source electrode 110 through the P− type low concentration well region 103 and the N + type source region 105. On the other hand, when the voltage applied to the gate electrode 108 is removed, the channel formed in the surface layer of the P − -type low concentration well region 103 disappears. As a result, the drain electrode 111 and the source electrode 110 are electrically insulated and exhibit a switching function.
[0027]
When the drain voltage increases, the depletion layer extending from the junction interface between the P + type high concentration well region 104 and the N− type epitaxial region 102 to the epitaxial region 102 side causes the P− type low concentration well region 103 and the gate insulating film 107 to grow. The electric field applied to is relaxed. Since the breakdown voltage of the element is determined by the avalanche breakdown of the PN junction between the P + type high concentration well region 104 and the N − type epitaxial region 102, the drain breakdown voltage is compared with the case where there is no P + type high concentration well region 104. Becomes higher.
[0028]
Next, an example of a method for manufacturing the semiconductor device having the configuration shown in FIG. 1 will be described with reference to process cross-sectional views shown in FIGS.
[0029]
2A, an N @-type SiC epitaxial region 102 having an impurity concentration of 1E14 to 1E18 cm @ -3 and a thickness of 1 to 100 .mu.m is formed on an N @ + type SiC substrate 101, for example.
[0030]
Next, in the step of FIG. 2B, sacrificial oxidation is performed on the epitaxial region 102, and after removing the sacrificial oxide film (it is not necessary to perform sacrificial oxidation), the mask material 201 is used. For example, aluminum ions 202 are implanted in a multistage manner at an acceleration voltage of 10 k to 3 MeV at a high temperature of 100 to 1000 ° C. to form the P − -type low concentration well region 103. The total dose is, for example, 1E12 to 1E16 / cm @ 2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0031]
Next, in the process of FIG. 2 (c), using the two mask materials formed simultaneously, that is, the mask material 203 and the mask material 204, the phosphorus ions 205 are accelerated at a high temperature of, for example, 100 to 1000 ° C. by 10 k to 1 MeV. N + type source region 105 is formed by multi-stage implantation with voltage. The total dose is, for example, 1E14 to 1E16 / cm2. As the N-type impurity, nitrogen, arsenic, or the like may be used in addition to phosphorus.
[0032]
Next, in the step of FIG. 2D, for example, using the photosensitive material (photoresist) 206, only the mask material 204 is removed while the mask material 203 is left.
[0033]
At this time, the photosensitive material 206 must be formed by patterning by photolithography so that it always covers the mask material 203 and does not contact the mask material 204. However, since the interval between the mask material 203 and the mask material 204 is secured several times the minimum design dimension, it is not necessary to design a design that allows for misalignment of photolithography. For example, at present, the distance between the mask material 203 and the mask material 204 is determined by other process and device factors such as reduction of contact resistance and side etching at the time of forming a contact hole. However, about 3 μm must be secured. If the thickness is 3 μm, the photosensitive material 206 can be sufficiently formed by ordinary photolithography so as to cover the mask material 203 and not to contact the mask material 204.
[0034]
Next, in the process of FIG. 2E, after removing the photosensitive material (photoresist) 206, the mask material 203 is used to apply aluminum ions 207 at an acceleration voltage of 10 k to 3 MeV at a high temperature of 100 to 1000 ° C., for example. Multi-stage implantation is performed to form a P + type high concentration well region 104. The total dose is, for example, 1E14 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0035]
In the above process, the P + type high concentration well region 104 is formed in a self-aligned manner with respect to the N + type source region 105 by using the mask material 203.
[0036]
Next, in the process of FIG. 2F, aluminum ions 209 are implanted at a high temperature of, for example, 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV using the mask material 208 to form the P + -type contact region 106. . The total dose is, for example, 1E14 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0037]
Note that the order of ion implantation for forming each region is not limited to that shown in this example.
[0038]
Next, in the process of FIG. 2G, heat treatment is performed at 1000 to 1800 ° C., for example. The implanted impurity is activated.
[0039]
Finally, in the process of FIG. 2H, the gate insulating film 107 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 108 is formed of, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer insulating film 109. Thereafter, although not particularly shown, a contact hole is formed in the interlayer insulating film 109 on the N + type source region 105 and the P + type contact region 106 to form a source electrode 110. Also, a metal film is deposited as the drain electrode 111 on the back surface of the substrate 101, and is heat-treated at, for example, about 600 to 1400 ° C. to complete the semiconductor device shown in FIG.
[0041]
In the first embodiment, since the P + type high concentration well region 104 can be formed in a self-aligned manner immediately below the N + type source region 105, the P + type high concentration well region 104 and the N− type epitaxial region 102 are formed. Even if a high electric field is applied to the junction, the depletion layer does not expand in the P + -type high concentration well region 104, so that punch-through can be prevented.
[0042]
In addition, the well resistance is reduced, and the retention of carriers in the P + type high concentration well region 104 is less likely to occur. As a result, the so-called avalanche resistance that the parasitic bipolar transistor formed by the N + -type source region 105, the P + -type high-concentration well region 104 and the N--type epitaxial region 102 becomes difficult to operate can be increased. Further, since the channel is formed in the low concentration well region 103, impurity scattering in the channel is reduced, the gate threshold voltage can be reduced, and the channel resistance can also be reduced.
[0044]
FIG. 3 is a cross-sectional view showing a configuration of a silicon carbide semiconductor device according to the second embodiment of the present invention. In FIG. 3, the silicon carbide semiconductor device according to the second embodiment is characterized by a P + type formed immediately below the N + type source region 105 as compared with the configuration of the first embodiment described above. The high concentration well region 301 is covered with the P− type low concentration well region 302. That is, the P + type high concentration well region 301 is
It is formed in a P− type low concentration well region 302 formed in the N− type epitaxial region 102. Other configurations are the same as those of the first embodiment shown in FIG.
[0045]
Next, the operation of the semiconductor device of the second embodiment will be described. The basic operation is the same as that of the first embodiment shown in FIG.
[0046]
When a positive voltage is applied to the gate electrode 108 in a state where a voltage is applied between the drain electrode 111 and the source electrode 110, the surface layer of the P − -type low concentration well region 302 facing the gate electrode 108 is An inverted channel is formed. As a result, a current flows from the drain electrode 111 to the source electrode 110 through the P− type low concentration well region 302 and the N + type source region 105. On the other hand, when the voltage applied to the gate electrode 108 is removed, the channel formed in the surface layer of the P − -type low concentration well region 302 disappears. As a result, the drain electrode 111 and the source electrode 110 are electrically insulated and exhibit a switching function.
[0047]
Since the breakdown voltage of the element is determined by the avalanche breakdown of the PN junction between the P + type high concentration well region 301 and the N − type epitaxial region 102 formed through the P − type low concentration well region 302, P + The drain breakdown voltage is higher than when the type high-concentration well region 301 is not provided.
[0048]
Next, an example of the manufacturing method of the semiconductor device according to the second embodiment shown in FIG. 3 will be described with reference to the process cross-sectional views of FIGS.
[0049]
First, in the process of FIG. 4A, an N @-type SiC epitaxial region 102 having an impurity concentration of 1E14 to 1E18 cm @ -3 and a thickness of 1 to 100 .mu.m is formed on an N @ + type SiC substrate 101, for example.
[0050]
Next, in the step of FIG. 4B, after the sacrificial oxidation is performed on the epitaxial region 102 and the sacrificial oxide film is removed (there is no need to perform the sacrificial oxidation), Using the mask material, that is, the mask material 401 and the mask material 402, for example, phosphorus ions 403 are implanted at a high temperature of 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV to form the N + -type source region 105. The total dose is, for example, 1E14 to 1E16 / cm2. As the N-type impurity, nitrogen, arsenic, or the like may be used in addition to phosphorus.
[0051]
Next, in the step of FIG. 4C, for example, using the photosensitive material (photoresist) 404, only the mask material 402 is removed while the mask material 401 is left. At this time, the photosensitive material 404 must be formed by patterning by photolithography so that it always covers the mask material 401 and does not contact the mask material 402. However, since the interval between the mask material 401 and the mask material 402 is secured several times the minimum design dimension, it is not necessary to design a design that allows for misalignment of photolithography. For example, at present, the distance between the mask material 401 and the mask material 402 is controlled by other process and device factors such as reduction of contact resistance and side etching at the time of forming a contact hole. However, about 3 μm must be secured. If the thickness is 3 μm, the photosensitive material 404 can be sufficiently formed by normal photolithography so as to cover the mask material 401 and not to contact the mask material 402.
[0052]
Next, in the step of FIG. 4D, after removing the photosensitive material (photoresist) 404, using the mask material 401, boron ions 405 are accelerated at a high temperature of 100 to 1000 ° C., for example, at an acceleration voltage of 10 k to 3 MeV. Then, a multi-stage implantation is performed to form a P + -type high concentration well region 301. The total dose is, for example, 1E14 to 1E16 / cm2. In such a process, by using the mask material 401, a P + type high concentration well region 301 is formed in a self-aligned manner with respect to the N + type source region 105.
[0053]
Thereafter, the P − type low concentration well region 302 is formed by diffusing the impurities by heat treatment performed in the step shown in FIG. For this purpose, boron is preferable as the P-type impurity forming the P + -type high concentration well region 301. This is because boron is easy to diffuse in SiC when SiC is heat-treated. By using boron, the P− type low concentration well region 302 can be easily formed by diffusion. The P − -type low concentration well region 302 may be formed by implanting both boron and aluminum and diffusing boron during the heat treatment.
[0054]
Next, in the process of FIG. 4E, using the mask material 406, for example, aluminum ions 407 are implanted at a high temperature of 100 to 1000 ° C. at an acceleration voltage of 10 k to 1 MeV, and the P + -type contact region 106 is formed. Form. The total dose is, for example, 1E14 to 1E16 / cm2. As the P-type impurity, boron, gallium, or the like may be used in addition to aluminum.
[0055]
Note that the order of ion implantation for forming each region is not limited to that shown in this example.
[0056]
Next, in the process of FIG. 4F, heat treatment is performed at 1000 to 1800 ° C., for example, to activate the implanted impurities. During the heat treatment, impurities introduced to form the P + type high concentration well region 301 in the step shown in FIG. 4D are diffused to form the P− type low concentration well region 302. Since the N + type source region 105 and the P + type high concentration well region 301 are formed in a self-aligned manner, the P− type low concentration well region 302 is also formed in a self-aligned manner with respect to the N + type source region 105. The
[0057]
Finally, in the step of FIG. 4G, the gate insulating film 107 is formed by thermal oxidation at about 1200 ° C., and then the gate electrode 108 is formed by, for example, polycrystalline silicon. Next, a CVD oxide film is deposited as the interlayer insulating film 109. After that, although not particularly shown, contact holes are formed in the interlayer insulating film 109 on the N + type source region 105 and the P + type contact region 106 to form the source electrode 110. Also, a metal film is deposited as the drain electrode 111 on the back surface of the substrate 101, and is heat-treated at, for example, about 600 to 1400 ° C. to form an ohmic electrode, thereby completing the semiconductor device of the second embodiment shown in FIG.
[0059]
In the semiconductor device of the second embodiment, since the P− type low concentration well region 302 can be formed in a self-aligned manner with respect to the N + type source region 105, the effect obtained in the first embodiment is obtained. In addition, the design design in consideration of the alignment accuracy of the mask material 201 and the mask material 203 shown in FIG. 2C for forming the P− type low concentration well region 103 and the N + type source region 105 is performed. Therefore, the device can be miniaturized. Further, the step of forming the mask material 201 used in the step shown in FIG. 2B and the step of performing the ion implantation shown in FIG. 2B are not necessary, and therefore, compared to the first embodiment, The manufacturing process can be simplified.
[0061]
The polytype of silicon carbide (SiC) used in the first and second embodiments is typically 4H, but other polytypes such as 6H and 3C may be used. Further, in the above-described embodiment, the drain electrode 111 is formed on the back surface of the SiC substrate 101, the source electrode 110 is disposed on the surface of the substrate 101, and the semiconductor device has a structure in which current flows vertically in the element. However, for example, the present invention can also be applied to a semiconductor device having a structure in which a drain electrode is disposed on the substrate surface in the same manner as the source electrode and a current flows laterally.
[0062]
In the above embodiment, the drain region 101 is N-type and the low-concentration well region 103 is P-type, for example. However, the combination of N-type and P-type is not limited to this. A configuration may be adopted in which 101 is P-type and low-concentration well region 103 is N-type.
[Brief description of the drawings]
FIG. 1 is a cross sectional view showing a configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention.
2 is a process cross-sectional view illustrating an example of a manufacturing method of the semiconductor device having the configuration illustrated in FIG. 1;
FIG. 3 is a cross sectional view showing a configuration of a silicon carbide semiconductor device according to a second embodiment of the present invention.
4 is a process cross-sectional view illustrating an example of a manufacturing method of the semiconductor device having the configuration illustrated in FIG. 3;
FIG. 5 is a cross sectional view showing a configuration of a conventional silicon carbide semiconductor device.
6 is a process cross-sectional view illustrating an example of a method for manufacturing the semiconductor device having the configuration shown in FIG. 5; FIG.
[Explanation of symbols]
101 N + type SiC substrate 102 N− type SiC epitaxial region 103, 302 P− type low concentration well region 104, 301 P + type high concentration well region 105 N + type source region 106 P + type contact region 107 Gate insulating film 108 Gate electrode 109 Interlayer insulating film 110 Source electrode 111 Drain electrode 201, 203, 204, 208, 401, 402, 406 Mask material 202, 207, 209 Aluminum ion implantation 205 Phosphorus ion implantation 206, 404 Photoresist 405 Boron ion implantation

Claims (2)

A first step of forming a first conductivity type drift region on a first conductivity type silicon carbide semiconductor substrate;
A second step of forming a second conductivity type low concentration well region in a surface layer portion of the drift region formed in the first step;
The first of said drift region formed in step, a third step of forming a first mask pattern and the second mask pattern,
A fourth step of introducing an impurity into the low-concentration well region through the first and second mask patterns to form a first conductivity type source region in the low-concentration well region;
A fifth step of removing only the second mask pattern;
Impurities are introduced deeper than the source region through the first mask pattern, and at least a part of the low-concentration well region is joined to form a second conductivity type high-concentration well region with respect to the source region. A sixth step of forming in a self-aligning manner;
A method for manufacturing a silicon carbide semiconductor device, comprising: a seventh step of forming a gate electrode on a channel region formed between the source region and the drift region. A first step of forming a first conductivity type drift region on a first conductivity type silicon carbide semiconductor substrate;
A second step of forming a first mask pattern and a second mask pattern on the drift region formed in the first step;
A third step of introducing an impurity into the drift region through the first and second mask patterns to form a source region of a first conductivity type in the drift region;
A fourth step of removing only the second mask pattern;
A fifth step of introducing an impurity through the first mask pattern and forming a second conductivity type high-concentration well region in a self-aligned manner with respect to the source region directly under the source region;
A sixth step of diffusing the impurities introduced in the fifth step around the high concentration well region by heat treatment to form a second conductivity type low concentration well region around the high concentration well region;
A method for manufacturing a silicon carbide semiconductor device, comprising: a seventh step of forming a gate electrode on a channel region formed between the source region and the drift region.

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