JPH09213954A - Vertical type mos transistor and static induction transistor and mos transistor having trench structure and manufacture of vertical type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce on resistance by injecting holes as minority carriers to a drift layer by forming a second conductivity type impurity diffusion region electrically connected to a gate electrode onto the surface of the drift layer between second conductivity type impurity diffusion regions. SOLUTION: Positive threshold voltage is applied to gate electrodes 7 for bringing a vertical type MOS transistor to a conductive state in the vertical type MOS transistor. That is, when positive voltage is applied to the gate electrodes 7, holes as minority carriers are injected to a drift layer 2 from a P-type impurity diffusion region 23 because the P-type impurity diffusion region 23 is connected to the gate electrodes 7. Since a section, into which holes are injected, in the drift layer 2 is operated by a bipolar mode by holes and electrons in a conductivity modulation region, into which a current is flowed by holes and electrons, a voltage drop is lowered. Accordingly, since the MOS transistor is operated in the bipolar mode, by which the current is flowed by electrons and holes, on resistance can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOS transistor, a static induction transistor, and a trench structure M transistor.
The present invention relates to a structure of an OS transistor and a method of manufacturing a vertical semiconductor device.

[0002]

2. Description of the Related Art A conventional vertical MO based on the sectional view of FIG.
An example of the S transistor will be described. As shown in the figure, a conventional vertical MOS transistor includes a high-concentration first conductivity type (N-type) drain region 1 and a low-concentration first conductivity type (N-type) formed on the drain region 1. In the semiconductor substrate 3 composed of the drift layer 2), a high-concentration second conductivity type P-type impurity region 4 is formed on the surface of the drift layer 2,
A high concentration of the first conductivity type (N type) is formed in the P type impurity region 4.
The source region 5 is formed, and the gate electrode 7 is formed on the P-type impurity region 4 between the source region 5 and the drift layer 2 via the gate oxide film 6.

In the conventional vertical MOS transistor shown in FIG. 7, when a positive voltage is applied to the gate electrode 7 to form a channel, electrons as carriers are transmitted through the channel and the drift layer 2, so that a current flows. . in this case,
Since carriers are only electrons, the on-resistance of the conventional vertical MOS transistor largely depends on the impurity concentration of the drift layer 2. That is, in order to realize low on-resistance, the impurity concentration of the drift layer 2 must be set high.

An example of a conventional static induction transistor will be described with reference to the sectional view of FIG. As shown in the figure,
The conventional static induction transistor includes a high concentration first conductivity type (N type) drain region 8 and a low concentration first conductivity type (N type) drift layer 9 formed on the drain region 8. In the semiconductor substrate 10 composed of, the second conductivity type (P-type) gate regions 11 are formed on the surface of the drift layer 9 at predetermined intervals.
Are formed, and the first conductivity type (N
(Type) source region 12 is formed.

In the conventional static induction transistor shown in FIG. 8, a positive voltage is applied to the gate region 11 to make the gate region 11
A channel is formed by reducing a potential barrier formed therebetween, and an electron flows as a carrier from the source region 12 through the channel and the drift layer, so that a current flows. In this case, since carriers are only electrons, the on-resistance of the conventional static induction transistor largely depends on the impurity concentration of the drift layer 9. That is, in order to realize low on-resistance, the impurity concentration of the drift layer 9 must be set high.

An example of a conventional MOS transistor having a trench structure will be described with reference to the sectional view of FIG. As shown in the figure, a conventional MOS transistor having a trench structure has a high-concentration first conductivity type (N-type) drain region 13
And a low-concentration first-conductivity-type (N-type) drift layer 14 formed on the drain region 13, and a low-concentration second-conductivity-type on the surface of the drift layer 14. A (P-type) P-type impurity layer 16 is formed, and a trench groove 17 reaching the drift layer 14 is formed in the P-type impurity layer 16.
Is formed, a gate electrode 19 is formed in the trench groove 17 via an oxide film 18, and a source region 20 is formed on the surface of the P-type impurity layer 16 so as to surround the trench groove 17. .

In the conventional trench-structured MOS transistor shown in FIG. 9, a positive voltage is applied to the gate electrode 19,
A channel is formed in the P-type impurity layer 16 and the source region 20 is formed.
An electric current flows because electrons, which are carriers, are transmitted from the channel through the channel and the drift region 14. in this case,
Since carriers are only electrons, conventional trench structure MO
The on-resistance of the S transistor largely depends on the impurity concentration of the drift region 14. That is, in order to realize low on-resistance, the impurity concentration of the drift region 14 must be set high.

Referring to FIG. 10, the structure of the semiconductor substrate used in the conventional semiconductor device shown in FIGS. 7 to 9 and its impurity concentration distribution will be described. In the figure, (a) is a sectional view of the semiconductor substrate, and (b) is a diagram showing an impurity concentration distribution in the depth direction of the semiconductor substrate. When manufacturing a conventional semiconductor substrate, the drift layer 22 is formed by epitaxial growth on the surface of the semiconductor layer 21 having a high impurity concentration. Therefore,
As shown in the figure, the impurity concentration of the drift layer 22 is constant.

As described above, the conventional vertical MO
The S transistor, the static induction transistor, or the MOS transistor having a trench structure is a unipolar device in which a current flows using only electrons as carriers and causes a voltage drop in the drift layer. In addition, if the drift layer is made thin to achieve low on-resistance and the concentration is high, the withstand voltage becomes low, and in order to obtain the required withstand voltage, the thickness and concentration of the drift layer according to the withstand voltage are required. It was a semiconductor device.

[0010]

The static induction transistor shown in FIG. 7, the vertical MOS transistor shown in FIG.
The resistance component of the MOS transistor having the trench structure shown in FIG. 9 is dominated by the resistance component of the drift layer. Therefore, in order to obtain a low on-resistance, in order to reduce the voltage drop in the drift layer, Although it is necessary to increase the impurity concentration, there is a problem in that a large reduction in on-resistance cannot be expected because the breakdown voltage decreases.

The present invention has been made in view of the above problems, and an object thereof is to inject a hole, which is a minority carrier, into the drift layer to reduce the on-resistance, or a vertical MOS transistor or Providing a structure of an electrostatic induction transistor or a MOS transistor having a trench structure, or reducing the on-resistance by providing a concentration gradient in the drift layer and forming a conductivity modulation region in the drift layer so that the impurity concentration becomes lower toward the surface side. It is to provide a method of manufacturing a vertical semiconductor device capable of achieving

[0012]

In order to achieve the above object, a vertical MOS transistor according to claim 1 has a low-concentration first conductivity type formed on the surface of a high-concentration first conductivity type semiconductor substrate. Type drift layer, a second conductivity type impurity diffusion region formed on the surface of the drift layer at a predetermined interval, and a first conductivity type impurity diffusion region formed in the second conductivity type impurity diffusion region.
A conductive type source region; an oxide film formed on the surface of the second conductive type impurity diffusion region between the source region and the drift layer; a gate electrode formed on the surface of the oxide film; In a vertical MOS transistor having a first conductivity type drain region, a second conductivity type impurity electrically connected to the gate electrode on a surface of the drift layer between the second conductivity type impurity diffusion regions. It is characterized in that a diffusion region is formed.

According to another aspect of the vertical MOS transistor of the present invention, a low concentration first conductivity type drift layer formed on the surface of a high concentration first conductivity type semiconductor substrate and a surface of the drift layer, A second conductivity type impurity diffusion region formed at a predetermined interval, a first conductivity type source region formed between the second conductivity type impurity diffusion regions, and the second region between the source region and the drift layer. A vertical MOS transistor comprising an oxide film formed on the surface of a conductivity type impurity diffusion region, a gate electrode formed on the surface of the oxide film, and a high-concentration first conductivity type drain region. In the drift layer between the two-conductivity-type impurity diffusion regions, a second-conductivity-type buried layer electrically connected to the gate electrode is formed.

The static induction transistor according to claim 3 is
Formed on the surface of a high-concentration first conductivity type semiconductor substrate,
A low-concentration first conductivity type drift layer, a second conductivity type gate region formed on the surface of the drift layer at a predetermined interval, and a first conductivity type source region formed between the gate regions. And a high-concentration first-conductivity-type drain region, in the drift layer between the gate regions, a second-conductivity-type buried layer electrically connected to the gate region. Is formed.

According to another aspect of the present invention, in a MOS transistor having a trench structure, a low concentration first conductivity type drift layer formed on a surface of a high concentration first conductivity type semiconductor substrate and a surface of the drift layer are formed. The formed low-concentration second conductivity type impurity diffusion layer and the oxide film formed in the trench groove reaching the drift layer from the surface of the second conductivity type impurity diffusion layer. A gate region that is in contact with the second-conductivity-type impurity diffusion layer via a first-conductivity-type source region formed on the surface of the second-conductivity-type impurity diffusion layer so as to surround the trench groove; In a MOS transistor having a trench structure including the first conductivity type drain region, a second conductivity type impurity diffusion region electrically connected to the gate region is formed immediately below the gate region. The one in which the features.

According to a fifth aspect of the present invention, in a method of manufacturing a vertical semiconductor device, a low-concentration first conductivity type drift layer formed on a surface of a high-concentration first conductivity type semiconductor substrate and a drift layer in the drift layer are provided. In a method of manufacturing a vertical semiconductor device that utilizes the conductivity modulation effect obtained by injecting minority carriers into, when epitaxially growing the drift layer on the surface of the semiconductor substrate, the impurity concentration becomes lower toward the surface side. The feature is that epitaxial growth is performed by changing the impurity concentration stepwise.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a vertical semiconductor device, wherein a low concentration first conductivity type drift layer formed on a surface of a high concentration first conductivity type semiconductor substrate and a drift layer in the drift layer. In a method of manufacturing a vertical semiconductor device that utilizes the conductivity modulation effect obtained by injecting minority carriers into the drift layer, high-energy ion implantation is performed in the drift layer so that the impurity concentration increases as the depth increases. It is a feature.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A vertical MO of the present invention based on FIG.
One embodiment of the S transistor will be described. The figure shows
It is a cell part sectional view of a vertical MOS transistor. However,
The same components as those shown in FIG. 7 are designated by the same reference numerals. The vertical MOS transistor shown in FIG.
The conventional vertical MOS transistor shown in (4) is added with a P-type impurity region for injecting minority carriers. That is, in the semiconductor substrate 3 in which the low-concentration first-conductivity-type (N-type) drift layer 2 is formed on the high-concentration first-conductivity-type (N-type) drain region 1 also serving as the ohmic contact layer,
A P-type impurity region 4 that is a second-conductivity-type impurity diffusion region is formed in the surface region of the drift layer 2, and a high-concentration first-conductivity-type (N-type) source region is formed in the P-type impurity region 4. 5 is formed, and P between the source region 5 and the drift region 2 is formed.
A gate electrode 7 is formed on the surface of the type impurity region 4 via a gate oxide film 6, and the drift layer 2 between the P type impurity regions 4 is formed.
A P-type impurity diffusion region 23, which is a second conductivity type impurity diffusion region for injecting minority carriers and is electrically connected to the gate electrode 7, is formed on the surface of the P.
The structure for connecting the type impurity diffusion region 23 and the gate electrode 7 is not shown).

In the vertical MOS transistor shown in the figure, a positive threshold voltage is applied to the gate electrode 7 to make it conductive. In the case of the conventional vertical MOS transistor, when a positive voltage larger than the threshold voltage is applied to the gate electrode 7, a channel is formed in the P-type impurity region 4 below the gate electrode 7 and electrons are emitted from the source region 5. It flows through the channel to the drain region 1. On the other hand, in the vertical MOS transistor shown in FIG. 1, when a positive voltage is applied to the gate electrode 7, since the P-type impurity diffusion region 23 is connected to the gate electrode 7, drift from the P-type impurity diffusion region 23 occurs. Holes, which are minority carriers, are injected into the layer 2. The portion of the drift layer 2 into which holes are injected serves as a conductivity modulation region in which a current flows due to holes and electrons. Since the conductivity modulation region operates in the bipolar mode of holes and electrons, the voltage drop is small. Therefore, in the case of the vertical MOS transistor shown in FIG. 1, since it operates in the bipolar mode in which a current flows due to electrons and holes, the on resistance can be reduced.

A different embodiment of the vertical MOS transistor of the present invention will be described with reference to FIG. The figure is a sectional view of a cell portion of a vertical MOS transistor. However, FIG.
The same reference numerals are given to the same configurations as those shown in FIG. The vertical MOS transistor shown in FIG. 2 is different from the vertical MOS transistor shown in FIG. 1 in that a P-type impurity diffusion region for injecting minority carriers is buried in the drift layer 2 between the P-type impurity regions 4. A P-type impurity diffusion region 24, which is a buried layer, is formed. In order to form the P-type impurity diffusion region 24, for example, a portion of the drift layer 2 is formed by epitaxial growth on the drain region 1 which also serves as an ohmic contact layer, and then P is formed through a mask formed by photolithography. A P-type impurity is selectively injected into a portion where the type impurity diffusion region 24 is formed, and the P-type impurity diffusion region 24 is formed by thermal diffusion.
Further, epitaxial growth is performed to form the drift layer 2.

Also in the case of the vertical MOS transistor shown in FIG. 2, similar to the vertical MOS transistor shown in FIG.
The P-type impurity diffusion region 24 is electrically connected to the gate electrode 7. (However, in the drawing, the P-type impurity diffusion region 24
The configuration for connecting the gate electrode 7 to the gate electrode 7 is omitted). The buried P-type impurity diffusion region 24 and the gate electrode 7 are contacted with each other by, for example, anisotropically etching the drift layer 2 up to the buried P-type impurity diffusion region 24 and connecting with the aluminum wiring. .
With the configuration as described above, the vertical M shown in FIG.
The OS transistor has the same effect as the vertical MOS transistor shown in FIG. 1 and can reduce the on-resistance.

An embodiment of the static induction transistor of the present invention will be described with reference to FIG. The figure is a sectional view of a cell portion of the static induction transistor. However, the same components as those shown in FIG. 9 are designated by the same reference numerals. The static induction transistor shown in the figure has a structure in which a P-type impurity diffusion region 25 is added as a buried layer for injecting minority carriers to the conventional static induction transistor shown in FIG. That is, the P-type impurity diffusion region 2 is formed in the drift layer 14.
The semiconductor substrate 26 in which 5 is embedded is formed by the same method as that of the static induction transistor shown in FIG.

The static induction transistor shown in the figure has a high concentration first conductivity type (N type) drain region 8 and a low concentration first conductivity type (N type) drain region 8 formed on the drain region 8. In the semiconductor substrate 10 configured with the drift layer 9, a P-type impurity diffusion region 25 for injecting minority carriers is formed in the drift layer 9 below the portion where the source region 12 is formed, and the P-type impurity diffusion region 25 is formed on the surface of the drift layer 9. , Second conductivity type (P type) at a predetermined interval
The gate region 11 is formed, and the first conductivity type (N type) source region 12 is formed between the gate regions 11.

The source region 12 is formed right above the P-type impurity diffusion region 25 buried in the drift layer 9. Further, the P-type impurity diffusion region 25 and the gate region 11 are electrically connected (however, in the figure, the structure for electrically connecting the P-type impurity diffusion region 25 and the gate region 11 is omitted). . A method of forming the buried P-type impurity diffusion region 25 and a method of connecting the buried P-type impurity diffusion region 25 and the gate region 11 are described in, for example, FIG.
The same manufacturing method as that of the vertical MOS transistor shown in FIG.

In the conventional static induction transistor shown in FIG. 8, when a positive voltage is applied to the gate region 11, a channel is formed in the drift layer 9 immediately below the source region 12, and electrons are drained from the source region 12 through the channel. Area 8
Flows to On the other hand, in the electrostatic induction transistor shown in the figure, when a positive voltage is applied to the gate region 11, the P-type impurity diffusion region 25 is connected to the gate region 11, so that the drift layer is removed from the P-type impurity diffusion region 25. Holes, which are minority carriers, are injected into 9. The portion of the drift layer 9 into which holes are injected serves as a conductivity modulation region in which current flows due to holes and electrons. Since the conductivity modulation region operates in the bipolar mode of holes and electrons, the voltage drop is small. Therefore, the static induction transistor shown in the figure operates in a bipolar mode in which a current flows due to electrons and holes, so that the on-resistance can be reduced.

Based on FIG. 4, M of the trench structure of the present invention is shown.
An embodiment of the OS transistor will be described. The figure is a sectional view of a cell portion of a MOS transistor having a trench structure. However, the same components as those shown in FIG. 9 are designated by the same reference numerals. MO of trench structure shown in the figure
The S-transistor has a structure in which a second conductivity type impurity diffusion region (P-type impurity diffusion region 26) for minority carrier injection is added to the conventional trench-structure MOS transistor shown in FIG. That is, the P-type impurity diffusion region 26 formed on the surface of the drift layer 14 is exposed at the bottom of the trench groove 17 formed for forming the gate region 19, and the P-type impurity diffusion region 26 is formed at the bottom of the trench groove 17. It is formed so that the impurity diffusion region 26 and the gate region 19 are in contact with each other. P-type impurity diffusion region 26 for minority carrier injection
The contact between the gate region 19 and the gate region 19 is, for example,
A trench groove 17 reaching the drift layer 14 from the surface of the P-type impurity layer 16 is formed by dry etching or the like through a patterned mask, and P-type impurities are injected into the bottom of the trench groove 17 to thermally diffuse the minority carriers. A P-type impurity diffusion region 26 for use is formed. Then, an oxide film 18 is formed inside the trench groove 17 by thermal oxidation or the like, and the oxide film 1 formed on the bottom of the trench groove 17 through a mask.
After etching only 8 by dry etching or the like, a gate region 19 (gate electrode) is formed.

In the MOS transistor having the trench structure shown in the figure, a positive threshold voltage is applied to the gate region 19 in order to make it conductive. In the case of the conventional trench MOS transistor shown in FIG. 9, when a positive voltage larger than the threshold voltage is applied to the gate region 19, the source region 2
A channel is formed in the P-type impurity layer 16 immediately below 0, and electrons flow from the source region 20 to the drain region 13 through the channel. On the other hand, in the MOS transistor of the trench structure shown in the figure, when a positive voltage is applied to the gate region 19, the P-type impurity diffusion region 26 is connected to the gate region 19 and therefore drifts from the P-type impurity diffusion region 26. Holes that are minority carriers are injected into the layer 14. The portion of the drift layer 14 into which holes are injected serves as a conductivity modulation region in which current flows due to holes and electrons. Since the conductivity modulation region operates in the bipolar mode of holes and electrons, the voltage drop is small. Therefore, the MOS transistor having the trench structure shown in the figure operates in a bipolar mode in which a current flows by electrons and holes, so that the on-resistance can be reduced.

An embodiment of a method of manufacturing a vertical semiconductor device according to the present invention will be described with reference to FIG. (A) is a cross-sectional view of a semiconductor substrate forming a vertical semiconductor device, and (b) is
It is a diagram which shows the impurity concentration distribution of the depth direction of a semiconductor substrate. In the figure, 27 is a high-concentration first conductivity type semiconductor layer 21,
28 is a first low-concentration first layer formed on the surface of the semiconductor layer 21.
It is a conductivity type drift layer. A semiconductor substrate 29 is composed of the semiconductor layer 21 and the drift layer 28.

The drift layer 28 shown in FIG. 5 corresponds to the semiconductor layer 2
On the surface of No. 1, a plurality of epitaxial layers having different impurity concentrations are sequentially formed by epitaxial growth. In this case, the plurality of epitaxial layers are formed by gradually changing the impurity concentration so that the impurity concentration becomes lower toward the surface of the drift layer. That is, the impurity concentration is set to be lower on the surface side of the drift layer 28. The semiconductor substrate 29 is configured in this way, and the drift layer 2 of the semiconductor substrate 29 is formed.
When a minority carrier is injected into the semiconductor layer 8, the lower the impurity concentration of the drift layer 28, the longer its diffusion length is, so that the conductivity modulation region is formed in a wide range and the ON resistance can be reduced. However, if the impurity concentration in the unnecessary portion of the drift layer 28 is lowered, the on resistance is increased. Therefore, if each vertical semiconductor device utilizing the conductivity modulation effect obtained by injecting minority carriers into the drift layer 28 shown in FIGS. 1 to 4 is formed on the semiconductor substrate 29 shown in FIG. A vertical semiconductor device having low on-resistance can be formed.

A different embodiment of the method of manufacturing the vertical semiconductor device of the present invention will be described with reference to FIG. (A) is sectional drawing of the semiconductor substrate which forms a vertical semiconductor device, (b)
FIG. 6 is a diagram showing an impurity concentration distribution in the depth direction of a semiconductor substrate. However, the same components as those shown in FIG. 5 are designated by the same reference numerals. In the figure, 27 is a high concentration first conductivity type semiconductor layer 21, 28 is a low concentration first conductivity type drift layer formed on the surface of the semiconductor layer 21. A semiconductor substrate 29 is composed of the semiconductor layer 21 and the drift layer 28. The drift layer 28 is configured so that the impurity concentration becomes higher as it gets deeper.

The method of manufacturing the semiconductor substrate 29 shown in FIG.
The drift layer 28 is epitaxially grown on the surface of the semiconductor layer 21 to form a semiconductor substrate 29.
9 by high-energy ion implantation, the first conductivity type (N
It can be formed by injecting (type) impurities into the deep portion of the drift layer 28 and annealing. As a result, the same effect as that of the method of manufacturing the vertical semiconductor device shown in FIG. 5 can be obtained.

The structure of each vertical semiconductor device and the method of manufacturing a vertical semiconductor device described above are not limited to the embodiments, and a configuration in which minority carriers are injected may be used in combination. Further, the conductivity type of each region of the vertical semiconductor device may be reversed.

[0033]

As described above, according to the vertical semiconductor device of the present invention, the drift layer of the first conductivity type is of the second conductivity type electrically connected to the gate region (gate electrode). By forming an impurity region (or a buried layer),
The conductivity modulation region can be formed in the drift layer.
In this conductivity modulation region, a current flows due to two types of carriers, electrons and holes, so that there is almost no voltage drop as compared with a drift layer in which minority carriers are not injected. As a result, the on-resistance can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a vertical MOS transistor of the present invention.

FIG. 2 is a cross-sectional view showing a different embodiment of the vertical MOS transistor of the present invention.

FIG. 3 is a sectional view showing an embodiment of a static induction transistor of the present invention.

FIG. 4 is a sectional view showing an embodiment of a trench-structured MOS transistor of the present invention.

5A and 5B are views showing an embodiment of a method for manufacturing a vertical semiconductor device according to the present invention, in which FIG. 5A is a sectional view and FIG. 5B is a diagram showing an impurity concentration distribution.

6A and 6B are views showing another embodiment of the method for manufacturing a vertical semiconductor device of the present invention, FIG. 6A is a sectional view, and FIG. 6B is a diagram showing an impurity concentration distribution.

FIG. 7 is a sectional view showing an example of a conventional vertical MOS transistor.

FIG. 8 is a sectional view showing an example of a conventional static induction transistor.

FIG. 9 is a cross-sectional view showing an example of a conventional MOS transistor having a trench structure.

10A and 10B are diagrams showing an example of a conventional method of manufacturing a vertical semiconductor device, in which FIG. 10A is a sectional view and FIG. 10B is a diagram showing an impurity concentration distribution.

[Explanation of symbols]

1 Drain Region 2, 9, 14, 28 Drift Layer 3, 10, 15 Semiconductor Substrate 4 P Type Impurity Region (Second Conduction Type Impurity Diffusion Region) 5 Source Region 6 Oxide Film 7 Gate Electrode 8 Drain Region 11, 19 Gate Region 12, 20 Source region 13 Drain region 16 P-type impurity layer (second conductivity type impurity diffusion layer) 17 Trench groove 18 Oxide film 23 P-type impurity diffusion region (impurity diffusion region) 24 P-type impurity diffusion region (buried layer) 25 P type impurity diffusion region (buried layer) 26 impurity diffusion region 27 semiconductor layer

Claims (6)

[Claims] 1. A low-concentration first-conductivity-type drift layer formed on the surface of a high-concentration first-conductivity-type semiconductor substrate, and a second drift layer formed at a predetermined interval on the surface of the drift layer. A high-concentration first-conductivity-type source region formed in the second-conductivity-type impurity diffusion region, a high-concentration first-conductivity-type source region, and the second-conductivity-type impurity diffusion region between the source region and the drift layer. In a vertical MOS transistor including an oxide film formed on the surface, a gate electrode formed on the surface of the oxide film, and a high-concentration first conductivity type drain region, the second conductivity type impurity diffusion region is provided. A second electrically connected to the gate electrode on the surface of the drift layer between
A vertical MOS transistor characterized in that a conductivity type impurity diffusion region is formed. 2. A low-concentration first-conductivity-type drift layer formed on the surface of a high-concentration first-conductivity-type semiconductor substrate, and a second drift layer formed at a predetermined interval on the surface of the drift layer. Formed on the surface of the second conductivity type impurity diffusion region between the conductivity type impurity diffusion region, the first conductivity type source region formed between the second conductivity type impurity diffusion regions, and the source region and the drift layer. In a vertical MOS transistor including a formed oxide film, a gate electrode formed on the surface of the oxide film, and a high-concentration first-conductivity-type drain region. In the drift layer,
A vertical MOS transistor, wherein a buried layer of a second conductivity type electrically connected to the gate electrode is formed. 3. A low-concentration first-conductivity-type drift layer formed on the surface of a high-concentration first-conductivity-type semiconductor substrate, and a second drift layer formed at a predetermined interval on the surface of the drift layer. A static induction transistor comprising a conductive type gate region, a first conductive type source region formed between the gate regions, and a high-concentration first conductive type drain region, wherein A static induction transistor comprising a drift layer and a buried layer of a second conductivity type electrically connected to the gate region. 4. A low-concentration first-conductivity-type drift layer formed on the surface of a high-concentration first-conductivity-type semiconductor substrate, and a low-concentration second conductivity formed on the surface of the drift layer. Type impurity diffusion layer and a trench groove reaching the drift layer from the surface of the second conductivity type impurity diffusion layer,
The second film is formed through the oxide film formed in the trench groove.
A gate region in contact with the conductivity type impurity diffusion layer, a first conductivity type source region formed on the surface of the second conductivity type impurity diffusion layer so as to surround the trench groove, and a high concentration first region
MOS with trench structure having conductivity type drain region
In a transistor, an MO of a trench structure is characterized in that an impurity diffusion region of a second conductivity type, which is electrically connected to the gate region, is formed immediately below the gate region.
S transistor. 5. A conductivity modulation effect obtained by providing a low-concentration first-conductivity-type drift layer on the surface of a high-concentration first-conductivity-type semiconductor layer, and injecting minority carriers into the drift layer. In a method of manufacturing a vertical semiconductor device utilizing the method described above, when the drift layer is epitaxially grown on the surface of the semiconductor substrate, it is possible to perform the epitaxial growth by gradually changing the impurity concentration so that the impurity concentration becomes lower toward the surface side. A method for manufacturing a vertical semiconductor device having the characteristics. 6. A conductivity modulation effect obtained by providing a low-concentration first-conductivity-type drift layer on the surface of a high-concentration first-conductivity-type semiconductor layer, and injecting minority carriers into the drift layer. A method of manufacturing a vertical semiconductor device, wherein high-energy ion implantation is performed on the drift layer such that the impurity concentration increases as the depth increases.