JPH10308512A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a structure of high withstand voltage, low ON-resistance and low gate threshold voltage and prevent breakdown of a gate oxide film in a groove bottom part, by forming a silicon carbide thin film in a groove side surface of a groove gate type power MOSFET. SOLUTION: A groove gate type power MOSFET is constituted by forming an n-type thin film semiconductor layer 8 in a side surface 7a of a groove 7 and an n<+> -type epitaxial layer 3 is formed between an n<-> -type epitaxial layer 2 and a p-type epitaxial layer 4. The p-type epitaxial layer 4, the n<+> -type epitaxial layer 3 and the n<-> -type epitaxial layer 2 constitute a pn<+> n<-> -diode and a withstand voltage of a pn<+> n<-> -diode is made lower than a withstand voltage of a surface of a gate oxide film 9 in a bottom part of the groove 7 by adjusting a concentration and a thickness of the n<+> -type epitaxial layer 3. Since a pn<+> n<-> -diode causes avalanche breakdown before a surface of the gate oxide film 9 in a bottom part of the groove 7, breakdown of the gate oxide film 9 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device, which can be used as a silicon carbide semiconductor device, for example, as an insulated gate field effect transistor, especially a vertical MOSFET for high power.

[0002]

2. Description of the Related Art Conventionally, a trench gate type power MOSFET excellent in low on-resistance and high withstand voltage has been used as a silicon carbide semiconductor device.
(JP-A-7-326755 or JP-A-8-70124) has been proposed. As shown in FIG. 19, this trench gate type power MOSFET has an n ⁺ type single crystal silicon carbide (SiC) semiconductor substrate 1, an n ⁻ type epitaxial layer (hereinafter referred to as an n ⁻ epi layer) 2 and a p type epitaxial layer ( A semiconductor substrate 100 made of hexagonal single-crystal silicon carbide is constituted by 3 (hereinafter referred to as a p-type epi layer), and its upper surface (main surface) is substantially a (0001-) carbon surface.

In a predetermined region of the surface layer of the p-type epi layer 4, n
^{A +} type source region 5 is formed, and a groove (trench) 7 is formed at a predetermined position of the n ⁺ type source region 5.
The trench 7 penetrates the n ⁺ type source region 5 and the p type epi layer 4 to reach the n ⁻ type epi layer 2, and has a side surface 7 a perpendicular to the surface of the p type epi layer 4 and the surface of the p type epi layer 4. Bottom 7b parallel to
Having.

[0004] A gate oxide film 9 is formed in the trench 7, and the gate oxide film 9 is filled with a gate electrode layer 10. On the gate electrode layer 10, an interlayer insulating film 11
Is arranged. Further, a source electrode layer 12 is formed on the surface of the n ⁺ -type source region 5 and the surface of the p-type epi layer 4 including on the interlayer insulating film 11.
2 is in contact with both the n ⁺ type source region 5 and the p type epi layer 4. Drain electrode layer 13 is formed on the surface of n ⁺ type silicon carbide semiconductor substrate 1 (the back surface of semiconductor substrate 100).

By applying a positive voltage to the gate electrode layer 10, the p-type epitaxial layer 3
The surface of the substrate serves as a channel, and a current flows between the source electrode layer 12 and the drain electrode layer 13.

[0006]

The breakdown voltage between the source and the drain in the above-mentioned trench gate type power MOSFET is as follows.
It is determined by the avalanche condition of the pn junction of the p-type epitaxial layer 3 and the n ⁻ -type epitaxial layer 2 and the condition that the entire region of the p-type epitaxial layer 3 is depleted to cause punch-through. Therefore, in order to prevent punch-through and increase the avalanche generation voltage, the impurity concentration of the p-type epitaxial layer 3 is sufficiently increased, and the n ⁺ -type source regions 5 and n
^It is necessary to sufficiently increase the thickness a of the region sandwiched between the-type epitaxial layers 2.

However, when the impurity concentration of the p-type epi layer 4 is increased, the gate threshold voltage is increased, and channel mobility is reduced due to an increase in impurity scattering, and the on-resistance is increased. Further, when the thickness a is increased, there is a problem that the channel length is increased and the on-resistance is increased.
Therefore, as shown in FIG. 20, the present applicant has applied n-type silicon carbide to the surface of n ⁺ -type source region 5, p-type epi layer 4 and n ⁻ -type epi layer 2 on side surface 7 a of trench 7. (Japanese Patent Application No. 7-229487) has proposed a semiconductor device in which the n-type thin film semiconductor layer 8 is formed by an epitaxial growth method.

In the semiconductor device shown in FIG.
The n-type thin film semiconductor layer 8 is used as a channel forming region, and a voltage is applied to the gate electrode layer 10 to apply an electric field to the gate oxide film 9 to induce a storage channel in the n-type thin film semiconductor layer 8 so that the source electrode is formed. A current is caused to flow between the layer 12 and the drain electrode layer 13. Thus, MOSF
By setting the operation mode of the ET to the accumulation mode in which the channel is induced without inverting the conductivity type of the channel formation layer, the MOSFET can be operated at a lower gate voltage than the inversion mode MOSFET in which the conductivity type is inverted and the channel is induced. Can work.

Further, since the impurity concentration of the p-type epitaxial layer 3 and the impurity concentration of the n-type thin film semiconductor layer 8 in which the channel is formed can be controlled independently, the impurity concentration of the p-type epitaxial layer 3 can be increased. n ⁺ type source region 5
And the thickness a sandwiched between the n ⁻ -type epitaxial layers 2 can be reduced, so that the channel length can be shortened, the breakdown voltage can be increased, and the on-resistance can be reduced.

Further, by lowering the impurity concentration of the n-type thin film semiconductor layer 8 in which the channel is formed, the gate threshold voltage can be lowered and the influence of impurity diffusion when carriers flow can be reduced. The mobility can be increased, the ON resistance can be reduced, and the power loss can be reduced. Therefore, according to the trench gate type power MOSFET shown in FIG. 20, a silicon carbide semiconductor device having high withstand voltage, low power loss, and low gate threshold voltage can be obtained.

However, when the trench gate type power MOSFET proposed previously shown in FIG. 20 was further studied, avalanche breakdown occurred on the surface of the gate oxide film 9 at the bottom of the trench 7, and the generated hot carriers were removed from the trench. 7 is implanted into the gate oxide film 9 at the bottom,
It has been found that there is a problem that the gate oxide film 9 is broken.

Accordingly, an object of the present invention is to prevent the gate oxide film from being broken at the bottom of the groove.

[0013]

To achieve the above object, according to the first aspect of the present invention, a pn junction between the second electrode layer (13) and the first electrode layer (12) is reversed. When a bias voltage is applied, the first conductive type high-resistance semiconductor layer (2) before the avalanche breakdown of the surface of the gate oxide film (9) at the bottom of the groove (7).
The pn junction between the first semiconductor layer (4) of the second conductivity type and the first semiconductor layer (4) is made conductive.

Therefore, the voltage between the high-resistance semiconductor layer (2) of the first conductivity type and the first semiconductor layer (4) of the second conductivity type is p.
Since the n-junction is made conductive first, it is possible to prevent the gate oxide film (9) from being broken at the bottom of the groove (7). Note that the conductive state means a state of an avalanche breakdown state or a punch-through state, as described later.

[0015] In the invention according to claim 2,
A first conductive type high-resistance semiconductor layer (2) and a second conductive type first resistive semiconductor layer (2);
And a second low-resistance semiconductor layer (3) of the first conductivity type interposed between the semiconductor layer (4). By interposing the second low-resistance semiconductor layer (3) in this manner, the high-resistance semiconductor layer (2) and the second high-resistance semiconductor layer (2) are formed before the surface of the gate oxide film (9) at the bottom of the groove (7) undergoes avalanche breakdown. 2 Low resistance semiconductor layer (3)
Can be conducted first.

In this case, a pn junction between the second electrode layer (13) and the first electrode layer (12) is used as the second low-resistance semiconductor layer (3). When a reverse bias voltage is applied to the second low-resistance semiconductor layer (3) and the first semiconductor layer (3) before the surface of the gate oxide film (9) at the bottom of the groove (7) undergoes avalanche breakdown. The film thickness and the impurity concentration can be set so that the avalanche breakdown occurs in the pn junction between 4). That is, by interposing the second low-resistance semiconductor layer (3), the reverse breakdown voltage of the pn junction by the high-resistance semiconductor layer (2) and the second low-resistance semiconductor layer (3) is reduced, and the pn junction is formed first. Avalanche breakdown is possible.

Further, the pn junction between the high-resistance semiconductor layer (2) and the semiconductor layer (4) is brought into a conductive state. The thickness of the depletion layer extending from the gate oxide film (9) toward the low-resistance semiconductor layer (1) is set so as not to reach the low-resistance semiconductor layer (1). Also in the present invention, the p between the high resistance semiconductor layer (2) and the semiconductor layer (4) is
Since the n-junction is made conductive first, it is possible to prevent the gate oxide film (9) from being broken at the bottom of the groove (7).

In this case, the high-resistance semiconductor layer (2) may be provided with a critical electric field strength at which a pn junction formed by the high-resistance semiconductor layer (2) and the semiconductor layer (4) avalanche breaks down. If the depletion layer extending from the gate oxide film (9) toward the low-resistance semiconductor layer (1) is set so as not to reach the low-resistance semiconductor layer (1), the high-resistance semiconductor layer can be formed. (2) and semiconductor layer (4)
Avalanche breakdown first.

Further, as in the invention according to claims 6 to 8, a buried semiconductor layer (14) separated from the groove (7) and in contact with the semiconductor layer (4) is provided in the high resistance semiconductor layer (2). If formed, the electric field strength at the corner formed by the buried semiconductor layer (14) and the high-resistance semiconductor layer (2) is increased to cause avalanche breakdown, and the groove (7) is formed.
Destruction of the gate oxide film (9) at the bottom can be prevented.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. (First Embodiment) FIG. 1 shows an n-channel type trench gate type power MOSFET (vertical power MOSFET) according to this embodiment.

Hexagonal silicon carbide is used for n ⁺ type silicon carbide semiconductor substrate 1 as the first low-resistance semiconductor layer.
On this n ⁺ type silicon carbide semiconductor substrate 1, n ⁻ type silicon carbide semiconductor layer (n ⁻ type epi layer) 2 as a high resistance semiconductor layer
And an n ⁺ -type silicon carbide semiconductor layer (n ⁺ -type epi layer) 3 as a second low-resistance semiconductor layer and a p-type silicon carbide semiconductor layer (p-type epi layer) 4 as a first semiconductor layer are sequentially stacked Have been. Thus, semiconductor substrate 100 made of single-crystal silicon carbide is constituted by n ⁺ -type silicon carbide semiconductor substrate 1, n ⁻ -type epi layer 2, n ⁺ -type epi layer 3 and p-type epi layer 4,
The upper surface (main surface) is a substantially (0001-) carbon surface.

An n ⁺ type source region 5 as a semiconductor region is formed in a predetermined region in a surface layer portion in the p type epi layer 4. Further, n in the surface layer portion in the p-type epi layer 4
^A low-resistance p-type silicon carbide region 6 is formed in a predetermined region on the outer peripheral side of ⁺ type source region 5. The groove 7 in a predetermined region of the n ⁺ -type source region 5 is formed, the groove 7, n ⁺
It penetrates through the source region 5, the p-type epi layer 4 and the n ⁺ -type epi layer 3 to reach the n ⁻ -type epi layer 2. The groove 7 is a semiconductor substrate 10
0 and a bottom surface 7b parallel to the surface of the semiconductor substrate 100.

N on the side surface 7a of the groove 7⁺Type source area
5, p-type epi layer 4, n⁺Type epi layer 3 and n^-Type epi layer
2 has a thin film semiconductor layer of n-type silicon carbide (second
(Semiconductor layer) 8 is substantially in the [11-00] direction or substantially [1
12-0]. n-type thin film semiconductor layer 8
Is a thin film with a thickness of about 1000-5000mm
Become. The crystal type of the n-type thin film semiconductor layer 8 is p-type
The same as the crystal type of the layer 4, for example, 6H-SiC.
ing. In addition, 4H-SiC, 3C-
It may be SiC. In addition, the n-type thin film semiconductor layer 8
The pure substance concentration is n ⁺Type silicon carbide semiconductor substrate 1, n⁺Type epi
Layer 3 and n⁺Lower than the impurity concentration of the
ing.

Further, a gate oxide film 9 is formed on the surface of the n-type thin film semiconductor layer 8 in the groove 7 and on the bottom surface 7b of the groove 7. The inside of the gate oxide film 9 in the trench 7 is filled with a gate electrode layer 10. Gate electrode layer 10 is covered with interlayer insulating film 11. A source electrode layer 12 as a first electrode layer is formed on the surface of n ⁺ type source region 5 and the surface of low-resistance p-type silicon carbide region 6. n
On the surface of ⁺ type silicon carbide semiconductor substrate 1 (the back surface of semiconductor substrate 100), a drain electrode layer 13 as a second electrode layer is provided.
Are formed.

The operation of the trench gate type power MOSFET is as follows. A positive electrode is applied to the gate electrode layer 10 to induce an accumulation type channel in the n-type thin film semiconductor layer 8 so that the source electrode layer 12 and the drain electrode layer 13 and the carrier flows. That is, the n-type thin film semiconductor layer 8 becomes a channel formation region. As described above, by setting the accumulation mode in which the channel is induced as the MOSFET operation mode, the MOSFET is operated at a lower gate voltage than the MOSFET in the inversion mode in which the conductivity type is inverted and the channel is induced.
Can be operated, the channel mobility can be increased, and the gate threshold voltage can be reduced with low power loss. The source / drain current control when no gate voltage is applied is performed by expanding a depletion layer of a pn junction formed by the p-type epi layer 4 (body layer) and the n-type thin film semiconductor layer 8 (channel forming layer). Normally off characteristic is n
This can be achieved by completely depleting the type thin film semiconductor layer 8.

The p-type epi layer 4 (body layer) and n ⁺
Since the type epi layer 3 forms a pn junction, the breakdown voltage of the element is p
Can be designed to be determined by the avalanche breakdown of the pn junction between the n-type epi layer 4 and the n ⁺ -type epi layer 3.
The breakdown strength can be increased. Further, by independently controlling the impurity concentration of the p-type epi layer 4 and the impurity concentration of the n ⁺ -type epi layer 3 and the n-type thin film semiconductor layer 8, a MOSFET having a high breakdown voltage, low power loss, and a low gate threshold voltage can be obtained. Become. In particular, by lowering the impurity concentration of the n-type thin film semiconductor layer 8 forming the channel, the influence of impurity scattering when carriers flow is reduced, and the channel mobility can be increased.

The breakdown voltage between the source and the drain is mainly controlled by the impurity concentration and the thickness of the n ⁻ -type epi layer 2, the n ⁺ -type epi layer 3 and the p-type epi layer 4. By increasing the impurity concentration, the distance L between the high-resistance semiconductor layer and the semiconductor region can be reduced, and the channel length can be reduced while maintaining high withstand voltage. for that reason,
The channel resistance can be drastically reduced, and the on-resistance between the source and the drain can be reduced.

Also, n⁺Type epi layer 3 and p type epi layer 4 and n
^-By being interposed between the mold epi layers 2,
At the surface of the gate oxide film 9 (hereinafter simply referred to as the bottom of the groove).
Of gate oxide film 9 due to avalanche breakdown of
Destruction can be prevented. This is described with reference to FIG.
explain. In FIG. 2, a P-type epi layer 4 having a cross section AA
n⁺Type epi layer 3, n^-Pn⁺n^-Die
An ode (body diode) is configured. This p
n ⁺n^-In a body diode, a p-type epi layer (bore)
N under layer 4)⁺Since the type epi layer 3 exists,
Reverse voltage between drain and source (between drain and source
Voltage that reverse biases the pn junction to be applied
At the time, from the p-type epi layer 4 to n⁺Type epi layer 3, n^-Type epi layer 2
The extension of the depletion layer extending toward is suppressed. The result
As a result, the electric field concentration by the depletion layer
Because it is larger than the field concentration, pn⁺n^-Diode
The withstand voltage becomes lower. This withstand voltage is n⁺Concentration of the epitaxial layer 3
Higher or n⁺Increase the thickness of the mold epilayer 3
And lower.

On the other hand, the bottom of the groove in the BB section is separated from the n ⁺ -type epi layer 3 by the n-type thin film semiconductor layer 8. For this reason, even if the n ⁺ -type epi layer 3 is formed between the p-type epi layer 4 and the n ⁻ -type epi layer 2, the breakdown voltage at the groove bottom does not decrease. Therefore, by adjusting the concentration and thickness of the n ⁺ -type epi layer 3, the breakdown voltage of the body diode can be made lower than the breakdown voltage of the trench bottom, and the avalanche breakdown of the body diode occurs earlier than the trench bottom. 9 can be prevented from being destroyed.

Further, since the n-type thin-film semiconductor layer 8 is formed beside the n ⁺ -type epi layer 3, the electric field strength of the body diode portion can be reduced at the bottom of the groove. Further, since the concentration of the n-type thin film semiconductor layer 8 is lower than that of the n ⁺ -type epitaxial layer 3, the depletion layer at the bottom of the groove in the n-type thin film semiconductor layer 8 in the BB cross section is expanded by AA. The cross section can be made larger than the n ⁺ -type epi layer 3, and the maximum electric field strength in the BB portion can be made lower than that in the AA portion.

Further, since the n ⁺ -type epi layer 3 is formed below the p-type epi layer 4, electrons flowing out from the n-type thin-film semiconductor layer 8 beside the p-type epi layer 4 toward the drain electrode 13. Flows in the lateral direction, that is, the p-type epi layer 4
, Carriers can flow immediately below the n ⁻ -type epitaxial layer 2 so that the resistance of the n ⁻ -type epi layer 2 can be reduced. It is preferable that the concentration of the n ⁺ -type epi layer 3 be higher than the concentration of the n ^-- type epi layer 2 by one digit or more. By setting the n ⁺ -type epi layer 3 to such a concentration, the thickness of the n ⁺ -type epi layer 3 can be reduced to 0.3 μm or less.

Next, a manufacturing process of the trench gate type power MOSFET will be described with reference to FIGS. First, FIG.
As shown in FIG. 1, an n ⁺ -type silicon carbide semiconductor substrate 1 having a (0001-) carbon surface as a main surface is prepared, and n
^- -type epitaxial layer 2 is epitaxially grown. Furthermore, n
^An n ⁺ -type epi layer 3 is epitaxially grown on the ⁻ type epi layer 2, and a p-type epi layer 4 is epitaxially grown thereon. Thus, n ⁺ type silicon carbide semiconductor substrate 1, n
^A semiconductor substrate 100 including the-type epi layer 2, the n ⁺ type epi layer 3, and the p type epi layer 4 is formed. Since the crystal axis of n ⁺ -type silicon carbide semiconductor substrate 1 is inclined by about 3.5 ° to 8 ° to form n ⁻ -type epi layer 2, n ⁺ -type epi layer 3, and p-type epi layer 4, The plane orientation of the main surface of the semiconductor substrate 100 is
It becomes a substantially (0001-) carbon surface.

Next, as shown in FIG. 4, an n ⁺ -type source region 5 is formed in a predetermined region of the surface of the p-type epi layer 4 by, for example, nitrogen ion implantation. Further, a low-resistance p-type silicon carbide region 6 is formed in another predetermined region of the surface layer portion of p-type epi layer 4 by, for example, ion implantation of aluminum. Then, as shown in FIG. 5, RIE (Reactive I
A trench 7 that penetrates the n ⁺ -type source region 5, the p-type epi layer 4, and the n ⁺ -type epi layer 3 and reaches the n ⁻ -type epi layer 2 is formed by an “on etching” method. At this time, the side surface 7a of the groove 7 is substantially in the [11-00] direction or substantially [11-00].
The groove 7 is formed so as to be parallel to the [2-0] direction.

Next, as shown in FIG. 6, the inner wall (side surface 7a and bottom surface 7b) of the groove 7 is formed by an epitaxial growth method.
N-type thin film semiconductor layer 8 on the upper surface of semiconductor substrate 100 including
To form Specifically, 6H-Si is formed by CVD.
A 6H-SiC thin film layer is homoepitaxially grown on C, and extends to the surface of the n ⁺ -type source region 5, p-type epi layer 4, n ⁺ -type epi layer 3, and n ^-- type epi layer 2 on the inner wall of the groove 7. An n-type thin film semiconductor layer 8 is formed.

At this time, the epi growth rate is (0001-)
Since the thickness is 8 to 10 times or more in the direction perpendicular to the carbon surface, the thin film layer 8 can be formed thick on the groove side surface 7a and thin on the groove bottom surface 7b. Here, the impurity concentration of n-type thin film semiconductor layer 8 on trench side surface 7 a is set lower than the impurity concentrations of n ⁺ -type silicon carbide semiconductor substrate 1, n ⁺ -type epi layer 3 and n ⁺ -type source region 5.

In the step of forming the n-type thin film semiconductor layer 8, the n-type thin film semiconductor layer 8 is grown while reducing surface irregularities caused by the groove forming step. Therefore, the channel forming surface becomes a flat surface,
Channel mobility is improved. Further, the n-type thin film semiconductor layer 8
Since there is no crystal defect caused by ion bombardment by the RIE method, a decrease in mobility can be prevented, and the on-resistance between the source and the drain can be reduced.

Subsequently, as shown in FIG. 7, a gate oxide film (thermal oxide film) 9 is formed on the surface of the semiconductor substrate 100 and the n-type thin film semiconductor layer 8 and on the bottom surface 7b of the groove 7 by thermal oxidation. At this time, the thermal oxide film is thin on the side surface 7a and thick on the substrate surface and the groove bottom surface 7b, and the n-type thin film semiconductor layer 8 formed on the surface of the semiconductor substrate 100 and the groove bottom surface 7b by epitaxial growth becomes an oxide film. This is because the oxidation rate of hexagonal silicon carbide is the fastest on the (0001-) carbon face (0001
-) It is about 5 times as large as the plane perpendicular to the carbon plane. In this manner, the n-type thin-film semiconductor layer 8 on the surface of the semiconductor substrate 100 and the bottom surface 7b of the groove in the n-type thin-film semiconductor layer 8 formed by epitaxial growth is thermally oxidized, and the n-type thin-film semiconductor layer 8 remains only on the groove side surface 7a. Becomes

In the step of forming the gate oxide film 9,
As described above, the channel forming surface is a flat surface,
The thickness of the gate oxide film 9 formed on the channel formation surface can also be made uniform. As a result, the completed MOSFE
At T, there is no local electric field concentration point when a gate voltage is applied. Therefore, the gate oxide film breakdown voltage can be improved. For the same reason, the life of the gate oxide film can be extended.

Then, as shown in FIG. 8, the inside of the gate oxide film 9 in the trench 7 is filled with a gate electrode layer 10. Further, as shown in FIG. 9, an insulating film 11 is formed on the upper surface of the gate electrode layer 10. Thereafter, as shown in FIG. 1, source electrode layer 12 is formed on n ⁺ -type source region 5 including on interlayer insulating film 11 and low-resistance p-type silicon carbide region 6. Further, a drain electrode layer 13 is formed on the surface of n ⁺ type silicon carbide semiconductor substrate 1 to complete a trench gate type power MOSFET.

As described above, in this embodiment, the side surface 7 of the groove 7
Since the n-type thin-film semiconductor layer 8 is disposed on the gate electrode layer a and the gate electrode layer 10 is provided via the n-type thin-film semiconductor layer 8, the n-type thin-film semiconductor layer 8 serving as a channel formation region is replaced with the p-type epilayer 4, n
^The concentration can be adjusted independently of the ⁺ type epi layer 3, and the gate threshold voltage can be reduced with high breakdown voltage and low power loss. Further, the impurity concentration of the n-type thin film semiconductor layer 8 forming the channel is low, and the film thickness is reduced to about 1000 to 5000 °, so that the leak current between the source and the drain can be reduced even under a high temperature condition. Can be smaller.

In the above-described embodiment, the source electrode layer 12 formed on the n ⁺ -type source region 5 and the low-resistance p-type silicon carbide layer 6 may be made of different materials. Further, the low-resistance p-type silicon carbide layer 6 can be omitted. In this case, the source electrode layer 12 is formed so as to be in contact with the n ⁺ -type source region 5 and the first p-type epi layer 4. Also, the source electrode layer 12
May be formed at least on the surface of the n ⁺ type source region 5.

Further, in the structure shown in FIG. 1, the side face 7a of the groove 7 is substantially 90 ° with respect to the surface of the semiconductor substrate 100. However, as shown in FIG. Does not necessarily have to be close to 90 °. The groove 7 may be V-shaped without a bottom surface. Further, as shown in FIG. 11, the side surface 7a of the groove 7 need not be a flat surface, but may be a smooth curved surface. A better effect can be obtained by designing the angle between the side surface 7a of the groove 7 and the surface of the semiconductor substrate 100 so as to increase the channel mobility.

As shown in FIG. 12, the upper portion of gate electrode layer 10 may have a shape extending above n ⁺ type source region 5. With this configuration, the connection resistance between the n ⁺ -type source region 5 and the channel induced in the n-type thin film semiconductor layer 8 can be reduced. Further, as shown in FIG. 13, the thickness of the gate oxide film 9 is substantially equal at the center and the lower end of the n-type thin film semiconductor layer 8 where the channel is formed, and is lower than the lower end of the n-type thin film semiconductor layer 8. Gate electrode layer 1
The structure may reach 0. With this structure, the connection resistance between the channel and the drain region induced in the n-type thin film semiconductor layer 8 can be reduced. Moreover,
It may be implemented as shown in FIG. That is, the upper part of the gate electrode layer 10 has a shape extending above the n ⁺ -type source region 5 as shown in FIG. 12, and the lower end of the n-type thin film semiconductor layer 8 as shown in FIG. A structure in which the gate electrode layer 10 extends to the bottom may be used.

The n-type thin film semiconductor layer 8 and the p-type epi layer 4
The p-type epi layer 4 may have a crystal type different from that of
By using the SiC of H and the n-type thin film semiconductor layer 8 as SiC of 4H and increasing the mobility in the direction in which carriers flow, a MOSFET with low power loss can be obtained. Further, in the above-described embodiment, the trench 7 is formed between the n ⁺ type source region 5 and the p ⁺
The structure shown in FIG. 15 penetrates through the n-type epi layer 4 and the n ⁺ -type epi layer 3 to reach the n ⁻ -type epi layer 2. However, as shown in FIG.
^- or it may be formed up to the middle of the n ⁺ -type epitaxial layer 3 to not reach the type epi layer 2. In this case, the thickness of the n ⁺ -type epi layer 3 in contact with the bottom of the groove 7 is n
The thickness is smaller than the thickness of the ⁺ type epi layer 3. Also in this configuration, the electric field strength of the body diode portion can be reduced at the groove bottom by the n-type thin film semiconductor layer 8. (Second Embodiment) Next, a second embodiment for preventing the gate oxide film 9 from being broken at the bottom of the groove will be described.

In the configuration shown in FIG. 16, when a reverse voltage is applied between the source and the drain, a voltage is applied to both the gate oxide film 9 and the n ⁻ -type epi layer 2 in the CC section, and And the n ⁻ -type epi layer 2 distributes the applied voltage between the source and the drain. On the other hand, in the AA section, since the impurity concentration of the p-type epi layer 4 is set higher than the impurity concentration of the n ⁻ -type epi layer 2, the depletion layer hardly spreads to the p-type epi layer 4 side. The depletion layer extends only to the n ⁻ -type epi layer 2 side. In this case, the applied voltage between the source and the drain is a one-sided step junction applied only to the n ⁻ -type epi layer 2.

Such a one-sided step junction distributes an applied voltage to both the gate oxide film 9 and the n ⁻ -type epi layer 2 and extends a depletion layer to the n ⁻ -type epi layer 2 side, as in the CC cross section. The electric field strength is higher than in the case where Also, the BB section is A
This is a region between the A-section and the C-C section, and the electric field intensity is a value intermediate between the A-A section and the C-C section. Therefore, p
When the critical electric field strength at which avalanche breakdown occurs in the pn ^- diode (body diode) formed by n ^- type epilayer 4 and n ^- type epilayer 2 is reached, gate oxide film 9 moves toward n ⁺ -type silicon carbide semiconductor substrate 1. In order that the extending depletion layer does not reach n ⁺ type silicon carbide semiconductor substrate 1, n
^{If the-} type epi layer 2 is made thick, avalanche breakdown occurs first in the pn ^- diode, so that breakdown of the gate oxide film 9 at the bottom of the groove can be prevented.

In FIG. 16, a chain line in the figure indicates a depletion layer. In this case, the relationship between the depletion layer and the thickness of the n ⁻ -type epi layer 2 is W ₁ > W ₂ , W _{1 3} <is set to W _4. The thickness of the gate oxide film 9 and the impurity of the p-type epi layer 4 are set so that the voltage applied to the gate oxide film 9 at the bottom of the groove becomes higher than the voltage applied to the p-type epi layer 4 when the critical electric field intensity is reached. The density has been set. (Third Embodiment) Next, a third embodiment for preventing the gate oxide film 9 from being broken at the bottom of the groove will be described.

In this embodiment, as shown in FIG.
^-And separated from the groove 7 in the p-type epi layer 2 and in contact with the p-type epi layer 4
Embedded p-type silicon carbide semiconductor layer (hereinafter simply referred to as p-type
Embedded layer) 14 is formed. this
According to the structure, the p-type buried layer 14 and n^-Type epi layer 2
A corner 14a is formed at the bottom of the joint, and the p-type
P-type buried layer composed of the p-type layer 4 and the p-type buried layer 14
A part with a small curvature is formed. As a result, the corner
The electric field strength at the corner of the portion 14a is determined by the maximum electric field strength of the BB section.
And the p-type buried layer 14 and n ^-Type epi layer 2
Pn^-Avalanche with diode (body diode)
Causes shell breakdown.

Therefore, breakdown occurs in the pn ^- diode, so that the gate oxide film at the bottom of the groove can be prevented from being broken. Also, the p-type buried layer 1
4 is formed so as to be separated from the groove 7, the portion where the breakdown occurs is formed in the p-type epi layer 4 and the source electrode layer 12.
Can be limited to the lower part of the contacted portion 4a. Therefore, the base resistance of the n ⁺ pn ^- parasitic bipolar transistor formed by n ⁺ -type source region 5, p-type epi layer 4 and n ^-- type epi layer 2 can be substantially reduced, and hfe can be reduced. be able to. As a result, the n ⁺ pn ^- parasitic bipolar transistor becomes difficult to operate, and the avalanche withstand capability can be increased.

In this embodiment, since the buried layer 14 is of p-type, the p-type buried layer 14 is
If the groove is formed deeper, a depletion layer extending from the p-type buried layer 14 in the reverse bias state can cover the groove bottom, and the electric field intensity at the groove bottom can be reduced. As a result, the reliability of the gate oxide film 9 can be further improved.

[0051] In the above embodiment has described the case where the buried layer 14 to the p-type, the case where the n ⁺ -type buried layer 14 is also a corner portion 14a
, The avalanche breakdown can be generated by making the electric field strength higher than the maximum electric field strength in the BB section.
As a result, effects similar to those of the above embodiment can be obtained.

Next, a method of manufacturing the embodiment shown in FIG. 17 will be described. First, as shown in FIG. 18A, an n ⁺ -type silicon carbide semiconductor substrate 1 whose main surface is a (0001-) carbon surface is prepared, and an n ⁻ -type epi layer 2 is epitaxially grown on the surface. Next, as shown in FIG. 18B, a mask material 15 for ion implantation, for example, a resist or an oxide film is formed on the surface of the n ⁻ -type epi layer 2.

Next, as shown in FIG. 18C, the mask material 15 at a predetermined place separated from the groove 7 by etching is formed.
Is opened, a p-type dopant, for example, Al is implanted to a predetermined depth by an ion implantation method, and the p-type buried layer 1 is formed.
4 is formed. Then, the mask material 15 is removed, and the p-type epi layer 4 is epitaxially grown thereon to form the semiconductor substrate 100. Note that the n ⁺ -type epi layer 3 as in the first embodiment is not formed on the semiconductor substrate 100.

Thereafter, the semiconductor substrate 100 is subjected to the steps of FIG. 4 and subsequent steps in the first embodiment to complete the MOSFET having the configuration shown in FIG. In the first and second embodiments, before the avalanche breakdown occurs at the groove bottom, the body diode (the pn junction between the p-type epi layer 4 and the n ⁺ -type epi layer 3 or the p-type
And the n ⁻ -type epi layer 2) breaks down the avalanche first. However, as another method, the n ⁺ -type epi layer 3 (or the n ⁻ -type epi layer 2) and the p-type The depletion layer formed therebetween may cause so-called punch-through reaching the n ⁺ type source region 5.
However, when the avalanche breakdown is generated as in the first and second embodiments described above, there is an advantage that the withstand voltage can be controlled more easily than when the punch-through is generated.

Further, in the first embodiment, the n-type thin film semiconductor layer 8 needs to be formed in order to reduce the electric field intensity of the body diode portion at the bottom of the groove, but in the second and third embodiments, Since such relaxation of the electric field strength is not required, a structure in which the n-type thin film semiconductor layer 8 is not formed can be adopted from the viewpoint of first performing avalanche breakdown by the body diode.

Further, the present invention relates to an n-channel vertical MOS
The present invention is not limited to the FET, and can be similarly applied to a p-channel vertical MOSFET in which the p-type and the n-type are interchanged. In the present specification, when expressing the plane and the direction axis of the hexagonal single-crystal silicon carbide, a bar should be added to the required number in the original case, but the expression means is restricted. For this reason, a required number is indicated with a "-" instead of a bar over the required number.

[Brief description of the drawings]

FIG. 1 is a sectional view of a trench gate type power MOSFET according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view for explaining the operation of the trench gate type power MOSFET shown in FIG.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the trench gate type power MOSFET shown in FIG.

FIG. 4 is a cross-sectional view for explaining a manufacturing step following FIG. 3;

FIG. 5 is a cross-sectional view for explaining a manufacturing step following FIG. 4;

FIG. 6 is a cross-sectional view for explaining a manufacturing step following FIG. 5;

FIG. 7 is a cross-sectional view for explaining a manufacturing step following FIG. 6;

FIG. 8 is a cross-sectional view for explaining a manufacturing step following FIG. 7;

FIG. 9 is a cross-sectional view for explaining a manufacturing step following FIG. 8;

FIG. 10 is a sectional view showing a modification of the trench gate type power MOSFET shown in FIG. 1;

FIG. 11 is a sectional view showing a modification of the trench gate type power MOSFET shown in FIG. 1;

FIG. 12 is a sectional view showing a modification of the trench gate type power MOSFET shown in FIG. 1;

FIG. 13 is a sectional view showing a modification of the trench gate type power MOSFET shown in FIG.

FIG. 14 is a sectional view showing a modification of the trench gate type power MOSFET shown in FIG. 1;

FIG. 15 is a sectional view showing a modification of the trench gate type power MOSFET shown in FIG. 1;

FIG. 16 is a schematic sectional view of a trench gate type power MOSFET according to a second embodiment of the present invention.

FIG. 17 is a schematic sectional view of a trench gate type power MOSFET according to a third embodiment of the present invention.

18 is a trench gate type power MOSFET shown in FIG.
FIG. 6 is a cross-sectional view for describing the manufacturing process.

FIG. 19 is a sectional view of a conventional trench gate type power MOSFET.

FIG. 20 shows a trench gate type power M previously proposed by the present applicant.
FIG. 3 is a cross-sectional view of an OSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n ^<+> type silicon carbide semiconductor substrate as 1st low resistance semiconductor layer, 2 ... n < ^- > type epi layer as high resistance semiconductor layer, 3 ...
N ⁺ -type epi layer 4 as a second low-resistance semiconductor layer ... p-type epi layer as a first semiconductor layer, 5 ... n as a semiconductor region
⁺ Type source region, 7 ... groove, 7a ... side surface, 7b ... bottom surface, 8
... N-type thin film semiconductor layer as second semiconductor layer, 9 gate oxide film, 10 gate electrode layer, 11 interlayer insulating film, 1
2 ... source electrode layer as first electrode layer, 13 ... drain electrode layer as second electrode layer, 14 ... p-type buried layer, 100 ... semiconductor substrate.

Claims (8)

[Claims] A first conductive type low-resistance semiconductor layer; a first conductive type high-resistance semiconductor layer; and a second conductive type first semiconductor layer. A semiconductor substrate (100) comprising: a first conductivity type semiconductor region (5) formed in a predetermined region of a surface layer portion of the first semiconductor layer; and a semiconductor region and a first region extending from a surface of the semiconductor substrate. A second semiconductor layer (8) made of a thin film of silicon carbide formed on at least a surface of the first semiconductor layer on a side surface of the groove; A gate oxide film formed on the surface of the semiconductor layer; a gate electrode layer formed on the gate oxide film in the trench; and at least the semiconductor region on the surface of the semiconductor substrate Electrode formed on part of the surface of the first electrode A second electrode layer (1) formed on the back surface of the semiconductor substrate;
3) when a reverse bias voltage is applied to a pn junction between the second electrode layer and the first electrode layer, the surface of the gate oxide film at the bottom of the groove is subjected to avalanche breakdown. A pn junction between the first-conductivity-type high-resistance semiconductor layer and the second-conductivity-type first semiconductor layer is brought into a conductive state. . 2. A first low-resistance semiconductor layer of a first conductivity type (1).
And a first conductive type high-resistance semiconductor layer (2), a first conductive type second low-resistance semiconductor layer (3), and a second conductive type first semiconductor layer (4). Semiconductor substrate (10
0), a first conductivity type semiconductor region (5) formed in a predetermined region of a surface portion of the first semiconductor layer, and penetrating the semiconductor region and the first semiconductor layer from the surface of the semiconductor substrate. A groove reaching at least the second low-resistance semiconductor layer; and a second semiconductor layer formed of a silicon carbide thin film formed on at least a surface of the first semiconductor layer on a side surface of the groove. A gate oxide film (9) formed on at least the surface of the second semiconductor layer; a gate electrode layer (10) formed on the gate oxide film in the trench; and a surface of the semiconductor substrate A first electrode layer (12) formed on at least a part of the surface of the semiconductor region; and a second electrode layer (1) formed on the back surface of the semiconductor substrate.
3) A silicon carbide semiconductor device comprising: 3. The semiconductor device according to claim 2, wherein the second low-resistance semiconductor layer includes a gate at a bottom of the groove when a reverse bias voltage is applied to a pn junction between the second electrode layer and the first electrode layer. Before the surface of the oxide film undergoes avalanche breakdown, its thickness and impurity concentration are set so that the pn junction between the second low-resistance semiconductor layer and the first semiconductor layer undergoes avalanche breakdown. 3. The silicon carbide semiconductor device according to claim 2, wherein: 4. A semiconductor made of silicon carbide in which a first conductive type low resistance semiconductor layer (1), a first conductive type high resistance semiconductor layer (2), and a second conductive type semiconductor layer (4) are laminated. Substrate (1
00); a first conductivity type semiconductor region (5) formed in a predetermined region of a surface portion of the semiconductor layer; and a groove (7) penetrating the semiconductor region and the semiconductor layer from the surface of the semiconductor substrate. A gate oxide film (9) formed on at least a surface of the second semiconductor layer; a gate electrode layer (10) formed on the gate oxide film in the trench; The first electrode layer (12) formed on at least a part of the surface of the semiconductor region, and the second electrode layer (1) formed on the back surface of the semiconductor substrate.
3) wherein the high resistance semiconductor layer has a reverse bias voltage applied to a pn junction between the second electrode layer and the first electrode layer, and the high resistance semiconductor layer and the semiconductor layer A depletion layer extending from the gate oxide film toward the low-resistance semiconductor layer is set to a thickness that does not reach the low-resistance semiconductor layer when the pn junction between the first and second semiconductor layers becomes conductive. Silicon carbide semiconductor device. 5. A high-resistance semiconductor layer, wherein a reverse bias voltage is applied to a pn junction between the second electrode layer and the first electrode layer, and the high-resistance semiconductor layer and the first resistance layer are connected to each other. When the PN junction of the semiconductor layer reaches the critical electric field strength at which avalanche breakdown occurs, the thickness is set so that the depletion layer extending from the gate oxide film toward the low-resistance semiconductor layer does not reach the low-resistance semiconductor layer. The silicon carbide semiconductor device according to claim 4, wherein: 6. A semiconductor made of silicon carbide in which a first conductive type low resistance semiconductor layer (1), a first conductive type high resistance semiconductor layer (2), and a second conductive type semiconductor layer (4) are laminated. Substrate (1
00); a first conductivity type semiconductor region (5) formed in a predetermined region of a surface portion of the semiconductor layer; and a groove (7) penetrating the semiconductor region and the semiconductor layer from the surface of the semiconductor substrate. A gate oxide film (9) formed on at least a surface of the second semiconductor layer; a gate electrode layer (10) formed on the gate oxide film in the trench; The first electrode layer (12) formed on at least a part of the surface of the semiconductor region, and the second electrode layer (1) formed on the back surface of the semiconductor substrate.
3), wherein a buried semiconductor layer (14) is formed in the high-resistance semiconductor layer so as to be separated from the groove and in contact with the semiconductor layer. 7. The silicon carbide semiconductor device according to claim 6, wherein said buried semiconductor layer is of a first conductivity type. 8. The silicon carbide semiconductor device according to claim 6, wherein said buried semiconductor layer is of a second conductivity type.