JP3415340B2 - Silicon carbide semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device, for example, an insulated gate field effect transistor, and more particularly to a vertical MOSFET for high power.

[0002]

2. Description of the Related Art In recent years, a vertical power MOSF manufactured by using a silicon carbide single crystal material as a power transistor.
ET is proposed. In order to reduce the loss of the power transistor, it is necessary to reduce the on-resistance, and as an element capable of effectively reducing the on-resistance, the groove gate type power MOSFET shown in FIG. 9 (for example, Japanese Patent Laid-Open No. 4-239778).
Issue). In the trench gate type power MOSFET in FIG. 9, an n-type epitaxial layer 22 is formed on an n-type silicon carbide semiconductor substrate 21, a p-type epitaxial layer 23 is further formed on the n-type epitaxial layer 22, and a p-type epitaxial layer 23 is further formed. An n-type source region 24 is formed in a predetermined region of the epitaxial layer 23. Further, a recess 25 penetrating the n-type source region 24 and the p-type epitaxial layer 23 and reaching the n-type epitaxial layer 22 is formed, and a gate electrode 27 is formed in the recess 25 via a gate insulating film 26.
Are formed. The insulating film 2 is formed on the upper surface of the gate electrode 27.
8 is formed and the n-type source region 24 including on the insulating film 28 is formed.
A source electrode film 29 is formed thereon, and a drain electrode film 30 is formed on the surface of the n-type silicon carbide semiconductor substrate 21.

Here, in the channel through which carriers flow between the source terminal and the drain terminal, a voltage is applied to the gate electrode 27, and the gate is sandwiched between the gate electrode 27 and the p-type epitaxial layer 23 on the side wall of the recess 25. An electric field is applied to the insulating film 26 to invert the conductivity type of the p-type epitaxial layer 23 in contact with the gate insulating film 26.

[0004]

However, in the trench gate type power MOSFET shown in FIG. 9, the impurity concentration of the region where the channel is formed is p type epitaxial layer 23.
It was specified by the impurity concentration of. As a result, the following problems have occurred. One of the parameters that determines the source-drain breakdown voltage of the power MOSFET having the structure shown in FIG. 9 is the impurity concentration N _A of the p-type epitaxial layer 23 and the thickness a sandwiched between the source region 24 and the n-type epitaxial layer 22. Is. The source-drain breakdown voltage is governed by the avalanche condition of the pn junction between the p-type epitaxial layer 23 and the n-type epitaxial layer 22 and the condition that the p-type epitaxial layer 23 is depleted and punch-through occurs. Therefore, the impurity concentration N _A of the p-type epitaxial layer 23 must be sufficiently high and the thickness a must be sufficiently thick. However, when the impurity concentration N _A of the p-type epitaxial layer 23 is increased, there is a problem that the gate threshold voltage is increased, and the impurity mobility is increased, so that the channel mobility is decreased and the on-resistance is increased. Further, when the thickness a is increased, the channel length becomes longer, and there is a problem that the on-resistance increases.

As described above, in order to realize a power MOSFET having a high breakdown voltage, a small current loss during operation, and a low threshold voltage, the impurity concentrations of the p-type epitaxial layer and the region where the channel is formed must be controlled independently. However, it was difficult with the conventional structure.

In order to solve the above-mentioned problems, the concentration of the channel forming layer is reduced by the thermal diffusion method in the trench gate type power MOSFET using the silicon single crystal. However, the trench gate type power M using silicon carbide
In the OSFET, there is a new problem that the thermal diffusion method cannot be used because the thermal diffusion constant of impurity atoms in silicon carbide is extremely small.

Therefore, an object of the present invention is to provide a silicon carbide semiconductor device having high breakdown voltage, low loss, and low threshold voltage.

[0008]

According to a first aspect of the present invention, there are provided a first conductivity type low resistance semiconductor layer, a first conductivity type high resistance semiconductor layer, and a second conductivity type first semiconductor layer. A semiconductor substrate made of single-crystal silicon carbide, which is formed by stacking in order, a first-conductivity-type semiconductor region formed in a predetermined region of a surface layer portion in the first semiconductor layer, the semiconductor region, and the semiconductor region. A groove penetrating the first semiconductor layer to reach the high resistance semiconductor layer, the semiconductor region forming a side surface of the groove, the silicon carbide extended to the surfaces of the first semiconductor layer and the high resistance semiconductor layer. A second conductive type second semiconductor layer formed of a thin film, a part of the surface of the semiconductor region, the surface of the second semiconductor layer and the surface of the high resistance semiconductor layer in the groove. Gate insulating film and a gate electrode formed on the surface of the gate insulating film When a first electrode layer formed on a part of the first surface of the semiconductor layer and said surface of at least the semiconductor region of the portion of the surface of the semiconductor region,
A gist of the present invention is a silicon carbide semiconductor device including a second electrode layer formed on the surface of the low resistance semiconductor layer.

According to a second aspect of the present invention, there is provided a silicon carbide semiconductor device in which the crystal type of the second semiconductor layer in the first aspect of the invention is the same as the crystal type of the first semiconductor layer. Use as a summary.

The invention described in claim 3 is the invention according to claim 1 or 2.
The gist of the invention is a silicon carbide semiconductor device in which the semiconductor substrate and the second semiconductor layer in the invention described in (3) are made of hexagonal silicon carbide.

According to a fourth aspect of the present invention, the substrate surface on which the semiconductor region of the semiconductor substrate according to any one of the first to third aspects is formed is approximately (0001).
The gist is a silicon carbide semiconductor device having a carbon surface.

According to a fifth aspect of the invention, the impurity concentration of the second semiconductor layer in the first aspect of the invention is lower than the impurity concentration of the first semiconductor layer, and the second semiconductor layer has a lower impurity concentration. The gist of the crystal type is a silicon carbide semiconductor device different from the crystal type of the first semiconductor layer. (Operation) According to the invention described in claim 1, by applying a voltage to the gate electrode layer (gate terminal) and applying an electric field to the gate insulating film, the conductivity type of the second semiconductor layer is inverted, Carriers flow between the first electrode layer (source terminal) and the second electrode layer (drain terminal). That is, the second semiconductor layer serves as a channel formation region.

At this time, by controlling the impurity concentration of the first semiconductor layer and the impurity concentration of the second semiconductor layer independently,
A silicon carbide semiconductor device having a high breakdown voltage, a low current loss, and a low threshold voltage can be obtained. In particular, by lowering the impurity concentration of the second semiconductor layer forming the channel, the influence of impurity scattering when carriers flow can be reduced and the channel mobility can be increased. Since the source-drain breakdown voltage is mainly controlled by the impurity concentration of the high-resistance semiconductor layer and the first semiconductor layer and the film thickness thereof, the impurity concentration of the first semiconductor layer is increased to increase the impurity concentration of the first semiconductor layer. Since the film thickness can be reduced and the channel length can be shortened while maintaining high withstand voltage, the channel resistance can be dramatically reduced and the on-resistance between the drain and the source can be reduced.

According to the invention of claim 2, claim 1
In addition to the effect of the invention described in (1), the crystal type of the second semiconductor layer is the same as the crystal type of the first semiconductor layer, so that the structure of the present invention can be easily formed.

According to the invention of claim 3, claim 1
Alternatively, in addition to the effect of the invention described in 2, the semiconductor substrate and the second semiconductor layer are made of hexagonal silicon carbide, which is more preferable.

According to the invention of claim 4, claim 1
In addition to the effect of the invention described in any one of 1 to 3, since the surface of the semiconductor substrate is the (0001) carbon surface, the high breakdown voltage structure can be easily formed.

According to the invention of claim 5, claim 1
In addition to the effect of the invention described in (1), since the impurity concentration of the second semiconductor layer is lower than the impurity concentration of the first semiconductor layer, the channel resistance can be reduced.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows n in the present embodiment.
The sectional view of a channel type groove gate type power MOSFET (vertical type power MOSFET) is shown.

Hexagonal system silicon carbide is used for n ⁺ type silicon carbide semiconductor substrate 1 as the low resistance semiconductor layer. On this n ⁺ type silicon carbide semiconductor substrate 1, an n ⁻ type silicon carbide semiconductor layer 2 as a high resistance semiconductor layer and a p type silicon carbide semiconductor layer 3 as a first semiconductor layer are sequentially laminated.

As described above, the n ⁺ type silicon carbide semiconductor substrate 1
And n ⁻ type silicon carbide semiconductor layer 2 and p type silicon carbide semiconductor layer 3
The semiconductor substrate 13 made of single crystal silicon carbide is constituted by and the upper surface of the semiconductor substrate 13 is a substantially (0001) carbon surface.

An n ⁺ type source region 4 as a semiconductor region is formed in a predetermined region in the surface layer portion of p type silicon carbide semiconductor layer 3. Furthermore, the p-type silicon carbide semiconductor layer 3
A low resistance p-type silicon carbide region 5 is formed in a predetermined region on the outer peripheral side of the n ⁺ -type source region 4 in the inner surface layer portion.

A groove 6 is formed at a predetermined position of the n ⁺ type source region 4.
The trench 6 penetrates the n ⁺ type source region 4 and the p type silicon carbide semiconductor layer 3 to reach the n ⁻ type silicon carbide semiconductor layer 2. The groove 6 has a side surface 6 a perpendicular to the surface of the semiconductor substrate 13 and a bottom surface 6 b parallel to the surface of the semiconductor substrate 13.

On the surface of the n ⁺ type source region 4, the p type silicon carbide semiconductor layer 3 and the n ⁻ type silicon carbide semiconductor layer 2 on the side surface 6a of the groove 6, a p type silicon carbide semiconductor thin film as a second semiconductor layer is formed. Layer 7 is extended. The crystal type of the p-type silicon carbide semiconductor thin film layer 7 is the same as the crystal type of the p-type silicon carbide semiconductor layer 3, and is 6H—SiC, for example. Other than this, it may be 4H-SiC or 3C-SiC. Further, the impurity concentration of the p-type silicon carbide semiconductor thin film layer 7 is lower than the impurity concentration of the p-type silicon carbide semiconductor layer 3 (10 ¹⁵ to 10 ¹⁶ cm ^-3 ).

Further, the surface of the n ⁺ type source region 4 near the opening of the groove 6, the surface of the p type silicon carbide semiconductor thin film layer 7 in the groove 6 and the bottom surface 6b of the groove 6 are continuously gate insulated. Membrane 8
Are formed. A gate electrode layer 9 is formed on the inside of the gate insulating film 8 in the groove 6 and on the gate insulating film 8 on the surface of the semiconductor substrate 13. Gate electrode layer 9
Are covered with an insulating film 10. Source electrode layer 11 as a first electrode layer is formed on the surface of n ⁺ type source region 4 and the surface of low resistance p type silicon carbide region 5. n
A drain electrode layer 12 as a second electrode layer is formed on the front surface (back surface of the semiconductor substrate 13) of the ⁺ type silicon carbide semiconductor substrate 1.

As the operation of this trench gate type power MOSFET, by applying a voltage to the gate electrode layer 9 and applying an electric field to the gate insulating film 8, the conductivity type of the p-type silicon carbide semiconductor thin film layer 7 is inverted, Carriers flow between the source electrode layer 11 and the drain electrode layer 12. That is, the p-type silicon carbide semiconductor thin film layer 7 becomes the channel formation region.

Here, by controlling the impurity concentration of the p-type silicon carbide semiconductor layer 3 and the impurity concentration of the p-type silicon carbide semiconductor thin film layer 7 independently, a MOSFET having a high withstand voltage, a low current loss and a low threshold voltage is obtained. Become. In particular, p forming the channel
By lowering the impurity concentration of the silicon carbide semiconductor thin film layer 7, the influence of impurity scattering when carriers flow can be reduced, and the channel mobility can be increased. Since the source-drain breakdown voltage is mainly controlled by the impurity concentration of the n ⁻ type silicon carbide semiconductor layer 2 and the p type silicon carbide semiconductor layer 3 and its film thickness, the impurity concentration of the p type silicon carbide semiconductor layer 3 is increased. Thus, the film thickness of p-type silicon carbide semiconductor layer 3 can be reduced, and the channel length can be shortened while maintaining high withstand voltage. Therefore, the channel resistance can be dramatically reduced, and the on-resistance between the drain and the source can be reduced.

Next, a manufacturing process of the trench gate type power MOSFET will be described with reference to FIGS. First, as shown in FIG. 2, an n ⁺ -type silicon carbide semiconductor substrate 1 is prepared, an n ⁻ -type silicon carbide semiconductor layer 2 is epitaxially grown on the surface of the n ⁻ -type silicon carbide semiconductor substrate 2, and a p-type carbon carbide semiconductor layer 2 is further formed on the n ⁻ -type silicon carbide semiconductor layer 2. The silicon semiconductor layer 3 is epitaxially grown. Thus, semiconductor substrate 13 formed of n ⁺ type silicon carbide semiconductor substrate 1, n ⁻ type silicon carbide semiconductor layer 2 and p type silicon carbide semiconductor layer 3 is formed.

Next, as shown in FIG.
In a predetermined region of the surface layer of the conductor layer 3, n ⁺Mold source area 4
Are formed by, for example, ion implantation of nitrogen. further,
A low resistance is applied to another predetermined region of the surface layer portion of the p-type silicon carbide semiconductor layer 3.
The anti-p-type silicon carbide region 5 is formed by, for example, aluminum ions.
It is formed by injection.

Then, as shown in FIG. 4, n ⁻ -type source region 4 and p-type silicon carbide semiconductor layer 3 are penetrated together to form n ^{− −.}
Groove 6 reaching type silicon carbide semiconductor layer 2 is formed. Further, as shown in FIG. 5, p-type silicon carbide semiconductor thin film layer 7 is formed on side surface 6 a of groove 6. That is, p ⁺ type silicon carbide semiconductor thin film layer 7 extending to the surfaces of n ⁺ type source region 4, p type silicon carbide semiconductor layer 3 and n ⁻ type silicon carbide semiconductor layer 2 on the inner wall of trench 6 is formed. Here, the impurity concentration of p-type silicon carbide semiconductor thin film layer 7 on groove side surface 6 a is set lower than the impurity concentration of p-type silicon carbide semiconductor layer 3. As a more specific method for forming the p-type silicon carbide semiconductor thin film layer 7, C
By the VD method, for example, 6H-SiC on 6H-SiC
The thin film layer 7 is grown by homoepitaxial growth.

Subsequently, as shown in FIG. 6, a gate insulating film 8 is formed on the surfaces of semiconductor substrate 13 and p-type silicon carbide semiconductor thin film layer 7 and on bottom surface 6b of trench 6. Then, as shown in FIG. 7, the surface of the gate insulating film 8 in the groove 6 and the groove 6
A gate electrode layer 9 is formed around the opening. further,
As shown in FIG. 8, the insulating film 10 is formed on the upper surface of the gate electrode layer 9.
To form. Thereafter, as shown in FIG. 1, source electrode layer 11 is formed on source region 4 including insulating film 10 and low resistance p-type silicon carbide region 5. Further, the drain electrode layer 12 is formed on the surface of the n ⁺ type silicon carbide semiconductor substrate 1 to complete the groove gate type power MOSFET.

As described above, in this embodiment, the p-type silicon carbide semiconductor thin film layer 7 is arranged on the side surface 6a of the groove 6, and the gate electrode is formed on the p-type silicon carbide semiconductor thin film layer 7 via the gate insulating film 8. Since the layer 9 is provided, the p-type silicon carbide semiconductor thin film layer 7 to be the channel forming region is formed as the p-type silicon carbide semiconductor layer 3
The concentration can be adjusted independently, and the threshold voltage can be lowered with high breakdown voltage and low current loss.

In addition to the structure described above, for example, n
^The source electrodes formed in the ⁺ type source region 4 and the low resistance p type silicon carbide region 5 may be made of different materials. Also, low resistance p
The type silicon carbide region 5 can be omitted. In this case, the source electrode layer 11 is formed so as to contact the n ⁺ type source region 4 and the p type silicon carbide semiconductor layer 3.

Further, the source electrode layer 11 may be formed on at least a part of the surface of the n ⁺ type source region 4. Although the side surface 6a of the groove 6 is vertical to the surface of the semiconductor substrate 13 in FIG. 1, it may not be vertical. Although the bottom surface 6b of the groove 6 is a surface parallel to the surface of the semiconductor substrate 13, it does not have to be parallel. The cross-sectional shape of the groove may be a V-shaped groove having no bottom surface or a U-shaped groove having a curved bottom surface.

Although the p-type silicon carbide semiconductor thin film layer 7 and the p-type silicon carbide semiconductor layer 3 have the same crystal type in the present embodiment, they may have different crystal types. In this case, the channel resistance can be further reduced by using a crystal type having a higher mobility in the carrier flow direction.

Further, in the above-mentioned example, the case where the present invention is applied to the n-channel vertical type MOSFET is explained.
P-channel vertical MO with the p-type and n-type swapped in
The same effect can be obtained in the SFET. Further, it goes without saying that modifications are included without departing from the spirit of the present invention.

The (0001) carbon surface in the present invention includes a (0001 bar) carbon surface which is a crystallographically symmetrical surface.

[0037]

As described above in detail, according to the present invention,
An excellent effect can be obtained in which the impurity concentration of the region where the channel is formed can be set to an arbitrary value to obtain a device having high breakdown voltage, low loss, and low threshold voltage.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional structure diagram of an n-channel groove type SiC MOSFET for explaining an embodiment.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of an n-channel groove type SiC MOSFET.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of an n-channel groove type SiC MOSFET.

FIG. 4 is a sectional view for explaining a manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 6 is a sectional view for explaining a manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 7 is a sectional view for explaining a manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 8 is a cross-sectional view for explaining the manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 9: Conventional silicon carbide trench gate type power MOSFE
The schematic diagram of the cross-sectional structure of T.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n ^<+> type | mold silicon carbide semiconductor substrate as a low resistance semiconductor layer, 2 ... n < ^- > type | mold silicon carbide semiconductor layer as a high resistance semiconductor layer, 3 ... p type silicon carbide semiconductor layer as a 1st semiconductor layer, 4 ... N ⁺ type source region as a semiconductor region, 6 ...
Groove, 6a ... Side surface, 6b ... Bottom surface, 7 ... P-type silicon carbide semiconductor layer as second semiconductor layer, 8 ... Gate insulating film, 9 ... Gate electrode layer, 11 ... Source electrode layer as first electrode layer , 12 ... Drain electrode layer as second electrode layer, 13
... Semiconductor substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Norihito Togura, 1-chome, Showa-cho, Kariya city, Aichi Prefecture, Nihon Denso Co., Ltd. (72) Inventor Hiroo Oma 1 41, Yokomichi, Nagakute-cho, Aichi-gun, Aichi prefecture Toyota Central Research Institute Co., Ltd. (56) Reference JP-A-7-131016 (JP, A) JP-A-2-91976 (JP, A) International Publication 94/013017 (WO, A1) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/36

Claims (5)

(57) [Claims] 1. A single-crystal silicon carbide, which is formed by sequentially laminating a low-resistance semiconductor layer of a first conductivity type, a high-resistance semiconductor layer of a first conductivity type, and a first semiconductor layer of a second conductivity type. A semiconductor substrate made of: a semiconductor region of a first conductivity type formed in a predetermined region of a surface layer portion in the first semiconductor layer; the high-resistance semiconductor layer penetrating the semiconductor region and the first semiconductor layer; a groove reaching said semiconductor region and said first semiconductor layer and the second semiconductor of the second conductivity type made of a thin film of extending silicon carbide on the surface of the high resistance semiconductor layer to form a side surface of said groove A layer, a part of the surface of the semiconductor region, a gate insulating film extending on the surface of the second semiconductor layer and the surface of the high resistance semiconductor layer in the groove, and on the surface of the gate insulating film. The formed gate electrode layer, the surface of the first semiconductor layer, and A first electrode layer formed on at least a part of the surface of the semiconductor region among a part of the surface of the semiconductor region; and a second electrode layer formed on the surface of the low resistance semiconductor layer. A silicon carbide semiconductor device characterized by the above. 2. The silicon carbide semiconductor device according to claim 1, wherein the crystal type of the second semiconductor layer is the same as the crystal type of the first semiconductor layer. 3. The silicon carbide semiconductor device according to claim 1, wherein the semiconductor substrate and the second semiconductor layer are made of hexagonal silicon carbide. 4. The silicon carbide semiconductor device according to claim 1, wherein the substrate surface of the semiconductor substrate on which the semiconductor region is formed has a substantially (0001) carbon surface. 5. The impurity concentration of the second semiconductor layer is lower than the impurity concentration of the first semiconductor layer, and the crystal type of the second semiconductor layer is different from the crystal type of the first semiconductor layer. The silicon carbide semiconductor device according to claim 1, wherein.