JP5101030B2 - Trench-type MOSFET and manufacturing method thereof - Google Patents

Description

  The present invention relates to a trench MOSFET having a drift layer made of silicon carbide and a method for manufacturing the same.

  Recently, a trench MOSFET made of silicon carbide, which has a high withstand voltage and low loss and is capable of high-speed switching operation, has been developed. The trench type MOSFET can greatly increase the channel density per unit area as compared with the planar type MOSFET. Therefore, the current that flows per unit area increases, and the on-resistance that causes conduction loss can be reduced. However, when a MOSFET is formed using silicon carbide, it is difficult to reduce the on-resistance because the mobility of electrons passing through the MOS channel (channel mobility) is low.

  Therefore, the trench type MOSFET of Patent Document 1 uses a (000-1) carbon surface on the main surface, and forms trench sidewalls parallel to the [1-100] direction. Patent Document 1 improves the channel mobility of a trench MOSFET by forming a MOS channel with a surface having a low MOS interface state density as a trench sidewall.

JP-A-10-229190

  However, in the trench MOSFET described in Patent Document 1, it is necessary to increase the impurity concentration of the base region in consideration of the breakdown voltage. As a result, Coulomb scattering due to impurities in the base region increases, and the channel mobility of the trench MOSFET decreases.

  Accordingly, an object of the present invention is to provide a trench MOSFET having a high channel mobility while maintaining a withstand voltage, and a method for manufacturing the same.

According to a first aspect of the present invention, there is provided a trench MOSFET manufacturing method comprising: forming a drift layer made of silicon carbide of a first conductivity type on a semiconductor substrate made of silicon carbide; and forming a second layer on a surface layer portion of the drift layer. A step of forming a second region made of conductive silicon carbide, a step of forming a groove having a bottom in the drift layer through the second region, and a first side along the sidewall of the groove Forming an impurity layer made of conductive silicon carbide, forming a source region made of silicon carbide of the first conductivity type in contact with the impurity layer on a surface layer portion of the second region, by diffusing an impurity from the second region to the impurity layer and the drift layer, the realm that in contact with the second region of the impurity layer and the drift layer, first made of silicon carbide of a second conductivity type 1 region Formed and characterized in that it comprises the steps of forming a base region made of silicon carbide having a said first region and the second region.
The trench type MOSFET according to claim 5 is a drift layer made of silicon carbide of a first conductivity type formed on a semiconductor substrate made of silicon carbide, and a second conductivity type made of a surface layer portion of the drift layer. A base region made of silicon carbide, a source region made of silicon carbide of a first conductivity type formed in a surface layer portion of the base region, the base region and the source region being in contact with a side wall, and a lower end being the base A groove portion formed in the drift layer so as to reach a region other than the region and the source region, and the base region is formed with a certain width from the sidewall of the groove portion along the sidewall of the groove portion. A first region of the second conductivity type and a second region other than the first region, and the impurity concentration of the first region is lower than the impurity concentration of the second region, Dori The base region joined to the first layer becomes the first region having a profile in which the density of the second conductivity type impurity is distributed from the high concentration to the low concentration from the second region toward the drift layer side. It is characterized by.

According to the method for manufacturing a trench MOSFET according to claim 1, since the first region is formed by diffusion of impurity ions from the second region, even a complicated structure such as a trench MOSFET can be easily formed. A base region having a second region with a relatively high concentration and a first region with a relatively low concentration can be formed.
Further, since the impurities in the second region also diffuse in the vertical direction, the density of the second conductivity type impurity is distributed from the high concentration to the low concentration from the second region toward the drift layer side in the base region joined to the drift layer. It becomes the 1st field which has the profile to do. Therefore, a pn junction in which the impurity density gently changes is formed at the interface between the drift layer and the first region. For this reason, the avalanche resistance of the pn junction is improved, and a high breakdown voltage can be realized.
According to the trench type MOSFET of the fifth aspect , since the channel is formed in the first region having the impurity concentration lower than that of the second region, the Coulomb scattering due to the impurity is suppressed and the channel mobility is increased. In addition, punch-through is suppressed and the breakdown voltage can be maintained by the second region having a high impurity concentration. Further, since the trench type MOSFET according to claim 5 does not have a so-called accumulation mode structure, it is possible to easily realize normally OFF.
Further, the base region joined to the drift layer is a first region having a profile in which the density of the second conductivity type impurity is distributed from a high concentration to a low concentration from the second region toward the drift layer side. Therefore, a pn junction in which the impurity density gently changes is formed at the interface between the drift layer and the first region. For this reason, the avalanche resistance of the pn junction is improved, and a high breakdown voltage can be realized.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
<A. Configuration>
FIG. 1 is a cross-sectional view showing the configuration of the main part of the trench MOSFET according to the first embodiment. FIG. 1 is a diagram showing a cross-sectional structure of one trench MOSFET among a plurality of trench MOSFETs that are continuously arranged in a comb shape or a polygon shape on a semiconductor substrate. FIG. 2 is an enlarged sectional view of the vicinity of the side wall of the trench 20 of the trench MOSFET according to the first embodiment. Hereinafter, the configuration of the trench MOSFET according to the first embodiment will be described in detail with reference to FIGS.

  Drift layer 2 made of silicon carbide of the first conductivity type is formed on semiconductor substrate 1 (substrate) of the first conductivity type (n-type in the example of the first embodiment). A base region 3 of the second conductivity type (p type in the example of the first embodiment) is formed in the surface layer portion of the drift layer 2. A source region 4 of the first conductivity type is formed on the surface layer portion of the base region 3. A trench (groove) 20 is formed in the drift layer 2 so that the base region 3 and the source region 4 are in contact with the side walls, and the lower end reaches a region other than the base region 3 and the source region 4.

  The base region 3 includes a first conductivity type first region 3 a formed with a certain width from the sidewall of the trench 20 along the sidewall of the trench 20. In the first embodiment, the width t (see FIG. 2) of the first region 3a is such that impurities (acceptors) are diffused from the second region 3b to the first region 3a, which will be described later, The distance is set to 2 μm or less so that the distance can be sufficiently diffused.

The impurity concentration (acceptor concentration) of the first region 3a is formed lower than the impurity concentration (acceptor concentration) of the second region 3b, which is the base region 3 other than the first region 3a. Then, in order to realize a high breakdown voltage trench MOSFET having a breakdown voltage of several hundred V or more and 3 kV or less, the impurity concentration of the second region 3b is 1 × 10 ¹⁷ / cm ³ or more and 5 × 10 ¹⁸ / cm ³ or less. It is desirable to be.

Here, the impurity density (donor density) of the semiconductor substrate 1 is desirably 1 × 10 ¹⁸ cm ⁻³ or more. The drift layer 2 is formed on the semiconductor substrate 1 by epitaxial growth. Further, the plane orientation of the main surface of the semiconductor substrate 1 may be any plane orientation such as a (0001) plane or a (11-20) plane.

  A first conductivity type epitaxial layer 9 (impurity layer) formed in a separate process from the drift layer 2 is formed at the bottom of the trench 20. A source electrode 7 is formed on the source region 4. A gate insulating film 5 is formed inside the trench 20. The gate insulating film 5 is formed in contact with the end region of the source region 4, the base region 3, and the drift layer 2. A gate electrode 6 is formed on the gate insulating film 5. Furthermore, a drain electrode 8 is formed on the main surface of the semiconductor substrate 1 opposite to the main surface on which the drift layer 2 is formed.

<B. Manufacturing method>
Next, a method for manufacturing a trench MOSFET according to the first embodiment will be described with reference to FIGS. 3 to 8 and 10 are cross-sectional views showing the manufacturing process of the trench MOSFET according to the first embodiment.

First, a semiconductor substrate 1 made of silicon carbide is prepared. Here, in the description, it is assumed that the conductivity type of the semiconductor substrate 1 is n-type. The impurity density (donor density) of the semiconductor substrate 1 is desirably 1 × 10 ¹⁸ cm ⁻³ or more. Next, as shown in FIG. 3, the drift layer 2 is formed on the semiconductor substrate 1 by the epitaxial crystal growth method. Here, it is assumed that the conductivity type of the drift layer 2 is the same n type as that of the semiconductor substrate 1.

In addition, the epitaxial growth of the drift layer 2 is controlled so that the thickness is 5 μm or more and 50 μm or less, and the n-type impurity concentration (donor density) is 1 × 10 ¹⁵ / cm ³ or more and 1 × 10 ¹⁷ / cm ³ or less. As a result, a trench MOSFET having a breakdown voltage of several hundred volts to 3 kV can be realized. Here, when the n-type drift layer 2 is formed as described above, nitrogen (N), phosphorus (P), or the like can be employed as the impurity dopant element.

  Next, a mask having a predetermined shape is applied to the upper surface of the drift layer 2 and impurity ions (p-type) are implanted. As a result, as shown in FIG. 4, the second region 3b which is p-type is formed. Here, FIG. 4 is a diagram showing a cross section of the element after removing the mask. Here, since the trench 20 is formed in the region where the ions are not implanted between the second regions 3b, the ion implantation may or may not be performed. Further, in the ion implantation process for forming the second region 3b, boron (B) that is relatively easily diffused in silicon carbide is employed as the impurity ions.

  In the ion implantation process, it is desirable that the depth of the second region 3 b does not exceed the thickness of the drift layer 2. For example, the thickness (depth) of the second region 3 b may be about 0.5 to 5 μm from the surface of the drift layer 2. Further, the second conductivity type (p-type) impurity concentration (acceptor concentration) in the second region 3 b exceeds the first conductivity type (n-type) impurity concentration (donor concentration) in the drift layer 2. .

The impurity concentration of the second region 3b is, for example, 1 × 10 ¹⁷ so that a trench MOSFET having a desired breakdown voltage can be realized, that is, punch-through breakdown of the base region 3 does not occur when the trench MOSFET is turned off. / Cm ³ or more and 5 × 10 ¹⁸ / cm ³ or less. After each of the above ion implantation processes, a mask is formed on the upper surface of the drift layer 2 and the second region 3b by photolithography, and a trench 20 is formed between the second regions 3b of the drift layer 2 by dry or wet etching. (FIG. 5). The depth of the trench 20 is set so as to exceed the depth of the second region 3 b and not to exceed the thickness of the drift layer 2. Therefore, the bottom of the trench 20 is formed in the drift layer 2.

  Next, epitaxial growth is performed on the semiconductor substrate 1 to form an epitaxial layer 9 which is an impurity layer of the first conductivity type along the sidewall of the trench 20 as shown in FIG. Here, the conductivity type of the epitaxial layer 9 is the first conductivity type, and is n-type here. The thickness is set to 0.01 μm or more and 2 μm or less.

  The n-type epitaxial layer 9 becomes a p-type region corresponding to a first region 3a formed by B (boron) diffusion described later. In order to form a channel region with a low acceptor density, the epitaxial growth is controlled so that the donor concentration of the epitaxial layer 9 is lower than the desired acceptor concentration of the first region 3a after diffusion.

  Next, a mask having a predetermined shape is applied to the upper surface of the second region 3b, and impurity ions (n-type) are implanted. As a result, an n-type source region 4 is formed as shown in FIG. Here, FIG. 7 is a diagram showing a cross section of the element after removing the mask. Further, in the ion implantation process for creating the source region 4, when the n-type source region 4 is created as described above (in other words, in the case of an n-channel MOSFET), for example, phosphorus ( P), nitrogen (N), or the like can be employed.

The depth of the source region 4 should not exceed the depth of the second region 3b. Furthermore, since the difference in depth between the base region 3 and the source region 4 becomes the channel length, the depth of the source region 4 is controlled so that a desired channel length is obtained. Further, the impurity density (donor concentration) in the source region 4 exceeds the impurity density (acceptor concentration) in the second region 3b, for example, 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less. If it is.

  The semiconductor substrate 1 subjected to the above ion implantation process is introduced into a heat treatment apparatus. Then, heat treatment is performed on the semiconductor substrate 1. The temperature of the heat treatment is, for example, 1300 to 1900 ° C., and the time is, for example, about 30 seconds to 1 hour. By the heat treatment, ions implanted into the semiconductor substrate 1 can be electrically activated.

  Here, B, which is an impurity easily diffusing in silicon carbide, diffuses in and out from the implanted second region 3b. At this time, B diffuses into the n-type epitaxial layer 9, and the conductivity type of the region in contact with the second region 3b of the epitaxial layer 9 is inverted to the p-type. As a result, as shown in FIG. 8, the first conductivity type first region 3a is formed.

By controlling the density of B in the first region 3a according to conditions such as the temperature and time of heat treatment, the p-type impurity density (acceptor concentration) of the first region 3a serving as a channel can be controlled. For example, the p-type impurity density of the first region 3a may be 5 × 10 ¹³ cm ³ or more and less than 5 × 10 ¹⁸ / cm ³ . Further, the p-type impurity density of the first region 3a does not have to be constant, and the first region 3a is laterally directed from the second region 3b side toward the trench 20 side wall (a direction parallel to the main surface of the semiconductor substrate 1). ) May have a concentration profile. The first region 3 a may have a concentration profile in the vertical direction (direction perpendicular to the main surface of the semiconductor substrate 1) from the interface side with the source region 4 toward the interface side with the drift layer 2.

FIG. 9 is a diagram for explaining the impurity profile of the first region of the trench MOSFET according to the first embodiment. FIG. 9 shows an example of the p-type impurity density profile in the lateral direction of the region where the channel is formed in the first region 3a. The x-axis in FIG. 9 corresponds to the distance from the trench sidewall in the direction of the arrow in FIG. Here, the first region 3a has a profile with a thickness of 0.2 μm and a p-type impurity density increasing from 1 × 10 ¹⁷ / cm ³ to 1 × 10 ¹⁸ / cm ^3. The type impurity density is 1 × 10 ¹⁸ / cm ³ .

  Next, the semiconductor substrate 1 is taken out from the heat treatment apparatus, and a gate insulating film 5 is formed on the surface of the drift layer 2 (FIG. 10). As the gate insulating film 5, a silicon dioxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, a hafnium oxide film, a zirconium oxide film, or the like can be employed.

  Next, the gate electrode 6 is filled on the gate insulating film 5 inside the trench 20. Thereafter, the source region 4 is exposed by removing a part of the gate insulating film 5. Then, a source electrode 7 is formed by forming and patterning a metal film on a portion where the source region 4 is exposed. Thereafter, the drain electrode 8 is formed on the main surface of the semiconductor substrate 1 opposite to the main surface on which the drift layer 2 is formed. Through the above steps, the main part of the trench MOSFET made of silicon carbide shown in FIG. 1 is completed.

  Note that the impurity concentration distribution of the n-type drift layer 2 and the impurity concentration distribution of the p-type base region 3 according to the first embodiment are determined by secondary ion mass spectrometry (SIMS) or charged particle activation. It can be measured by an analytical method (CPAA: Charged-Particle Activation Analysis).

<C. Effect>
<C-1. Experimental results>
Next, experimental results of the MOSFET according to the first embodiment will be described. 11 and 12 are diagrams showing the performance of the MOSFET according to the first embodiment. The n-channel MOSFET that is the subject of the experiment has a channel region formed on the (0001) plane. Here, FIG. 11 is an experimental result showing the relationship between the impurity concentration Na (horizontal axis) of the p-type first region 3a included in the MOSFET and the channel mobility μch (vertical axis) of the MOSFET. FIG. 12 shows experimental results showing the relationship between the impurity concentration Na (horizontal axis) of the first region 3a and the threshold voltage Vth (vertical axis) of the MOSFET.

  As shown in FIG. 11, it was confirmed that the channel mobility μch increases as the impurity concentration (acceptor concentration) in the first region 3a decreases. Further, as shown in FIG. 12, it was confirmed that the threshold voltage Vth decreases as the impurity concentration (acceptor concentration) in the first region 3a decreases.

<C-2. Effect>
As described above, according to the trench MOSFET according to the first embodiment, since the impurity concentration of the first region 3a serving as the channel region is relatively low, the impurity scattering is reduced and high mobility is realized. it can. That is, a low on-loss trench MOSFET can be realized. Furthermore, since the second region 3b has a relatively high impurity concentration, punch-through breakdown can be prevented and a high breakdown voltage trench MOSFET can be realized.

  According to the method for manufacturing a trench MOSFET according to the first embodiment, since the first region 3a is formed by diffusion of impurity ions from the second region 3b, even a complicated structure such as a trench MOSFET is used. The base region 3 having the second region 3b having a relatively high concentration and the first region 3a having a relatively low concentration can be easily formed.

  Further, since the MOS interface formed on the sidewall of the trench is formed on the surface of the epitaxially grown first region 3a, it is not affected by etching damage at the time of trench formation. Further, since B diffuses also in the vertical direction, the p-type impurity density is distributed from the high concentration to the low concentration in the base region 3 joined to the drift layer 2 from the second region 3b toward the drift layer 2 side. It becomes the 1st field 3a which has a profile. Therefore, a pn junction in which the impurity density gently changes is formed at the interface between the drift layer 2 and the first region 3a. For this reason, the avalanche resistance of the pn junction is improved, and a high breakdown voltage can be realized.

  By forming the trench MOSFET having the above-described configuration, it is possible to provide a MOSFET made of silicon carbide that has the most excellent pressure resistance in practical use and has the least operating loss when ON. Further, in the trench MOSFET according to the first embodiment, the n-type epitaxial layer 9 formed in the trench 20 becomes p-type due to diffusion of p-type impurities, and thus does not have an accumulation mode structure. Therefore, normally OFF of the MOSFET can be easily realized.

  In the trench MOSFET manufacturing method according to the first embodiment, B is used as the p-type impurity. However, aluminum (Al) or the like may be used, for example. Furthermore, B and Al may be employed at the same time. For example, Al that is relatively difficult to diffuse in silicon carbide and B that is easily diffused may be injected into the second region 3b. After the heat treatment, the Al distribution is almost the same as the distribution after the implantation, and B diffuses in and out, and the distribution changes compared to after the implantation. Therefore, Al and B are distributed in the second region 3b. The diffused B is distributed in the region 3a.

In the channel region, B is diffused and a region having a low impurity concentration is formed, and a gentle pn junction is formed at the interface between the drift layer 2 and the base region 3. In the second region 3b, even if the B concentration decreases after diffusion, a high concentration of Al (1 × 10 ¹⁸ / cm ³ ) remains and is distributed, so that punch-through of the base region 3 can be reliably prevented. . Further, even when an ionic species other than B or Al is employed, the above matters can be easily applied if it is determined whether or not the ionic species are likely to diffuse by heat treatment.

  In the trench type MOSFET manufacturing method according to the first embodiment, the sidewall of the trench 20 is formed to be perpendicular to the semiconductor substrate 1 as shown in FIG. 5, but as shown in FIG. An angle may be attached. FIG. 13 is a cross-sectional view showing another manufacturing process of the trench MOSFET according to the first embodiment.

  Further, in order to suppress an increase in contact resistance between the source electrode 7 and the base region 3, the first region 3a of the base region 3 located between the source electrode 7 and the second region 3b in FIG. May be removed.

Further, as shown in FIG. 14, a region having a high concentration of the second conductivity type impurity may be formed in advance in the surface of the base region in contact with the source electrode 7. FIG. 14 is a diagram showing the configuration of the trench MOSFET when the second conductivity type high concentration region 10 is inserted into the base region 3. The impurity concentration of the high concentration region 10 may be, for example, 1 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²³ / cm ³ or less. The depth of the high concentration region 10 needs not to exceed the depth of the base region 3.

<Embodiment 2>
<A. Configuration>
FIG. 15 is a cross-sectional view showing the configuration of the main part of the trench MOSFET according to the second embodiment. FIG. 15 is a diagram illustrating a cross-sectional structure of one trench MOSFET among a plurality of trench MOSFETs that are continuously arranged in a comb shape or a polygonal shape on a semiconductor substrate 1 and are folded back multiple times. In the trench MOSFET according to the second embodiment, the first region 3 a is disposed between the source region 4 and the gate insulating film 5 along the sidewall of the trench 20. Other configurations are the same as those of the first embodiment shown in FIG. 1, and the same components are denoted by the same reference numerals, and redundant description is omitted.

<B. Manufacturing method>
Next, a method for manufacturing the trench MOSFET according to the second embodiment will be described with reference to FIGS. 16 to 19 are cross-sectional views showing manufacturing steps of the trench MOSFET according to the second embodiment.

  In the first embodiment, the manufacturing method has been described in which the trench 20 is formed after the second region 3b is formed, and the source region 4 is formed after the region corresponding to the first region 3a is epitaxially grown. In the trench MOSFET according to the second embodiment, as shown in FIG. 16, after the formation of the second region 3b, the source region 4 is formed on the surface of the second region 3b. Here, FIG. 16 is a cross-sectional view after forming the source region.

  Next, as shown in FIG. 17, a trench 20 is formed in the source region 4, the second region 3 b, and the drift layer 2. Next, as shown in FIG. 18, the n-type epitaxial layer 9 is formed on the trench 20, the source region 4, and the second region 3b. Next, as shown in FIG. 19, the epitaxial layer 9 other than the trench sidewall is removed by etching or polishing. Since the epitaxial layer 9 formed on the surface of the source region 4 is removed, an increase in the source contact resistance can be prevented.

  Here, the epitaxial layer 9 leaves a portion formed on the side wall of the trench where the channel is formed, and if the portion where the source region 4 is in contact with the source electrode 7 is removed, the other regions are removed even if removed. You don't have to. For example, the trench bottom portion of the epitaxial layer 9 may or may not be removed. FIG. 19 shows a structure in which the epitaxial layer 9 at the bottom of the trench is not removed. Alternatively, the epitaxial layer 9 may be selectively formed only inside the trench by selective growth.

  Through the above manufacturing process, a structure similar to the structure shown in FIG. 7 of Embodiment 1 can be formed. Thereafter, through the same steps as in the first embodiment, the structure of the main part of the trench MOSFET shown in FIG. 15 can be obtained. The detailed manufacturing process is the same as that of the first embodiment, and therefore will be omitted.

<C. Effect>
In the method for manufacturing a trench MOSFET according to the second embodiment, epitaxial growth is performed after all ion implantation steps are completed. Therefore, when epitaxial growth of the epitaxial layer 9 is performed at a temperature necessary for the activation of the implanted ions (for example, 1500 ° C.), the implanted ions are diffused and activated during the formation of the epitaxial layer 9. Can be omitted. As a result, the process can be simplified as compared with the manufacturing method of the trench MOSFET according to the first embodiment.

  In the method for manufacturing a trench MOSFET according to the second embodiment, the second region 3b having a relatively high concentration and the first region 3a having a relatively low concentration can be easily formed as in the first embodiment. it can. In the first region 3a serving as the channel region, impurity scattering is reduced, and high mobility can be realized (realization of low on-loss). Furthermore, punch-through destruction can be prevented in the second region 3b, and a high breakdown voltage can be realized.

  Similarly to the structure of FIG. 14 described in Embodiment 1, a region having a high concentration of the second conductivity type (p-type) impurity may be formed in the surface of the base region in contact with the source region 4. In this case, the element cross-sectional view has a structure shown in FIG.

<Embodiment 3>
<A. Configuration>
The configuration of the trench MOSFET according to the third embodiment is the same as that of the first embodiment shown in FIG.

<B. Manufacturing method>
Next, with reference to FIG. 20, the manufacturing method of the trench type MOSFET according to the third embodiment will be described. FIG. 20 is a cross-sectional view showing the manufacturing process of the trench MOSFET according to the third embodiment.

  In the manufacturing method of the trench MOSFET according to the first and second embodiments, the second region 3b is formed by ion implantation. However, in the third embodiment, the second region 3b is formed by epitaxial growth. That is, after the n-type drift layer 2 is formed, the p-type second region 3b is formed by epitaxial growth. FIG. 20 shows a cross-sectional view after forming the second region 3b.

  For example, Al or B is used as the p-type impurity dopant in the epitaxial growth of the second region 3b. Here, the n-type drift layer 2 and the second region 3b can be formed continuously by switching the dopant source gas during epitaxial growth.

  Subsequent steps are the same as those in the first or second embodiment. That is, the source region may be formed after the trench formation as in the first embodiment, or the trench may be formed after the source region is formed as in the second embodiment.

<C. Effect>
In the manufacturing method of the trench type MOFET according to the third embodiment, since the drift layer 2 and the second region 3b can be formed continuously, the base region 3 is formed by ion implantation as in the first embodiment or the second embodiment. The process can be simplified as compared with the case of forming.

  According to the method for manufacturing a trench MOSFET according to the third embodiment, the second region 3b having a relatively high concentration and the first region 3a having a relatively low concentration are easily formed as in the first embodiment. be able to. And in the 1st field 3a used as a channel field, impurity scattering becomes small and high mobility can be realized (realization of low on loss). Furthermore, punch-through destruction can be prevented in the second region 3b, and a high breakdown voltage can be realized.

3 is a cross-sectional view showing a configuration of a main part of the trench MOSFET according to the first embodiment. FIG. 3 is an enlarged cross-sectional view of the vicinity of a sidewall of a trench of the trench MOSFET according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the trench MOSFET according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the trench MOSFET according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the trench MOSFET according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the trench MOSFET according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the trench MOSFET according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the trench MOSFET according to the first embodiment. FIG. 6 is a diagram for explaining an impurity profile of a first region of the trench MOSFET according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process of the trench MOSFET according to the first embodiment. FIG. FIG. 3 is a diagram showing the performance of the MOSFET according to the first embodiment. FIG. 3 is a diagram showing the performance of the MOSFET according to the first embodiment. 12 is a cross-sectional view showing another manufacturing process of the trench MOSFET according to the first embodiment. FIG. FIG. 6 is a cross-sectional view showing another configuration of the trench MOSFET according to the first embodiment. 6 is a cross-sectional view showing a configuration of a main part of a trench MOSFET according to a second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the trench MOSFET according to the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the trench MOSFET according to the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the trench MOSFET according to the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the trench MOSFET according to the second embodiment. FIG. 12 is a cross-sectional view showing a manufacturing process of the trench MOSFET according to the third embodiment. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Drift layer, 3 Base area | region, 3a 1st area | region, 3b 2nd area | region, 4 Source area | region, 5 Gate insulating film, 6 Gate electrode, 7 Source electrode, 8 Drain electrode, 9 Epitaxial layer, 10 High concentration Layer, 20 trenches.

Claims (6)

Forming a drift layer made of silicon carbide of the first conductivity type on a semiconductor substrate made of silicon carbide;
Forming a second region made of silicon carbide of the second conductivity type on a surface layer portion of the drift layer;
Forming a trench having a bottom in the drift layer through the second region;
Forming an impurity layer made of silicon carbide of the first conductivity type along the sidewall of the groove;
Forming a source region made of silicon carbide of the first conductivity type on the surface layer of the second region so as to be in contact with the impurity layer ;
By diffusing an impurity from said second region to said impurity layer and the drift layer, the realm that in contact with the second region of the impurity layer and the drift layer, first made of silicon carbide of a second conductivity type Forming a region, and forming a base region made of silicon carbide having the first region and the second region;
A method for producing a trench MOSFET, comprising: Said first area, said second direction from region side on the side wall of the groove, the trench MOSFET manufacturing method according to claim 1, characterized in that it has a concentration distribution of the impurity of the second conductivity type. The step of forming the drift layer includes the step of forming the drift layer by epitaxial growth on the semiconductor substrate,
The method of manufacturing a trench MOSFET according to claim 1, wherein the step of forming the second region includes a step of forming the second region by ion implantation in the drift layer . The step of forming the drift layer includes the step of forming the drift layer by epitaxial growth on the semiconductor substrate,
2. The method of manufacturing a trench MOSFET according to claim 1, wherein the step of forming the second region includes a step of forming the second region by epitaxial growth on the drift layer . A drift layer made of silicon carbide of the first conductivity type formed on a semiconductor substrate made of silicon carbide;
A base region made of silicon carbide of the second conductivity type formed in the surface layer portion of the drift layer;
A source region made of silicon carbide of the first conductivity type formed in a surface layer portion of the base region;
A groove formed in the drift layer so that the base region and the source region are in contact with the side wall, and the lower end reaches a region other than the base region and the source region;
With
The base region is
A first region of a second conductivity type formed with a certain width from the side wall of the groove part along the side wall of the groove part,
A second region that is a region other than the first region;
Have
The impurity concentration of the first region is lower than the impurity concentration of the second region,
The base region joined to the drift layer becomes the first region having a profile in which the density of the second conductivity type impurity is distributed from a high concentration to a low concentration from the second region toward the drift layer side. Trench type MOSFE T characterized by the above . 6. The trench type MOSFET according to claim 5, wherein the width of the first region is 2 [ mu] m or less .

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