JP4793437B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device having a trench gate and a method for manufacturing the same.

  In recent years, SiC has attracted attention as a power device material that can provide high electric field breakdown strength. Since the SiC semiconductor device has a high electric field breakdown strength, a large current can be controlled. Therefore, it is expected to be utilized for controlling a hybrid car motor.

  In the SiC semiconductor device, it is effective to increase the channel density in order to pass a larger current. For this reason, MOSFETs having a trench gate structure are adopted and put into practical use in silicon transistors. This trench gate structure is naturally applicable to a SiC semiconductor device, but there is a big problem when applied to SiC. That is, since SiC has a breakdown electric field strength 10 times that of silicon, SiC semiconductor devices are used in a state where a voltage nearly 10 times that of silicon devices is applied. Therefore, there is a problem that an electric field 10 times stronger than that of the silicon device is applied to the gate insulating film formed in the trench that has entered SiC, and the gate insulating film is easily broken at the corner of the trench. When this was calculated by simulation, an electric field of 4.9 MV / cm was concentrated on the gate insulating film in the trench when 650 V was applied to the drain. In order to withstand actual use, it is necessary to make it 3 MV / cm or less, and considering long-term reliability, it is desirable to make it 2 MV / cm or less.

As a solution to such a problem, there is an SiC semiconductor device disclosed in Patent Document 1. In this SiC semiconductor device, the electric field concentration at the bottom of the trench is reduced by designing the bottom of the trench gate to be thicker than the side surface. Specifically, a (1120) plane trench gate structure is fabricated using a 4H—SiC (000-1) c plane substrate. Thus, when a gate insulating film is formed by thermal oxidation in a trench in which a trench side surface is an a surface and a bottom surface is a c surface using a c surface substrate, the oxidation rate of the c surface is 5 times that of the a surface. The oxide film at the bottom of the trench can be five times as thick as the side surface. Thereby, it is possible to alleviate electric field concentration at the bottom of the trench.
JP 9-199724 A

  However, in the structure in which the gate insulating film is thick at the bottom of the trench as described above, for example, when the film thickness on the side surface of the trench is set to 40 nm and the film thickness at the bottom of the trench is designed to 200 nm, calculation is performed by simulation. In this case, it was confirmed that the electric field concentration of the gate insulating film in the trench could be reduced to 3.9 MV / cm. However, it was not yet sufficient, and it was found that further electric field relaxation was necessary.

  Therefore, the present inventors have previously proposed a method for the longitudinal direction of the trench gate as a SiC semiconductor device having a structure capable of further reducing the electric field and capable of preventing a variation in product characteristics and improving the yield. An application has been filed for a structure in which a p-type deep layer extends in the linear direction and in a direction parallel to the substrate plane (see Japanese Patent Application No. 2008-31704).

  In this earlier application, as the SiC semiconductor device, an accumulation type MOSFET in which an n-type channel layer is formed around the side including the side surface of the trench gate and an inversion type MOSFET in which the n-type channel layer is not formed are proposed. Among these storage MOSFETs, an n-type channel is formed by epitaxially growing an n-type layer on the surface of a trench for forming a trench gate. The on-resistance of the MOSFET may also vary in the surface.

  In consideration of this, in the case of an inversion type MOSFET, there is no need to form an n-type channel layer by epitaxial growth, so there is no fear of in-plane variation in the on-resistance of the MOSFET.

However, in the case of an inversion type MOSFET, the p-type base region has one configuration that determines the breakdown voltage. That is, in the case of inverting the MOSFET, basically along the trench n in trench gate structure unit ^- Pressure depletion layers extending -type drift layer ^- n from depletion and p-type deep layer extending -type drift layer side Is decided. However, at a position away from the trench gate structure, the depletion layer extends to the n ⁻ type drift layer between the p type deep layers, and the depletion layer extending from the p type base region to the n ⁻ type drift layer reduces the breakdown voltage. It will be decided.

For this reason, if the impurity concentration of the p-type base region is high, a depletion layer extending from the p-type base region to the n ⁻ -type drift layer becomes wide. For example, the p-type impurity concentration of the p-type base region is about 1 × 10 ¹⁷ cm ^−3. When the concentration is high, punch-through does not occur at the time of reverse bias, so that the breakdown voltage can be improved. On the other hand, the p-type base region is inverted when the channel region is formed. Therefore, if the p-type impurity concentration of the p-type base region is high, the channel mobility is lowered and the on-resistance is increased. On the other hand, when the p-type impurity concentration of the p-type base region is reduced, for example, when the p-type impurity concentration of the p-type base region is lowered to about 1 × 10 ¹⁶ cm ⁻³ , the channel mobility increases and the on-resistance However, the depletion layer extending from the p-type base region to the n ⁻ -type drift layer becomes narrow and punch-through occurs at the time of reverse bias, causing a reduction in breakdown voltage.

  SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an inversion trench gate structure SiC semiconductor device capable of reducing both on-resistance and improving breakdown voltage, and a method for manufacturing the same.

In order to achieve the above object, according to the first aspect of the present invention, in the SiC semiconductor device including the inversion type MOSFET, the SiC semiconductor device is disposed below the base region (3) and deeper than the trench (7). The second conductivity type deep layer (10) extending in the direction intersecting the longitudinal direction of the trench (7) and parallel to the substrate plane is separated from the side surface of the trench (7). And a second conductivity type body layer (6) that is deeper than the source region (4) and at a higher concentration than the base region (3), and is located above the deep layer (10). In addition, a base region (3) and a source region (4) are formed, and current flows between the source electrode (11) and the drain electrode (13) through the channel region even at the position where the deep layer (10) is formed. This It is characterized in.

  As described above, since the body layer (6) having a higher concentration than the base region (3) is provided in addition to the deep layer (10), the drift layer is formed even at a position away from the trench gate structure. (2) The amount of elongation of the depletion layer extending to the side can be increased. For this reason, most of the depletion layer can be extended to the drift layer (2) side. Therefore, even at a position where the deep layer (10) is not formed, a high breakdown voltage can be provided at a position away from the trench gate structure.

  Moreover, since the breakdown voltage can be secured by providing the body layer (6), the concentration of the base region (3) can be reduced. For this reason, the base region (3) can be easily inverted to form a wide channel region, and the channel mobility is increased. As a result, it is possible to obtain an SiC semiconductor device having an inverted trench gate structure capable of both reducing the on-resistance and improving the breakdown voltage.

  In the invention according to claim 2, the width of the deep layer is 1.5 μm, the distance between the deep layers is 2.0 μm, and the distance from the side surface of the trench (7) to the body layer (6) is 0.00. It is characterized by being 4 to 0.9 μm apart.

  In this way, the base region (3) does not become difficult to be reversed in the body layer (6) even if the mask displacement at the time of manufacture is taken into consideration. For this reason, it becomes possible to aim at reduction of on-resistance compared with the case where the body layer (6) is not provided.

For example, as described in claim 3, the concentration of the second conductivity type impurity in the base region (3) is 5.0 × 10 ¹⁵ to 5.0 × 10 ¹⁶ / cm ³ , and the second concentration of the body layer (6) is set. The concentration of the conductive impurity can be set to 1.0 × 10 ^{18 to} 1.0 × 10 ²⁰ / cm ³ .

  The SiC semiconductor device as described above is manufactured by, for example, a manufacturing method shown below. For example, as described in claim 4, the first conductivity type silicon carbide having a lower impurity concentration than the substrate (1) on the first or second conductivity type substrate (1) made of silicon carbide. A step of forming a drift layer (2) comprising: a step of forming a deep layer (10) of the second conductivity type on the surface layer of the drift layer (2) so as to extend in one direction; and a deep layer A step of forming a base region (3) made of silicon carbide of the second conductivity type on (10) and the drift layer (2), and a surface layer portion of the base region (3) in the base region (3), Forming a source region (4) composed of silicon carbide of the first conductivity type higher in concentration than the drift layer (2), and ionizing second conductivity type impurities deeper than the source region (4); By implantation, the second conductivity type having a higher concentration than the base region (3). In the step of forming the body region (6) made of silicon carbide at a predetermined distance, and in the place where the body region (6) is separated from the surface of the source region (4), the base region (3) In a direction intersecting with the extending direction of the deep layer (10) and parallel to the substrate plane so as to reach the drift layer (2) and become shallower than the deep layer (10). A step of forming a trench (7) in the longitudinal direction, a step of forming a gate insulating film (8) on the surface of the trench (7), and a gate on the gate insulating film (8) in the trench (7). A step of forming an electrode (9), a step of forming a source electrode (11) electrically connected to the source region (4) and the base region (3), and a drain electrode ( And 13) forming a step. It by the process, can be produced inversion type SiC semiconductor device shown in claim 1.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
FIG. 1 is a perspective sectional view of a MOSFET having an inverted trench gate structure according to the present embodiment. This figure corresponds to the extracted one cell of the MOSFET. Although only one MOSFET cell is shown in the figure, MOSFETs having the same structure as the MOSFET shown in FIG. 1 are arranged so as to be adjacent to each other in a plurality of rows. 2A to 2D are cross-sectional views of the MOSFET of FIG. 1, and FIG. 2-A is a cross-sectional view taken along line AA in FIG. 1 in parallel with the xz plane. 2-b is a section taken along line BB in FIG. 1 when parallel to the xz plane, and FIG. 2-c is a section taken along line CC along line yz in FIG. 2D is a cross section when cut in parallel with the yz plane along the line DD in FIG.

The MOSFET shown in FIGS. 1 and 2-a to 2-d has an n ⁺ -type substrate 1 made of SiC having an n-type impurity concentration of, for example, phosphorus of 1.0 × 10 ¹⁹ / cm ³ and a thickness of about 300 μm. It is used as a semiconductor substrate, and the surface of the n ⁺ -type substrate 1 is made of SiC having an n-type impurity concentration such as phosphorus of 3.0 to 7.0 × 10 ¹⁵ / cm ³ and a thickness of about 10 to ¹⁵ μm. An n ⁻ type drift layer 2 is formed. The impurity concentration of the n ⁻ type drift layer 2 may be constant in the depth direction, but the concentration distribution is inclined, and the n ⁺ type substrate 1 side of the n ⁻ type drift layer 2 is n ⁺ type. It is preferable that the concentration be higher than that on the side away from the substrate 1. For example, the impurity concentration in the portion of about 3 to 5 μm from the surface of the n ⁺ -type substrate 1 in the n ⁻ -type drift layer 2 is preferably higher than that in other portions by about 2.0 × 10 ¹⁵ / cm ³ . In this way, since the internal resistance of the n ⁻ type drift layer 2 can be reduced, the on-resistance can be reduced.

A p-type base region 3 is formed in the surface layer portion of the n ⁻ -type drift layer 2, and an n ⁺ -type source region 4 and a p ⁺ -type contact layer 5 are formed in an upper layer portion of the p-type base region 3. ing. Further, in the p-type base region 3, a p ⁺ -type body layer 6 is formed at a position deeper than the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5.

The p-type base region 3 has a p-type impurity concentration such as boron or aluminum of, for example, 5.0 × 10 ^{15 to} 5.0 × 10 ¹⁶ / cm ³ and a thickness of about 2.0 μm. The n ⁺ -type source region 4 is configured such that the n-type impurity concentration (surface concentration) such as phosphorus in the surface layer portion is, for example, 1.0 × 10 ²¹ / cm ³ and the thickness is about 0.3 μm. The p ⁺ -type contact layer 5 has a p-type impurity concentration (surface concentration) such as boron or aluminum in the surface layer portion of, for example, 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm. The p ⁺ type body layer 6 has a p-type impurity concentration such as boron or aluminum of, for example, 1.0 × 10 ^{18 to} 1.0 × 10 ²⁰ / cm ³ and a thickness of about 0.7 to 1.1 μm. Has been.

The n ⁺ -type source region 4 is disposed on both sides of a trench gate structure described later, and the p ⁺ -type contact layer 5 is provided on the opposite side of the trench gate structure with the n ⁺ -type source region 4 interposed therebetween. The p ⁺ type body layer 6 is disposed on both sides of the trench gate structure, and is separated from the side surface of the trench 7 for forming the trench gate structure by a predetermined distance, for example, about 0.4 to 0.9 μm. Is formed.

A trench 7 is formed so as to penetrate the p-type base region 3 and the n ⁺ -type source region 4 and reach the n ⁻ -type drift layer 2. The trench 7 is formed to have a width of, for example, 1.4 to 2.0 μm and a depth of 2.0 μm or more (for example, 2.4 μm). The p-type base region 3 and the n ⁺ -type source region 4 are arranged so as to be in contact with the side surface of the trench 7.

  Further, the surface of the trench 7 is covered with a gate oxide film 8, and the inside of the trench 7 is filled with the gate electrode 9 made of doped Poly-Si formed on the surface of the gate oxide film 8. Yes. The gate oxide film 8 is formed by thermally oxidizing the inner wall surface of the trench 7, and the thickness of the gate oxide film 8 is, for example, about 100 nm on both the side surface side and the bottom side of the trench 7.

In this way, a trench gate structure is configured. This trench gate structure is extended with the y direction in FIG. 1 as the longitudinal direction. A plurality of trench gate structures are arranged in parallel in the x direction in FIG. Further, the above-described n ⁺ type source region 4, p ⁺ type contact layer 5 and p type body layer 6 are also extended along the longitudinal direction of the trench gate structure.

Further, in the n ⁻ type drift layer 2 below the p-type base region 3, the normal direction to the portion of the side surface of the trench 7 in the trench gate structure where the channel region is formed (the x direction in FIG. 1). That is, the p-type deep layer 10 extending in the direction perpendicular to the longitudinal direction of the trench 7 is provided. The p-type deep layer 10 is deeper than the bottom of the trench 7, and the depth from the surface of the n ⁻ -type drift layer 2 is about 2.6 to 3.0 μm (from the bottom of the p-type base region 3). The depth is set to 0.6 to 1.0 μm, for example. Further, the width of the p-type deep layer 10 (dimension in the y direction in FIG. 1) is 0.6 to 1.5 μm, which is 1.5 μm in this embodiment. The p-type impurity concentration in the p-type deep layer 10 such as boron or aluminum is, for example, 1.0 × 10 ¹⁷ / cm ^{3 to} 1.0 × 10 ¹⁹ / cm ³ . A plurality of the p-type deep layers 10 are arranged in parallel along the longitudinal direction of the trench gate structure, and the interval between the adjacent p-type deep layers 10 is, for example, 1.5 to 3 μm. In this case, the thickness is set to 2.0 μm.

A source electrode 11 and a gate wiring (not shown) are formed on the surface of the n ⁺ type source region 4 and the p ⁺ type contact layer 5 and the surface of the gate electrode 9. The source electrode 11 and the gate wiring are composed of a plurality of metals (for example, Ni / Al, etc.), and at least n-type SiC (specifically, the n ⁺ -type source region 4 and the gate electrode 9 in the case of n doping) The portion in contact with n-type SiC is made of a metal capable of ohmic contact with n-type SiC, and the portion in contact with at least p-type SiC (specifically, p ⁺ -type contact layer 5 or gate electrode 9 in the case of p-doping) is p-type. It is made of a metal capable of ohmic contact with SiC. The source electrode 11 and the gate wiring are electrically insulated by being formed on the interlayer insulating film 12, and the source electrode 11 is connected to the n ⁺ -type source region through the contact hole formed in the interlayer insulating film 12. 4 and the p ⁺ -type contact layer 5 are in electrical contact, and the gate wiring is in electrical contact with the gate electrode 9.

Then, on the back side of the n ⁺ -type substrate 1 n ⁺ -type substrate 1 and electrically connected to the drain electrode 13 are formed. With such a structure, an n-channel inversion type MOSFET having a trench gate structure is formed.

  Such an inverted MOSFET having a trench gate structure operates as follows.

First, in the state before the gate voltage is applied to the gate electrode 9, the channel region is not formed in the portion of the p-type base region 3 located on the side surface of the trench 7. For this reason, even if a positive voltage is applied to the drain electrode 13, electrons cannot move due to the PNP junction structure formed by the n ⁻ type drift layer 2, the p type base region 3, and the n ⁺ type source region 4. No current flows between the drain electrode 13.

Next, when off (gate voltage = 0 V, drain voltage = 650 V, source voltage = 0 V), since a reverse bias is applied even if a voltage is applied to the drain electrode 13, the p-type base region 3 and the p-type deep layer 10 are used. And the n ⁻ type drift layer 2 and between the trench gate structure and the n ⁻ type drift layer 2, the depletion layer spreads. At this time, if the concentration of the p-type base region 3 is low, the amount of extension of the depletion layer spreading toward the n ⁻ -type drift layer 2 side is reduced.

However, in the present embodiment, since the p ⁺ type body layer 6 having a higher concentration than the p type base region 3 is formed, the extension amount of the depletion layer spreading toward the n ⁻ type drift layer 2 side is p type base. More than the region 3 alone. Therefore, in addition to the depletion layer extending between the p-type deep layer 10 and the n ⁻ -type drift layer 2 and between the trench gate structure and the n ⁻ -type drift layer 2, the p-type base region 3 (p ⁺ -type body layer) 6) and the depletion layer extending between the n ⁻ type drift layer 2 can prevent punch-through. Therefore, the breakdown voltage can be improved by forming the p ⁺ type body layer 6 having a higher concentration than the p type base region 3.

Note that since the gate voltage is 0 V, an electric field is also applied between the drain and the gate. For this reason, electric field concentration can also occur at the bottom of the gate oxide film 8. However, since the p-type deep layer 10 is deeper than the trench 7, the depletion layer at the PN junction between the p-type deep layer 10 and the n ⁻ -type drift layer 2 is on the n ⁻ -type drift layer 2 side. As a result, the high voltage due to the influence of the drain voltage hardly enters the gate oxide film 8. In particular, if the impurity concentration of the p-type deep layer 10 is higher than that of the p-type base region 3, the amount of depletion layer extending toward the n ⁻ -type drift layer 2 becomes larger. As a result, the electric field concentration in the gate oxide film 8, particularly the electric field concentration at the bottom of the trench 7 in the gate oxide film 8 can be relaxed, and the gate oxide film 8 is prevented from being destroyed. Is possible.

On the other hand, when ON (gate voltage = 20 V, drain voltage = 1 V, source voltage = 0 V), 20 V is applied as the gate voltage to the gate electrode 9, so that the p-type base region 3 is inverted on the side surface of the trench 7. Thus, a channel region is formed. Therefore, electrons injected from the source electrode 11 reach the n ⁻ type drift layer 2 after passing through the channel region in the p type base region 3 from the n ⁺ type source region 4. As a result, a current can flow between the source electrode 11 and the drain electrode 13.

At this time, in the present embodiment, since the p ⁺ type body layer 6 is provided to reduce the impurity concentration of the p type base region 3, the p type base region 3 can be easily inverted to form a wide channel region. Enables channel mobility. Further, since the p ⁺ type body layer 6 is formed at a position away from the trench 7 in the p type base region 3, the p type base region 3 is not easily inverted due to the influence of the p ⁺ type body layer 6. There is nothing. Therefore, it is possible to reduce the on-resistance as compared with the case where the p ⁺ type body layer 6 is not provided.

For example, when a p-type base region 3 has a breakdown voltage in a MOSFET that does not include the p ⁺ -type body layer 6, the p-type impurity concentration of the p-type base region 3 needs to be about 1 × 10 ¹⁷ / cm ^3. Therefore, the channel mobility was as low as 120 cm ² / V · s, and as a result, the on-resistance was 5.1 mΩ · cm ² . On the other hand, when the p ⁺ type body layer 6 is provided as in the present embodiment, the p type impurity concentration of the p type base region 3 can be set to about 1 × 10 ¹⁶ / cm ³ , for example. In that case, the channel mobility becomes as high as 210 cm ² / V · s, and the on-resistance can be reduced to 3.5 mΩ · cm ² .

As a reference, the operation in the off state was confirmed by simulation. FIG. 3 is a diagram showing the result of examining the equipotential line distribution in the cross section (corresponding to the DD cross section of FIG. 1) obtained by cutting the p-type deep layer 10 in the direction perpendicular to the longitudinal direction as shown on the left side of the drawing. is there. Also, FIG. 4 shows the equipotential line distribution and current density when the p ⁺ -type body layer 6 is not formed and when the p ⁺ -type body layer 6 is not formed in the MOSFET having the inverted trench gate structure provided with the p-type deep layer 10. It is the figure which showed distribution. Note that the equipotential distribution and current density distribution in FIG. 4 are obtained by examining the distribution in the normal direction of the side surface of the trench 7 between the p-type deep layers 10.

For example, when the impurity concentration of the p-type base region 3 is about twice the impurity concentration of the n ⁻ -type drift layer 2, if neither the p ⁺ -type body layer 6 nor the p-type deep layer 10 is present, the n ⁻ -type If the depletion layer extends 4 μm on the drift layer 2 side, the depletion layer extends 2 μm on the p-type base region 3 side. In this case, it is easy to punch through.

On the other hand, when the p-type deep layer 10 is provided, the depletion layer also extends from the p-type deep layer 10. For example, when the impurity concentration of the p-type deep layer 10 is about 100 times the impurity concentration of the n ⁻ -type drift layer 2, the depletion layer almost extends to the n ⁻ -type drift layer 2 side. For this reason, it is possible to provide a high breakdown voltage as can be confirmed from the equipotential line distribution below the p-type deep layer 10 in FIG.

However, as can be seen from both side portions of the p-type deep layer 10 in FIG. 3 and the equipotential line distribution in FIG. 4, in the portion where the p-type deep layer 10 is not formed (between the p-type deep layers 10), If the p ⁺ type body layer 6 is not formed, the amount of depletion layer extending to the n ⁻ type drift layer 2 is small, so that a high breakdown voltage cannot be provided as can be confirmed from the equipotential line distribution. Further, since the depletion layer extends from the trench 7 in the trench gate structure based on the work function difference between the gate oxide film 8 and SiC, a breakdown voltage can be provided in the vicinity of the trench gate structure, but it is separated from it. It becomes impossible to give pressure resistance at the position. That is, punch-through cannot be prevented only by the depletion layer extending from the p-type deep layer 10 and the trench gate structure to the n ⁻ -type drift layer 2 side. For this reason, as shown in the current density distribution in FIG. 4, a punch-through current flows.

However, in the case of this embodiment, since the p ⁺ type body layer 6 is provided in addition to the p type deep layer 10, the n ⁻ type drift layer 2 side is also provided at a position away from the trench gate structure. The amount of depletion layer extending to For example, since the impurity concentration of the p ⁺ type body layer 6 can be about 1000 times the impurity concentration of the n ⁻ type drift layer 2, most of the depletion layer can extend to the n ⁻ type drift layer 2 side. Therefore, as can be seen from the equipotential line distribution in FIG. 4, it is possible to provide a high breakdown voltage at a position away from the trench gate structure even at a position where the p-type deep layer 10 is not formed. According to experiments, it has been confirmed that a high breakdown voltage of 1200 V or more can be achieved.

Thus, in addition to the p-type deep layer 10 and the depletion layer extending from the trench gate structure to the n ⁻ -type drift layer 2 side, the p ⁺ -type body layer 6 and the p-type base region 3 are moved to the n ⁻ -type drift layer 2 side. Due to the extending depletion layer, a high breakdown voltage can be provided not only in the vicinity of the trench gate structure and the position where the p-type deep layer 10 is formed, but also in a position away from the trench gate structure. Further, punch-through can be prevented, and it is possible to prevent the punch-through current from flowing as can be seen from the current density distribution of FIG.

Note that, when the p-type deep layer 10 is formed in the normal direction to the portion where the channel region is formed on the side surface of the trench 7 in the trench gate structure as in the present embodiment, the p-type deep layer 10 is formed. The channel region is not formed on the side surface of the trench 7 having the trench gate structure at a certain position. For this reason, it may be a cause of an increase in on-resistance, but the increase in on-resistance is not large and can be adjusted according to the width and interval of the p-type deep layer 10, so that it does not cause a problem. . In addition, since the p ⁺ type body layer 6 is provided in the structure in which the p type deep layer 10 is formed as in the present embodiment, the p type deep layer 10 can be spaced apart. It becomes possible to contribute to resistance reduction.

  Next, a method for manufacturing the MOSFET having the inverted trench gate structure shown in FIG. 1 will be described. 5 to 6 are cross-sectional views showing a manufacturing process of the MOSFET having the inverted trench gate structure shown in FIG. 5 and 6, the left side is a cross-sectional view taken along line AA in FIG. 1 in parallel with the xz plane (the location corresponding to FIG. 2-a), and the right side is D- in FIG. A cross-sectional view taken along line D and parallel to the yz plane (a place corresponding to FIG. 2D) is shown. Hereinafter, description will be given with reference to these drawings.

[Step shown in FIG. 5A]
First, an n ⁺ -type substrate 1 having an n-type impurity concentration such as phosphorus of 1.0 × 10 ¹⁹ / cm ³ and a thickness of about 300 μm is prepared. After forming the drain electrode 13 on the back side of the n ⁺ -type substrate 1, the thickness of n-type impurity concentration of, for example, 3.0~7.0 × 10 ¹⁵ / cm ³ of phosphorus or the like on the surface of the n ⁺ -type substrate 1 An n ⁻ type drift layer 2 made of SiC having a thickness of about 15 μm is epitaxially grown.

[Step shown in FIG. 5B]
After the mask 20 made of LTO or the like is formed on the surface of the n ⁻ type drift layer 2, the mask 20 is opened in a region where the p-type deep layer 10 is to be formed through a photolithography process. Then, ion implantation and activation of a p-type impurity (for example, boron or aluminum) is performed on the mask 20 so that, for example, the boron or aluminum concentration is 1.0 × 10 ¹⁷ / cm ^{3 to} 1.0 × 10 ¹⁹ / cm. ^3. p-type having a thickness of about 0.6 to 1.0 μm, a width of about 0.6 to 1.5 μm (for example, 1.5 μm), and a distance of 2.0 to 3.0 μm (for example, 2.0 μm) The deep layer 10 is formed. Thereafter, the mask 20 is removed.

[Step shown in FIG. 5 (c)]
A p-type impurity layer having a p-type impurity concentration such as boron or aluminum of about 5.0 × 10 ^{15 to} 5.0 × 10 ¹⁶ / cm ³ and a thickness of about 2.0 μm is formed on the surface of the n ⁻ -type drift layer 2. Is grown epitaxially to form the p-type base region 3.

[Step shown in FIG. 6A]
After forming a mask (not shown) made of, for example, LTO on the p-type base region 3, a photolithography process is performed, and the p ⁺ -type body layer 6 is formed on the region where the p ⁺ -type body layer 6 is to be formed. In consideration of the width and the distance from the side surface of the trench 7 to the p ⁺ type body layer 6, the mask is opened at a predetermined distance. Thereafter, p-type impurities (for example, boron or aluminum) are ion-implanted.

Subsequently, after forming a mask (not shown) made of, for example, LTO on the p-type base region 3, a mask is formed on the formation region of the n ⁺ -type source region 4 through a photolithography process. Open. Thereafter, n-type impurities (for example, nitrogen) are ion-implanted.

Further, after removing the previously used mask, a mask (not shown) is formed again, and the mask is opened on a region where the p ⁺ -type contact layer 5 is to be formed through a photolithography process. Thereafter, a p-type impurity (for example, nitrogen) is ion-implanted.

Then, by activating the implanted ions, the n ⁺ -type source region 4 having an n-type impurity concentration (surface concentration) such as phosphorus of 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm is formed. At the same time, the p ⁺ -type contact layer 5 having a p-type impurity concentration (surface concentration) such as boron or aluminum of 1.0 × 10 ²¹ / cm ³ and a thickness of about 0.3 μm is formed. Further, a p ⁺ type body layer 6 having a p-type impurity concentration such as boron or aluminum of about 1.0 × 10 ^{18 to} 1.0 × 10 ²⁰ / cm ³ and a thickness of about 0.7 to 1.1 μm is formed. . Thereafter, the mask is removed.

[Step shown in FIG. 6B]
After forming an etching mask (not shown) on the p-type base region 3, the n ⁺ -type source region 4 and the p ⁺ -type contact layer 5, a region where the trench 7 is to be formed, specifically, the p ⁺ -type body layer 6 is formed. An etching mask is opened at a place where they are separated from each other. Then, after performing anisotropic etching using an etching mask, the trench 7 is formed by performing isotropic etching or sacrificial oxidation process as necessary. Thereby, trench 7 is formed so that the distance to p ⁺ type body layer 6 is 0.4 to 0.9 μm. Thereafter, the etching mask is removed.

Here, mask misalignment occurs in the step of forming the trench 7 and the ion implantation step for forming the p ⁺ type body layer 6 described above, so that the formation positional relationship between the p ⁺ type body layer 6 and the trench 7 is shifted. there is a possibility. Specifically, the maximum value of the positional deviation due to mask misalignment considering both processes is expected to be about 0.2 μm, and the distance between the p ⁺ type body layer 6 and the trench gate structure may be shifted by the maximum value. There is.

On the other hand, to prevent the p-type base region 3 from being inverted due to the influence of the impurity concentration of the p ⁺ -type body layer 6 and the channel mobility from being lowered, the p ⁺ -type body layer 6 is provided with the trench 7. Must be separated from the side surface by 0.1 μm or more.

However, in this embodiment, since the distance from the side surface of the trench 7 to the p ⁺ type body layer 6 is 0.4 μm or more, even if mask misalignment occurs, the distance does not become less than 0.2 μm. . Therefore, it is possible to prevent the p-type base region 3 from being inverted due to the influence of the impurity concentration of the p ⁺ -type body layer 6 and the channel mobility from being lowered.

Although it is conceivable to form the p ⁺ type body layer 6 without forming the p type deep layer 10, in that case, the breakdown voltage is given only by the trench gate structure and the depletion layer extending from the p ⁺ type body layer 6. Will have to. For this reason, if the p ⁺ type body layer 6 is separated from the trench gate structure, the depletion layer extending from the trench gate structure and the p ⁺ type body layer 6 cannot provide a withstand voltage between them. There is a limit to the distance that the p ⁺ -type body layer 6 can be separated from the side surface. In the experiment, it has been confirmed that the distance is about 0.3 μm. However, even if the distance from the side surface of the trench 7 to the p ⁺ type body layer 6 is set to 0.3 μm, the distance varies between 0.1 and 0.5 μm due to the mask displacement. Therefore, if also the p-type base region 3 is the channel mobility or longer can be inverted affected by the impurity concentration of the p ⁺ -type body layer 6 may become low, from the trench gate structure and the p ⁺ -type body layer 6 In some cases, the extending depletion layer cannot provide a withstand voltage therebetween. Therefore, it is important to have a structure including both the p ⁺ type body layer 6 and the p type deep layer 10 as in the MOSFET of this embodiment.

[Step shown in FIG. 6 (c)]
By performing the gate oxide film forming step, the gate oxide film 8 is formed on the entire surface of the substrate including the inside of the trench 7. Specifically, the gate oxide film 8 is formed by gate oxidation (thermal oxidation) by a pyrogenic method using a wet atmosphere.

  Subsequently, after a polysilicon layer doped with n-type impurities is formed on the surface of the gate oxide film 8 at a temperature of, for example, about 440 nm at a temperature of 600 ° C., an etch back process or the like is performed, whereby the gate oxide film is formed in the trench 7. 8 and the gate electrode 9 are left.

The subsequent steps are the same as in the prior art and are not shown. However, after the interlayer insulating film 12 is formed, the interlayer insulating film is patterned to contact the n ⁺ type source region 4 and the p ⁺ type contact layer 5. While forming a hole, the contact hole connected with the gate electrode 9 is formed in another cross section. Subsequently, after depositing an electrode material so as to fill the contact hole, the source electrode 11 and the gate wiring are formed by patterning the electrode material. Thereby, the MOSFET shown in FIG. 1 is completed.

  According to the manufacturing method described above, since the p-type deep layer 10 is not formed by trench embedding in which a p-type layer is epitaxially grown and buried by digging a trench, the planarization step after filling the trench Therefore, it is possible to prevent the occurrence of crystal defects.

The p-type deep layer 10 can also be formed by ion implantation from the surface of the p-type base region 3, but ion implantation for forming the p-type deep layer 10 is performed from the surface of the n ⁻ -type drift layer 2. Like to do. For this reason, it is not necessary to form the p-type deep layer 10 by high-speed ion implantation with high energy, and it becomes possible to suppress generation of defects due to high-speed ion implantation.

  Further, when the longitudinal direction of the trench 7 and the longitudinal direction of the p-type deep layer 10 are made parallel, the device characteristics are affected if the distance between them is not constant. The alignment of the mask used and the mask used when forming the p-type deep layer 10 is important. However, since a certain amount of mask displacement inevitably occurs, the influence of device characteristics due to mask displacement cannot be completely eliminated. On the other hand, according to the SiC semiconductor device of the present embodiment, the longitudinal direction of the trench 7 and the longitudinal direction of the p-type deep layer 10 are perpendicular to each other. There is no impact. As a result, variation in product characteristics can be prevented and yield can be improved. Therefore, by adopting the structure as in the present embodiment, it is possible to provide a SiC semiconductor device having a structure in which variation in product characteristics can be prevented and yield can be improved.

(Other embodiments)
(1) In the first embodiment, the distance from the side surface of the trench 7 constituting the trench gate structure to the p-type body layer 6 is set to 0.4 to 0.9 μm. This is selected as a distance that can achieve both improvement in breakdown voltage and reduction in on-resistance when the width of the p-type deep layer 10 is 1.5 μm and the interval is 2.0 μm. The distance to the layer 6 varies depending on the width and interval of the p-type deep layer 10. 7 and 8 show a trench gate structure when the width of the p-type deep layer 10 is 1.5 μm and the interval is 2.0 μm, and when the width is 1.5 and the interval is 3.0 μm. 6 is a graph showing the results of examining the breakdown voltage [V] and the on-resistance [mΩ · cm ² ] when the distance from the side surface of the trench 7 to the p-type body layer 6 is changed.

When the width of the p-type deep layer 10 is 1.5 μm and the interval is 2.0 μm, as shown in FIG. 7, in order to obtain a withstand voltage of 1200 V or more, the side surface of the trench 7 to the p-type body layer 6 can be obtained. The distance may be 0.9 μm or less. As shown in FIG. 8, the distance from the side surface of the trench 7 to the p-type body layer 6 is 0 so that the on-resistance is about 4 mΩ · cm ^2. It is sufficient if it is 4 μm or more.

On the other hand, when the width of the p-type deep layer 10 is 1.5 μm and the interval is 3.0 μm, the p-type body layer 6 is formed from the side surface of the trench 7 in order to obtain a breakdown voltage of 1200 V or more as shown in FIG. The distance from the side surface of the trench 7 to the p-type body layer 6 can be reduced so that the on-resistance is about 4 mΩ · cm ² as shown in FIG. May be 0.4 μm or more.

  Thus, by changing the distance from the side surface of the trench 7 to the p-type body layer 6 according to the width and interval of the p-type body layer 10, it is possible to achieve both improvement in breakdown voltage and reduction in on-resistance. is there.

  (2) In the first embodiment, an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the conductivity type of each component is reversed. The present invention can also be applied to p-channel type MOSFETs. In the above description, a MOSFET having a trench gate structure has been described as an example. However, the present invention can also be applied to an IGBT in which a MOSFET is incorporated in a gate portion as a similar trench gate structure. The IGBT only changes the conductivity type of the substrate 1 from the n-type to the p-type with respect to the first embodiment, and the other structure and manufacturing method are the same as those of the first embodiment.

(3) In the first embodiment, the p-type base region 3, the n ⁺ -type source region 4 and the p ⁺ -type body layer 6 are formed before the trench 7 is formed, but the p-type base is formed after the trench 7 is formed. The region 3, the n ⁺ -type source region 4, the p ⁺ -type body layer 6 and the like may be formed by ion implantation.

  (4) The structure shown in the first embodiment is merely an example, and settings can be changed as appropriate. For example, the gate oxide film 8 formed by thermal oxidation has been described as an example of the gate insulating film, but may include an oxide film or nitride film that is not thermally oxidized. The drain electrode 13 may be formed after the source electrode 11 is formed.

  (5) In the first embodiment, the p-type deep layer 10 extends in the normal direction of the side surface of the trench 7. However, the p-type deep layer 10 is inclined in one direction with respect to the side surface of the trench 7. A structure in which a plurality of p-type deep layers 10 inclined in one direction with respect to the normal direction of the side surface of the trench 7 are arranged in a stripe shape and p is inclined in the opposite direction. A plurality of the deep mold layers 10 may be arranged in a stripe shape, and each stripe may intersect to form a lattice shape. That is, it is sufficient that the longitudinal direction of the p-type deep layer 10 intersects at least the longitudinal direction of the trench 7.

(6) In the first embodiment, the case where the p ⁺ type body layer 6 is deeper than the n ⁺ type source region 4 and shallower than the p type base region 3 is taken as an example. It may be deeper than the base region 3. Further, the p ⁺ type body layer 6 may not be in contact with the p ⁺ type contact layer 5.

  (7) In addition, when indicating the orientation of a crystal, a bar (-) should be attached above a desired number, but since there is a limitation on expression based on a personal computer application, in this specification , And a bar before the desired number.

1 is a perspective sectional view of a MOSFET having an inverted trench gate structure according to a first embodiment of the present invention. It is AA sectional drawing of FIG. It is BB sectional drawing of FIG. It is CC sectional drawing of FIG. It is DD sectional drawing of FIG. It is a figure which shows the result of having investigated equipotential line distribution in the cross section which cut | disconnected the p-type deep layer 10 in the orthogonal | vertical direction with respect to the longitudinal direction. In the MOSFET of the inverted trench gate structure provided with the p-type deep layer 10, the equipotential line distribution and the current density distribution when the p ⁺ -type body layer 6 is formed and when not formed are shown. is there. FIG. 6 is a cross-sectional view showing a manufacturing process of the MOSFET having the inverted trench gate structure shown in FIG. 1. FIG. 6 is a cross-sectional view showing a manufacturing process of the MOSFET having the inverted trench gate structure following FIG. 5. It is a graph which shows the result of having investigated withstand voltage [V] when changing the distance from the side surface of the trench 7 to the p-type body layer 6 by changing the width and interval of the p-type deep layer 10. It is a graph which shows the result of having investigated ON resistance [mohm * cm < ² >] when changing the distance from the side surface of the trench 7 to the p-type body layer 6 by changing the width | variety and space | interval of the p-type deep layer 10. FIG.

Explanation of symbols

1 n ⁺ type substrate 2 n ⁻ type drift layer 3 p type base region 4 n ⁺ type source region 5 p ⁺ type contact layer 6 p ⁺ type body layer 7 trench 8 gate oxide film 9 gate electrode 10 p type deep layer 11 source Electrode 12 Interlayer insulating film 13 Drain electrode 20 Mask

Claims (4)

A first or second conductivity type substrate (1) made of silicon carbide;
A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate (1) and having a lower impurity concentration than the substrate (1);
A base region (3) made of silicon carbide of the second conductivity type formed on the drift layer (2);
A source region (4) formed on the base region (3) and made of silicon carbide of the first conductivity type having a higher concentration than the drift layer (2);
Formed so as to be deeper than the source region (4) and the base region (3) and reach the drift layer (2), and the source region (4) and the base region (3) are disposed on both sides. A trench (7) having a longitudinal direction as one of the directions,
A gate insulating film (8) formed on the surface of the trench (7);
A gate electrode (9) formed on the gate insulating film (8) in the trench (7);
A source electrode (11) electrically connected to the source region (4) and the base region (3);
A drain electrode (13) formed on the back side of the substrate (1),
By controlling the voltage applied to the gate electrode (9), an inverted channel region is formed on the surface of the base region (3) located on the side surface of the trench (7), and the source region (4) And a silicon carbide semiconductor device comprising an inversion type MOSFET for passing a current between the source electrode (11) and the drain electrode (13) via the drift layer (2),
It is disposed below the base region (3) and located deeper than the trench (7), and extends in a direction intersecting the longitudinal direction of the trench (7) and parallel to the substrate plane. A deep layer (10) of the second conductivity type provided;
A body layer (6) of the second conductivity type that is disposed so as to be separated from the side surface of the trench (7), is deeper than the source region (4), and has a higher concentration than the base region (3). And ,
The base region (3) and the source region (4) are also formed on the deep layer (10), and the source electrode (11) is formed through the channel region even at the position where the deep layer (10) is formed. And a silicon carbide semiconductor device, wherein a current flows between the drain electrode (13) .   The width of the deep layer is 1.5 μm, the distance between the deep layers is 2.0 μm, and the distance from the side surface of the trench (7) to the body layer (6) is 0.4 to 0.9 μm. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is separated. The concentration of the second conductivity type impurity in the base region (3) is 5.0 × 10 ¹⁵ to 5.0 × 10 ¹⁶ / cm ³ , and the concentration of the second conductivity type impurity in the body layer (6) is 1.0. ^{3. The} silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is set to × 10 ^{18 to} 1.0 × 10 ²⁰ / cm ³ . Forming a drift layer (2) made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate (1) on the first or second conductivity type substrate (1) made of silicon carbide; When,
Forming a second conductivity type deep layer (10) on the surface layer of the drift layer (2) so as to extend in one direction;
Forming a base region (3) made of silicon carbide of the second conductivity type on the deep layer (10) and the drift layer (2);
In the base region (3), a source region (4) made of silicon carbide of the first conductivity type having a higher concentration than the drift layer (2) is formed in a surface layer portion of the base region (3). Process,
A body region (6) made of silicon carbide having a second conductivity type higher than that of the base region (3) by ion-implanting a second conductivity type impurity at a position deeper than the source region (4). ) At intervals of a predetermined distance;
In the place where the body region (6) is separated, it penetrates the base region (3) from the surface of the source region (4) to the drift layer (2), and the deep layer (10) Forming a trench (7) having a longitudinal direction parallel to the substrate plane and a direction intersecting with the direction in which the deep layer (10) extends so as to be shallower than
Forming a gate insulating film (8) on the surface of the trench (7);
Forming a gate electrode (9) on the gate insulating film (8) in the trench (7);
Forming a source electrode (11) electrically connected to the source region (4) and the base region (3);
Forming a drain electrode (13) on the back side of the substrate (1). A method for manufacturing a silicon carbide semiconductor device, comprising:

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