JP2917532B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a silicon carbide semiconductor, particularly suitable for high voltage and large current, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A so-called power transistor suitable for handling a high voltage or a large current has conventionally used all silicon semiconductors. , Field effect transistors and insulated gate bipolar transistors. The most basic performance required for the power transistor in general is that the on-state forward voltage is low, the input impedance is high, and the switching speed is high. Looking at transistors, each has advantages and disadvantages.

That is, the bipolar transistor and the field-effect transistor both have a high switching speed, but the former has an advantage of a low forward voltage,
The latter has the disadvantage of low input impedance, and the latter has the advantage of high input impedance, but has the disadvantage of high forward voltage. These insulated gate bipolar transistors have a low forward voltage and a high input impedance, but have the disadvantage of a slower switching speed.

For this reason, various efforts have been made in the past to improve the performance of power transistors by solving the above problems, but this improvement naturally has its limitations based on the basic performance values of semiconductor materials. At present, it is considered that the theoretical limit of the performance of a transistor using a silicon semiconductor is already approaching considerably, and silicon carbide is attracting attention as one of new semiconductor materials capable of overcoming this limit.

As is well known, silicon carbide is a semiconductor having a wider bandgap than silicon, and is attracting attention as a material for semiconductor devices suitable for environments with high radioactivity levels or places with high noise such as around automobile engines. But
Recently, highly crystalline wafers have been obtained (eg, RFDavis etal; Mat. Res. Soc. Symp.
c., Vol. 162, l990, p. 463), and the feasibility of a semiconductor device using the same is being studied (for example, K.
Shenai et al; IEEE Trans. On Elect. Dev., Vol. 36,
No. 9, 1989, p.1181).

[0006] In addition to the above-mentioned characteristics of silicon carbide having a wide band gap, silicon carbide has a characteristic that the electric field strength at which a carrier multiplication effect occurs in the crystal is higher than that of silicon, and thus the dielectric breakdown voltage is higher. Since it is not always easy to form a semiconductor layer having the same structure therein, a field effect type is more suitable than a bipolar type as a transistor using silicon carbide. Related to effect transistors. Although little is known about the prior art regarding this type of transistor, RFDavis, HFPC May (1989) Proceedings;
On p.81, there is a report that as a result of trial production of a horizontal field-effect transistor, transistor characteristics similar to those of a silicon semiconductor were obtained.

However, such a field-effect transistor having a horizontal structure is disadvantageous for a large current, as is well known, and is disadvantageous even in achieving a high breakdown voltage by utilizing the inherent characteristics of silicon carbide which can withstand a high electric field strength. Therefore, it is desirable to employ a vertical structure for a high voltage and large current in a field effect transistor using a silicon carbide semiconductor. Although a vertical structure of a silicon carbide field effect transistor suitable for such power is not yet known, an outline of a typical vertical structure when a silicon semiconductor is used for reference will be briefly described below with reference to FIG. I do.

A vertical field effect transistor for a large current generally comprises a number of small transistors connected in parallel. FIG. 4 shows one unit in such a composite structure in the case of an n-channel type. A drain connection layer 41 is diffused in a strong n-type from the back side of the n-type substrate 40, and a polycrystalline silicon gate 43 is provided on the surface thereof via a gate oxide film 42. The impurity is ion-implanted and thermally diffused to form a deep p-type well 44 and a shallow n-type source layer 45 such that the peripheries extend under the gate 43 as shown in the figure. . Further, after covering the area of the gate 43 with the insulating film 46, an aluminum electrode film 47 is provided thereon, and the electrode film 47 is also attached to the drain connection layer 41 on the back surface side.

Such a vertical field effect transistor 50 is
As shown, the electrode film 47 for short-circuiting the well 44 and the source layer 45 on the surface is replaced with the source terminal S, the electrode film 47 connected to the drain connection layer 41 is replaced with the drain terminal D, and the electrode film 46 connected to the gate 43. Is a gate terminal G, and the terminal G
By controlling the formation of a channel on the surface of the lower part of the gate 43 of the well 44 by the gate voltage applied to the well 44, the source terminal S and the drain terminal D are cut off or made conductive. The current i at the time of conduction is called a vertical type because it flows vertically inside the substrate 40 and the like as shown in the figure.

[0010]

However, it is difficult to apply the vertical structure as shown in FIG. 4 to a field effect transistor using silicon carbide as it is. This is because the temperature required for diffusion of impurities for forming a semiconductor layer is about 2000 ° C. or more for silicon carbide compared to about 1000 ° C. for silicon, and impurities can be thermally diffused at such a high temperature. This is because practical equipment is not practical, and rather deep diffusion like the well 44 in FIG. 4 takes a very long time, so that it is practically impractical.

Another problem is that the field effect transistor has a drawback that the forward voltage is originally high as described above. Even if a high breakdown voltage can be achieved by using silicon carbide, a large current cannot be obtained. If the forward voltage at the time of flowing is too high, its practicality may be significantly reduced. To lower the forward voltage, it is necessary to increase the impurity concentration in the semiconductor layer to lower its intrinsic resistance. However, as described above, it is difficult to eliminate this drawback if the impurity diffusion is difficult.

The present invention solves the problems of silicon carbide in which the thermal diffusion of impurities is difficult based on the present situation, and further utilizes the characteristics of a field-effect transistor having a high switching speed and a high input impedance while further improving its high withstand voltage. It is an object of the present invention to provide a vertical-structure field effect transistor using silicon carbide and a method of manufacturing the same using silicon carbide, which is capable of improving the forward voltage.

[0013]

According to the present invention, there is provided a field effect transistor comprising a first semiconductor region made of silicon carbide of one conductivity type and silicon carbide of another conductivity type superposed thereon. A second semiconductor region, and a third semiconductor region of one conductivity type formed in a part of the surface of the second semiconductor region.
A semiconductor region, a recess dug to reach the first semiconductor region from within the third semiconductor region, a gate insulating film covering the surface of the recess, and a recess formed through the gate insulating film. And a pair of source / drain terminals connected to the first and third semiconductor regions, and a gate terminal connected to the gate region. The first semiconductor region extends from the periphery of the second semiconductor region. Is achieved by digging a mesa-etched groove reaching.

In general, the first semiconductor region in the above structure may be used as a drain layer, the second semiconductor region may be used as a well or a substrate, and the third semiconductor region may be used as a source layer. It is preferable that the second semiconductor region is an epitaxial layer of silicon carbide grown on a substrate made of silicon carbide of the conductivity type of the above, and the second semiconductor region is an epitaxial layer of silicon carbide further grown thereon. It is preferable to use a single crystal of silicon carbide having a high impurity concentration. Further, the third semiconductor region may be a very shallow semiconductor layer which is activated by introducing impurities into the surface of the second semiconductor region. Further, it is advantageous that the second semiconductor region and the third semiconductor region are short-circuited to each other on the surface by an electrode film for leading out a terminal.

It is desirable that the field effect transistor of the present invention also has a composite structure in which small transistors are integrated as in the case of using a silicon semiconductor. In a field effect transistor for high breakdown voltage, a guard ring or a channel stopper layer is usually provided in order to prevent dielectric breakdown along the semiconductor surface. However, when a silicon carbide semiconductor is used, impurity diffusion for the purpose is difficult, so that the second semiconductor region is used instead. It is advantageous to dig a mesa-etched groove reaching the first semiconductor region from the periphery of. When the field effect transistor has the above-described composite structure, the mesa etching groove may be provided so as to commonly surround a plurality of small transistors.

The method of manufacturing a field-effect transistor according to the present invention includes a step of epitaxially growing a first semiconductor region of silicon carbide of one conductivity type on a substrate of silicon carbide of one conductivity type; A step of epitaxially growing a second semiconductor region of silicon carbide of the other conductivity type thereon, a step of digging a recess in a part of the surface of the second semiconductor region so as to reach the first semiconductor region, Covering the surface of the substrate with a gate insulating film, and forming a gate region so as to fit into the recess through the gate insulating film,
Implanting impurities into the peripheral region of the recess on the surface of the second semiconductor region to form the third semiconductor region in one conductivity type; and forming a source and a source connected to the first and third semiconductor regions.
Disposing a drain electrode film and a gate electrode film connected to the gate region.

In the epitaxial growth step of the first and second semiconductor regions in the above structure, these semiconductor regions may be grown in a vapor phase by a CVD method using a source gas containing silane and methane. It is advantageous to use a reactive ion etching method in the excavation step. In the step of covering the gate insulating film, it is preferable to form a silicon oxide film by oxidizing the surface of the recess, and in the step of forming a gate region in the recess, polycrystalline silicon is grown by CVD. Advantageously.

In the step of forming the third semiconductor region, it is difficult to thermally diffuse the impurity after ion implantation as described above. Therefore, the implanted impurity is activated by a high-temperature heat treatment, and the impurity is shallow, for example, about 0.1 μm. The third semiconductor region may be formed. Further, the step of forming the third semiconductor region does not need to be performed after the gate region is provided, but may be performed before the step of excavating the recess for the gate region.

The use of aluminum as the p-type impurity and the use of nitrogen as the n-type impurity for the silicon carbide semiconductor improves the characteristics of the field-effect transistor by imparting impurity levels as narrow as possible to the respective semiconductor regions. Desirable above.

[0020]

In the field effect transistor according to the present invention, the first and second semiconductor regions described in the preceding item are constituted by an epitaxial layer of silicon carbide, impurities are introduced from the beginning during the epitaxial growth, and the gate region is formed by the first and second semiconductor regions. 2
By making the portion of the second semiconductor region in contact with the gate insulating film on the side surface of the recess as a so-called buried structure to be fitted into the recess dug to reach the first semiconductor region through the semiconductor region, This eliminates the need to diffuse impurities from the back into the first and second semiconductor regions, and solves the problem of silicon carbide in which thermal diffusion of impurities is difficult.

Further, the present invention improves the withstand voltage of the field effect transistor by setting the electric field strength in the first semiconductor region to be high by utilizing the feature that silicon carbide has a high allowable maximum electric field strength. By optimizing the thickness of the first semiconductor region in accordance with the set value, the forward voltage of the field effect transistor can be reduced. Hereinafter, the reason why the forward voltage can be reduced will be described using some equations.

In the field effect transistor of the present invention, as described above, a channel is formed in the second semiconductor region, and if the on-resistance is R, the sum of the resistance Rc of this channel and the resistance R1 in the first semiconductor region is obtained. , R = Rc + R1 1) In a high withstand voltage field effect transistor of several hundred V or more, the channel resistance Rc is 1% of the resistance R1 of the first semiconductor region.
Actually, the resistance R may be determined only by the resistance R1.

Similarly, the voltage applied when the field effect transistor is turned off may be applied to the first semiconductor region, and can be expressed by the following equation, where V is the withstand voltage of the field effect transistor. V = Emd−qN1d ² / 2ε 2) where Em is the electric field intensity in the first semiconductor region, that is, the allowable maximum electric field intensity of silicon carbide, d is the thickness of the first semiconductor region, q
Is the electron charge, N1 is the impurity concentration of the first semiconductor region, and ε is the dielectric constant of silicon carbide. As is well known, the internal electric field intensity distribution when the depletion layer extends in the first semiconductor region is well known. It changes linearly with a slope determined by the impurity concentration.

Since the resistance R1 of the first semiconductor region in the equation (1) at the time of ON is proportional to the thickness d and inversely proportional to the impurity concentration N1, if the ON resistance R is equal to the resistance R1, the reciprocal thereof is as follows. It is expressed by the following equation. 1 / R = A · μN1 / d 3) where A is a proportionality constant, and μ is the mobility of electrons in silicon carbide. By the way, the impurity concentration obtained from the equation (3) and the equation (2)
When N1 is inserted, 1 / R = A · (2εμ / q) (Em / d ² −V / d ³ ) 4) is obtained. The right side of the equation (4) is the thickness d of the first semiconductor region.
When the thickness that minimizes the left side is obtained as a function of the following equation, d = 3V / 2Em 5). Assuming that the forward voltage of the field effect transistor when the thickness of the first semiconductor region is set to this optimum value d is Vf, By substituting the thickness d in equation (5) into equation (4), the following equation is obtained. VfαRαV ² / εμEm ³ 6)

As can be seen from the above, the forward voltage Vf of the field effect transistor is reduced by 6 by optimizing the thickness d of the first semiconductor region according to the maximum electric field strength Em of silicon carbide as in the above equation (5). ), It can be reduced in inverse proportion to the cube of the maximum electric field strength Em. The maximum electric field strength Em of silicon carbide is 3x
Since about one order of magnitude higher than 3.7 × 10 ¹⁵ V / cm of silicon at 10 ¹⁶ V / cm it can be seen that significantly reduce the forward voltage Vf. Also, the thickness d of the first semiconductor region can be made as thin as about ８ of that of silicon. Note that the above effect is slightly reduced because the mobility μ of electrons in equation 6) is lower in silicon carbide than in silicon, but the forward voltage can still be reduced to about 1/20.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of an embodiment of a field-effect transistor according to the present invention, FIG.
2A and 2B are a cross-sectional view and a top view of a field-effect transistor having a composite structure. In these embodiments, all the field effect transistors are of the n-channel type.

For the field-effect transistor 30 shown in FIG. 1, in this embodiment, a strong n-type doped silicon carbide single crystal substrate 10 is deposited on a substrate 10 of the same n-type doped silicon carbide. A three-layer silicon carbide is used in which a first semiconductor region 11 made of an epitaxial layer and a second semiconductor region 12 made of the same silicon carbide doped with a high p-type impurity concentration are sequentially stacked. A shallow third semiconductor region 13 in which nitrogen or the like is ion-implanted at a high dose as an n-type impurity is formed in the central portion of the surface of the second semiconductor region. When the field-effect transistor 30 has a withstand voltage of, for example, 1000 V, the thickness of the first semiconductor region 11 is about 10 μm,
Has a thickness of 1-2 μm and a depth of the third semiconductor region 13 of 0.5 μm.
m. Further, a recess 14 is dug from the center of the third semiconductor region 13 to penetrate the second semiconductor region 12 to reach the first semiconductor region 11, and a thin gate insulating film 21 is provided so as to cover the surface thereof. The gate 23 in this embodiment is made of polycrystalline silicon formed so as to fill the recess 14.

In the field-effect transistor 30 shown in FIG.
The semiconductor region 12 is a p-type well, the third semiconductor region 13 is an n-type source region, the first semiconductor region 11 and the underlying substrate 10 are n-type.
In order to derive connection terminals therefrom, insulating films 24 are provided on the front and back surfaces, respectively, and an electrode film 25 which is in conductive contact with a predetermined portion in a window opened therethrough is provided. As shown, the surfaces of the second semiconductor region 12 and the third semiconductor region 13 are short-circuited by the electrode film 25, and the source terminal S is led out. A drain terminal D is led out of the electrode film 25 that is in conductive contact with the substrate 10, and a gate terminal G is led out of the electrode film 25 that is in conductive contact with the gate 23.

This field-effect transistor 30 is an n-channel type in which a portion of the p-type second semiconductor region 12 facing the gate 23 with the gate insulating film 21 interposed therebetween is a channel forming region.
The channel formation can be controlled by a voltage applied to the gate terminal G as usual, so that the source terminal S and the drain terminal D can be cut off or made conductive. It is of a vertical type in which a current flows vertically in the substrate 10 and the first semiconductor region 11 during conduction, and a depletion layer extends in the first semiconductor region 11 during interruption. As described above, since the maximum electric field strength of silicon carbide in first semiconductor region 11 is high and the thickness can be made approximately one digit thinner than that of silicon, field effect transistor 30 according to the present invention is suitable for high breakdown voltage and The direction voltage can be reduced by one digit or more. The characteristics of the field-effect transistor having a high input impedance and a high switching speed are also utilized in the case of the present invention as they are, and are comparable to those of silicon.
In addition, since silicon carbide has a thermal conductivity about three times higher than that of silicon, there is an advantage that cooling is easy. Note that it is advantageous for the field effect transistor for a large current to have a composite structure as shown in FIG.

Although the field effect transistor of the present invention is suitable for high breakdown voltage as described above, since a guard ring or a channel stopper is provided on the surface as in the case of silicon, it is necessary to diffuse impurities into the surface of the second semiconductor region 12. Is difficult,
Instead, it is desirable to provide a mesa etching groove 15 in the peripheral portion as shown in FIG. For this mesa etching, dry etching using a fluorine-based reaction gas or the like is preferably used. By selecting isotropic etching conditions, the mesa etching groove 15 is formed at a second angle of about 45 degrees as shown in FIG. At least the first semiconductor region from the periphery of the semiconductor region 12
After digging to reach 11, the etched surface is covered with an insulating film 24 of silicon oxide or silicon nitride and then isolated into chips to obtain the state shown in the figure.

Next, a method of manufacturing the field effect transistor of the present invention will be described with reference to FIG. Figure (a) shows several hundred μm.
Each of n-type first semiconductor region 11 and p-type second semiconductor region 12 of silicon carbide is provided on n-type silicon carbide substrate 10
Shows a state where epitaxial growth was performed at a thickness of about 10 μm and a thickness of 1 to 2 μm, respectively, as described above.

The epitaxial growth of these semiconductor regions 11 and 12 may be carried out by vapor phase growth by a CVD method using a source gas containing, for example, silane and methane, and by mixing impurities into the source gas for the vapor phase growth. By arranging, silicon carbide to be epitaxially grown can be doped with impurities at a desired concentration. For this purpose, nitrogen is most suitable as the n-type impurity and aluminum is most suitable as the p-type impurity.

FIG. 2B shows a process of excavating the recess 14.
Chemical etching can be used for this digging, but the recess 14 is digged in a substantially right-angled side shape as shown in the figure under anisotropic etching conditions using dry etching, particularly reactive ion etching. Is advantageous.
It is desirable that the width of the recess 14 is narrow, for example, 2 to 3 μm so that it can be easily filled with polycrystalline silicon or the like in the next step. Although not shown in the figure, this digging etching is of course performed using a photoresist film or the like as a mask.

FIG. 2C shows a step of growing the gate insulating film 21 and the polycrystalline silicon 22 for the gate. The gate insulating film 21 is most easily formed as a thermal oxide film as in the case of silicon, and a silicon oxide film is formed as the gate insulating film 21 even in the case of silicon carbide by short-time thermal oxidation in an atmosphere containing oxygen. It can be applied in a suitable thickness of, for example, 0.05 to 0.1 μm. Next, the polycrystalline silicon 22 is reduced in pressure C using silane as a source gas.
The recess 14 is grown until it fills the recess 14 by the VD method or the like to obtain the state shown in the figure. Furthermore, this polycrystalline silicon 22 is, for example, CF
Fig. 2 (d) by dry etching using ₄ as a reaction gas
The gate insulating film 21 remaining only on the surface other than the recess 14 is removed by short-time chemical etching using dilute hydrofluoric acid or the like.

FIG. 2D shows a step of forming the third semiconductor region 13. To this end, unnecessary portions are covered with a mask (not shown) using an ion implantation method, and nitrogen is applied to the gate 23 on the surface of the second semiconductor region 12 at a high dose under an acceleration voltage of about 100 kV.
Is implanted to a depth of, for example, about 0.1 μm in the peripheral area of the n-type third semiconductor region 13. Since thermal diffusion of the introduced impurities is difficult in silicon carbide, the temperature is thereafter set to 1100 ° C.
A heat treatment is performed only at a high temperature to activate the impurities. Even if the third semiconductor region 13 is very shallow, it can sufficiently serve as its source region. Thereafter, as described with reference to FIG. 1, the mesa etching groove 15 is dug, the insulating film 24 is covered, and the electrode film 25 is provided.
To the completed state.

FIG. 3 shows an embodiment in which the present invention is applied to a field effect transistor 31 having a composite structure. FIG. 3 (a) is a cross-sectional view, FIG. 3 (b) is a partial top view, and FIG.
(b) corresponds to a cross section taken along line XX. The gate 23 in the three recesses 14 in FIG. 3A is actually a cross section of the gate 23 having a continuous mesh pattern shown in FIG. 3B. In the case of a composite structure, it is advantageous to form the recess 14 and the gate 23 in such a net-like or comb-like pattern, and for convenience of illustration, only two meshes are shown in FIG. However, it is actually a net-like pattern having tens to hundreds of eyes. The recess 14 having such a pattern is dug so as to penetrate the second semiconductor region 12 and reach the first semiconductor region 11 as shown in FIG. Recess
It is provided to extend from 14 toward the outside and the inside of the mesh.

As shown in FIG. 3B, the gate 23 has an extending portion 23a extending outward from the net pattern.
The gate terminal G is led out from the electrode film 25 that is in conductive contact with the terminal a. The electrode film 25 for the source terminal S is formed so as to cover the entire mesh pattern of the gate 23, and is insulated from the gate 23 by the insulating film 24, as can be seen from FIG. As in the previous embodiment, the surfaces of the second semiconductor region 12 and the third semiconductor region 13 are short-circuited by the electrode film 25 for the source terminal S. The mesa etching groove 15 is dug into the peripheral portion of the chip of the field effect transistor 31 so as to surround the whole of the composite structure from the outside, and its surface is protected by the insulating film 24. In this example, the electrode film 25 for the drain terminal D is provided so as to cover the entire back surface of the chip as shown in FIG. The field effect transistor 31 having the composite structure shown in FIG.
Are suitable for large currents, can easily be configured with a rating of several tens of amps to more than one hundred amps, and have a field effect transistor 31 of several tens amps.
It can be built in a chip of about mm square.

The present invention is not limited to the above-described embodiments, but can be embodied in appropriate modes and various forms.
The conductivity type, thickness, and the like of each semiconductor region in the embodiment are merely examples, and should be appropriately set in accordance with conditions such as voltage and current in which the field effect transistor is used. Further, in the manufacturing method illustrated in FIG. 2, the third semiconductor region is formed after the recess is formed, but the recess may be formed after the third semiconductor region is formed.

[0039]

As described above, in the field effect transistor of the present invention, the first and second semiconductor regions of silicon carbide are stacked in one and the other conductivity types, and the third semiconductor region is formed in the second semiconductor region.
A part of the surface of the semiconductor region is formed with one conductivity type, a recess is dug from within the third semiconductor region to reach the first semiconductor region, and the surface is covered with a gate insulating film. A gate is formed, and in the manufacturing method, first and second semiconductor regions of silicon carbide of one conductivity type and the other conductivity type are epitaxially grown on a substrate of silicon carbide of one conductivity type. A recess is dug from a part of the surface until reaching the first semiconductor region, the surface is covered with a gate insulating film, a gate region is formed in the recess, and impurities are ion-implanted around the recess to form a first semiconductor region. The following effects can be obtained by forming the three semiconductor regions with one conductivity type.

(A) The first and second semiconductor regions are made of silicon carbide doped with impurities during epitaxial growth,
In addition, by forming a channel in the second semiconductor region as a structure in which the gate is fitted in the recess, the first and second channels are formed.
Eliminates the need to diffuse impurities later into the semiconductor region,
It is possible to provide a highly practical field-effect transistor by solving the problem of difficulty in thermally diffusing impurities into silicon carbide.

(B) By making use of the feature that silicon carbide has a high allowable maximum electric field strength, the first semiconductor region has a role of withstanding high electric field strength, so that the withstand voltage value is much higher than that of the silicon type. A transistor can be formed.

(C) By optimizing the thickness and the impurity concentration in accordance with the set value of the electric field intensity in the first semiconductor region, the forward voltage of the field effect transistor can be reduced by one digit or more compared to the prior art. .

(D) Since the internal heat can be easily dissipated by utilizing the high thermal conductivity of silicon carbide, the chip size of the field effect transistor can be reduced and the operation thereof can be reduced in conjunction with the reduction of the forward voltage. Reliability can be improved.

The present invention overcomes the limitations of using silicon while maintaining the advantages of high switching speed and input impedance of a field-effect transistor, and as described above, has a high breakdown voltage and a low forward voltage. It is possible to commercialize a field effect transistor for practical use for the first time using silicon carbide.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a field-effect transistor using a silicon carbide semiconductor according to the present invention.

FIG. 2 shows an embodiment corresponding to FIG. 1 of the method for manufacturing a field-effect transistor according to the present invention, showing the state in the main process up to the completed state in FIG. 1 by FIGS. It is sectional drawing of the wafer for effect transistors.

FIG. 3 shows an embodiment in which the present invention is applied to a field effect transistor having a composite structure, by a cross-sectional view of FIG. 3A and a partial top view of FIG.

FIG. 4 is a cross-sectional view showing a structural example of a conventional field effect transistor using a silicon semiconductor for reference.

[Explanation of symbols]

 10 Substrate of silicon carbide 11 First semiconductor region or drain region 12 Second semiconductor region or well region 13 Third semiconductor region or source region 14 Recess 15 Mesa etching groove 21 Gate insulating film 22 Polycrystalline silicon 23 Gate 25 Electrode film 30 Field-effect transistor 31 Field-effect transistor of composite structure D Drain terminal G Gate terminal S Source terminal

Claims (1)

(57) [Claims] A first semiconductor region made of silicon carbide of one conductivity type, a second semiconductor region made of silicon carbide of another conductivity type superposed thereon, and a first semiconductor region made of silicon carbide of another conductivity type. A third semiconductor region formed of one conductivity type in the region of the portion, a recess dug to reach the first semiconductor region from within the third semiconductor region, and a surface of the recess. A gate insulating film to cover, a gate region formed in the recess through the gate insulating film, a pair of source / drain terminals connected to the first and third semiconductor regions, and a gate terminal connected to the gate region And a mesa-etched groove extending from the periphery of the second semiconductor region to the first semiconductor region.