JP4164892B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly suitable for application to an insulated gate field effect transistor (hereinafter referred to as a power MOSFET), in particular, a vertical power MOSFET.
[0002]
[Prior art]
There are a field plate structure and a guard ring structure as a structure applied to the chip outer peripheral area (unit cell outer peripheral area) of the semiconductor device. As an example of these structures, FIG. 27 shows a storage channel type planar MOSFET to which a field plate structure is applied.
[0003]
As shown in FIG. 27, the outer peripheral region of the cell region where the planar MOSFET 500 is formed has n⁺N formed on the type semiconductor substrate 501^-A p-type layer region 507 extending toward the outside of the cell region is provided in the surface layer portion of the type semiconductor layer 502. This p-type layer region 507 has n^-By forming a PN junction with the type semiconductor layer 502, it plays the role of preventing breakdown.
[0004]
Further, an electrode 522 is provided in the outer peripheral region in contact with the p-type layer 507 through a contact hole formed in the insulating film 518 and extending toward the outside of the cell region.
This electrode 522 is a field plate, and the withstand voltage can be improved by making the electrode 522 extending toward the outside of the cell region become equipotential and extending the depletion layer to the outer periphery of the cell region. .
[0005]
In general, since the breakdown voltage of a semiconductor device is determined by the shape of a region where a pn junction terminates, there is a termination technique that weakens the electric field in this region evenly in order to obtain a high breakdown voltage semiconductor device. As one of the termination techniques, a mesa structure as shown in JP-A-4-239778 has been proposed.
As a semiconductor device having a mesa structure, an n-channel vertical power MOSFET is shown in FIG. 28, and the mesa structure will be described with reference to FIG.
[0006]
The semiconductor substrate 120 of this vertical power MOSFET has n⁺N on the silicon carbide semiconductor substrate 101^-A laminated layer of a p-type silicon carbide semiconductor layer 102 and a p-type silicon carbide conductor layer 103 is used. A groove 107 is formed in this substrate to form an oxide film 109 and a gate electrode 110. A source region 104 is formed around the region to form a cell region. Then, a groove 105 surrounding the periphery of the cell region is formed. For example, the side surface of the groove 105 is tapered. In this way, n around the cell region^-A mesa structure is formed by terminating a pn junction composed of a silicon carbide semiconductor layer 102 and a p-type silicon carbide conductor layer 103 on the side surface of the groove 105.
[0007]
By adopting such a mesa structure, it is attempted to increase the breakdown voltage of the semiconductor device.
As shown in FIG. 29, in the mesa structure, the side surface of the groove 105 may not be a tapered shape but may be substantially perpendicular to the substrate surface.
[0008]
[Problems to be solved by the invention]
However, it has been found that the above structure has the following problems.
First, in the field plate structure shown in FIG. 27, when silicon carbide is used as the semiconductor material, the critical electric field strength at which avalanche breakdown occurs is an order of magnitude higher than when silicon is used, and the n-type drain layer The impurity concentration of the drain layer (n⁺The resistance value of the type semiconductor layer 501) can be lowered, and the on-resistance can be reduced. However, if the impurity concentration is set so high, the depletion layer extends outside the cell region and electric field concentration occurs at the interface of the insulating film 509. Therefore, once avalanche breakdown occurs at this interface. There arises a problem that hot carriers having high energy are injected into the insulating film 509 and dielectric breakdown occurs. This problem also occurs when the guard ring structure is adopted.
[0009]
On the other hand, in the mesa structure shown in FIG. 28, the side portion of the groove 105 constituting the mesa structure, specifically, n^-There is a problem that electric field concentration occurs at the connection portion between the interface between oxide silicon carbide semiconductor layer 102 and p-type silicon carbide semiconductor layer 103 and oxide film 109, and oxide film 109 in this electric field concentration portion is dielectrically broken down.
Further, in the case of the mesa structure, particularly when the side surface of the groove 105 is substantially perpendicular to the substrate surface as shown in FIG. 29, the groove 105 as shown by the equipotential line in the figure. There is also a problem that electric field concentration is likely to occur also at the corners of this area, and the insulating film 109 in this part is broken down.
[0010]
The present invention has been made in view of the above problems, and an object thereof is to prevent dielectric breakdown of an insulating film caused by electric field concentration in a silicon carbide semiconductor device.
[0011]
[Means for Solving the Problems]
  In order to achieve the above object, the following technical means are adopted. In the first aspect of the present invention, the first conductive type low resistance layer (1) and the first conductive type first semiconductor layer formed on the low resistance layer and having a higher resistance than the low resistance layer. (2) and a second semiconductor layer (3) of the second conductivity type formed on the first semiconductor layer, and a semiconductor substrate (100) whose main surface is the surface of the second semiconductor layer ) To form a first groove (7) constituting the cell region and a second groove (5) constituting the mesa structure, and an insulating film (9) on the side surface of the second groove, Between the second semiconductor layer and the first semiconductor layer,The resistance is higher than that of the first semiconductor layer,Reducing electric field concentration in insulating film1Electric field relaxation layer made of conductive material (6) And at the time of breakdown, an avalanche breakdown is caused in the vicinity of a region where the electric field relaxation layer, the first semiconductor layer (2), and the second semiconductor layer intersect, so that the electric field relaxation layer It is characterized by alleviating electric field concentration.
[0012]
  Thus, even in the case where the cell region has a groove shape, the second region between the insulating film on the side surface of the second groove, the second semiconductor layer, and the first semiconductor layer1By forming an electric field relaxation layer made of a conductive type material, the electric field concentration at the portion of the second groove constituting the mesa structure, that is, at the interface between the interface between the first semiconductor layer and the second semiconductor layer and the insulating film. Can be mitigated, and dielectric breakdown of the insulating film can be prevented.
  Further, by forming the electric field relaxation layer with the first conductivity type material having a higher resistance than the first semiconductor layer, the extension of the depletion layer is increased by the electric field relaxation layer, and the first semiconductor layer and the second semiconductor layer are formed. Electric field concentration at the interface between the layer and the insulating film can be reduced.
[0014]
  Claims2In the invention described in (1), an electrode layer (40) connected to the first electrode is provided on the surface of the insulating film formed on the surface of the electric field relaxation layer. It is characterized by a lower voltage.
[0015]
  Thus, since the electric field relaxation layer can be always depleted by making the voltage of the electric field relaxation layer lower than the threshold voltage, the interface between the first semiconductor layer and the second semiconductor layer and the insulating film Electric field concentration can be prevented from occurring at the connection part.
[0018]
  Claims3As shown inOr 2The invention described in (5) is preferably applied to a silicon carbide semiconductor device in which the low resistance layer, the first semiconductor layer, the second semiconductor layer, and the electric field relaxation layer are made of silicon carbide..
[0023]
  Claim4In the invention described in the above, after the mesa structure forming groove (5) is formed, at least the side surface of the mesa structure forming groove is formed.Higher resistance than the first semiconductor layerFirst1Electric field relaxation layer made of conductive material (6), And then a cell region forming groove (7) is formed.
  As described above, since the formation of the cell region formation groove is performed after the formation of the electric field relaxation layer, the electric field relaxation layer is not formed in the cell region formation groove. For this reason, it is possible to freely select another semiconductor layer in the cell region forming groove, and to change the parameters in the semiconductor device.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below.
(First embodiment)
FIG. 1 is a sectional view of an n-channel type vertical power MOSFET according to an embodiment of the present invention. Hereinafter, the structure of the vertical power MOSFET will be described with reference to FIG.
[0046]
N as a low-resistance semiconductor layer made of hexagonal silicon carbide⁺N type silicon carbide semiconductor substrate 1 as a high resistance semiconductor layer^-Type silicon carbide semiconductor layer 2 and p type silicon carbide semiconductor layer 3 are sequentially laminated.⁺Type silicon carbide semiconductor substrate 1, n^-A semiconductor substrate 100 made of single crystal silicon carbide is constituted by the type silicon carbide semiconductor layer 2 and the first p-type silicon carbide semiconductor layer 3. The upper surface of the semiconductor substrate 100 is a substantially (0001-) carbon surface.
[0047]
The predetermined region in the surface layer portion in p-type silicon carbide semiconductor layer 3 has n as a semiconductor region.⁺A mold source region 4 is formed. N⁺A groove 7 is formed in a predetermined region of the mold source region 4. This groove 7 is n⁺Type source region 4 and p type silicon carbide semiconductor layer 3, and n^-Type silicon carbide semiconductor layer 2 is reached.
Groove 5 is formed in a predetermined region of p-type silicon carbide semiconductor layer 3, and this groove 5 is formed to be the same as or deeper than groove 7. The groove 5 is formed so as to surround a circle around the groove 7 serving as a cell region, and a mesa structure is formed by the groove 5.
[0048]
In addition, the groove side surface of the groove 5 is n as an electric field relaxation layer made of a silicon carbide semiconductor.^-A high resistance layer 6 of the mold is formed. This high resistance layer 6 is formed of n^-It has a higher resistance than that of the type silicon carbide semiconductor layer 2 and is formed at a lower concentration by about one digit when converted to an impurity concentration.
Further, a thermal oxide film 9 as a gate insulating film is formed on the substrate including the grooves 7 and 5. A base electrode 10 made of polysilicon is formed on the channel forming portion in the groove 5, and an insulating film 11 is formed on the semiconductor substrate 100 including the gate electrode 10.
[0049]
A source electrode 12 is formed on the thermal oxide film 9, and the source electrode 12 is n through a contact hole formed in the thermal oxide film 9 and the insulating film 10.⁺Electrically conductive with source region 4 and p-type silicon carbide semiconductor layer 3.
N forming the bottom surface of the groove 5^-N-type silicon carbide semiconductor layer 2 has a high concentration of n so as to surround the cell region.⁺A type silicon carbide semiconductor layer 15 is formed. This n⁺The type silicon carbide semiconductor layer 15 is electrically connected to the electric wiring 16 through contact holes formed in the thermal oxide film 9 and the insulating film 10, and when using the vertical power MOSFET, the electric wiring 16 P-type silicon carbide semiconductor layer 3 and n are held around the cell at the same potential.^-The degree of extension of the depletion layer at the pn junction by the silicon carbide semiconductor layer 2 is made uniform.
[0050]
Thus, the vertical power MOSFET has n on the outermost groove side surface.^-The structure includes a high-resistance layer 6 of a mold. And this n^-Type high resistance layer 6 is n^-It serves to prevent dielectric breakdown in the thermal oxide film 9 in the vicinity of the interface between the p-type silicon carbide semiconductor layer 2 and the p-type silicon carbide semiconductor layer 3, that is, in the thermal oxide film 9 in the mesa structure.
[0051]
In addition, when a predetermined drive voltage is applied to the gate electrode 10 in the vertical power MOSFET configured as described above, n^-Type silicon carbide semiconductor layer 2 and n⁺The p-type silicon carbide semiconductor layer 3 between the type source regions 4 serves as a channel region to flow current.
The gate, source, and drain potentials in the vertical power MOSFET are represented by VG, VS, and VD, respectively.
[0052]
2 when using the vertical power MOSFET shown in FIG.^-Electric field distribution curve in type silicon carbide semiconductor layer 2 is indicated by a dotted line.
As shown in this figure, n^-Electric field in type silicon carbide semiconductor layer 2 shows a distribution spread in a plane by a mesa structure. The electric field is concentrated in the vicinity of the high resistance layer 6. The electric field distribution curve is terminated through the high resistance layer 6.
[0053]
At this time, since the electric field is concentrated in the high resistance layer 6 portion, the electric field concentration is also observed in the thermal oxide film 9. However, even when the high resistance layer 6 is broken down, the breakdown is caused by the high resistance layer 6. And p-type silicon carbide semiconductor layer 3 and n^-Avalanche breakdown in the vicinity of the region where the silicon carbide semiconductor layer 2 intersects, and the thermal oxide film 9 and n^-Since this is not a breakdown at the interface between p-type silicon carbide semiconductor layer 2 and p-type silicon carbide semiconductor layer 3, breakdown of thermal oxide film 9 is suppressed by breakdown. As described above, since the dielectric breakdown of the thermal oxide film 9 can be prevented, the breakdown voltage in the vertical power MOSFET can be improved.
[0054]
Next, a manufacturing process of the trench gate type power MOSFET will be described with reference to FIGS.
[Step shown in FIG. 3 (a)]
First, a low-resistance n whose main surface is a (0001-) carbon surface⁺Type silicon carbide semiconductor substrate 1 is prepared and n is formed on the surface thereof^-Type silicon carbide semiconductor layer 2 is epitaxially grown, and n^-P type silicon carbide semiconductor layer 3 is epitaxially grown on type silicon carbide semiconductor layer 2. As a result, n⁺Type silicon carbide semiconductor substrate 1 and n^-Double epi semiconductor substrate 100 formed of type silicon carbide semiconductor layer 2 and p type silicon carbide semiconductor layer 3 is formed.
[0055]
Then, using a mask material for p-type silicon carbide semiconductor layer 3, for example, ion implantation of nitrogen or the like is performed, and n is applied to a predetermined region of the surface layer portion of p-type silicon carbide semiconductor layer 3.⁺A mold source region 4 is formed.
[Step shown in FIG. 3B]
Dry etching is performed to penetrate the p-type silicon carbide semiconductor layer 3 and n^-Groove 5 reaching type silicon carbide semiconductor layer 2 is formed. At this time, n is the cell region⁺The groove 5 is formed so as to form a substantially circular shape centering on the mold source region 4.
[0056]
[Step shown in FIG. 3 (c)]
Epitaxial growth is performed, and the epitaxial growth layer is thermally oxidized to form n on the side surface of the groove 5.^-A high resistance layer 6 made of a type silicon carbide semiconductor is formed. However, this high resistance layer 6 is n^-Concentration lower than that of type silicon carbide semiconductor layer 2, that is, n^-It is formed with a higher resistance than the type silicon carbide semiconductor layer 2. In this epitaxial growth and thermal oxidation, n^-Type silicon carbide semiconductor layer 2 and p type silicon carbide semiconductor layer 3 have a hexagonal crystal structure.^-The type silicon carbide semiconductor layer 6 is uniformly formed with good control (see Japanese Patent Application Laid-Open Nos. 7-326755, 9-74193, and Japanese Patent Application No. 8-9625).
[0057]
[Step shown in FIG. 4 (a)]
n⁺N in the center of the source region 4⁺A groove 7 penetrating through the source region 4 and the p-type silicon carbide semiconductor 3 is formed. At this time, the depth of the groove 7 is the same as or shallower than that of the groove 5.
Further, the step of forming the groove 7 is n^-Since the process is performed after the step of forming silicon carbide semiconductor layer 6, the silicon carbide semiconductor layer is not formed in groove 7. Therefore, when it is desired to form a semiconductor layer in the groove 7, n^-A semiconductor layer having a conductivity type different from that of type silicon carbide semiconductor layer 6, a semiconductor layer having the same conductivity type and a different concentration, or a semiconductor layer having a different thickness can be separately formed. Thereby, the parameter in the vertical power MOSFET can be changed.
[0058]
[Step shown in FIG. 4B]
N in the portion where the groove 5 is formed using the mask material^-N-type silicon carbide semiconductor layer 2 is ion-implanted, for example, with nitrogen so that the cell region goes around the bottom of trench 5⁺Type silicon carbide semiconductor layer 8 is formed.
[Step shown in FIG. 4 (c)]
A thermal oxide film 9 is formed on the surface of the semiconductor substrate 100 including the grooves 5 and 7 by thermal oxidation. At this time, thermal oxidation is performed in a wet atmosphere. Then, the double epitaxial substrate is raised to 1000 ° C., and a thermal oxide film 9 of, eg, 100 nm is formed on the side surface of the groove, and a thermal oxide film 9 of, eg, 500 nm is formed on the bottom surface of the groove.
[0059]
[Step shown in FIG. 5A]
A polysilicon layer is laminated on the semiconductor substrate 100, and a gate electrode layer 10 is formed on the surface of the thermal oxide film 9 in the groove 7 by photo-etching.
[Step shown in FIG. 5B]
The insulating film 1 is formed on the upper surface of the gate electrode layer 10 by a vapor deposition method (for example, chemical vapor deposition method). Then, contact holes are selectively formed in a predetermined region by photo etching.
[0060]
[Step shown in FIG. 5 (c)]
A source electrode 12 made of, for example, Ni is formed on the surfaces of the source region 4 and the p-type silicon carbide semiconductor layer 3 including the insulating film 11. And n⁺When drain electrode 13 made of, for example, Ni is formed on the back side of type silicon carbide semiconductor substrate 1, a vertical power MOSFET having the configuration shown in FIG. 1 is completed.
[0061]
  (Second Embodiment)
  Next, a second embodiment to which the present invention is applied will be described with reference to FIG. In the first embodiment described above, the groove 5 sideOn the facen^-The type silicon carbide semiconductor layer 6 is formed as an electric field relaxation layer, but in this embodiment n^-Instead of the type silicon carbide semiconductor layer 6, the p-type silicon carbide semiconductor layer 30 is grooved.5The electric field relaxation layer is formed on the side surface of the substrate.
[0062]
FIG. 7 shows an electric field distribution when the vertical power MOSFET in FIG. 6 is used. As shown in this figure, p-type silicon carbide semiconductor layer 30 and n^-Electric field is changed by the depletion layer generated by the pn junction in type silicon carbide semiconductor layer 2, and the electric field distribution curve is shown as extending in the bottom direction of groove 5.
Thus, by forming the p-type silicon carbide semiconductor layer 30 on the side surface of the groove 5 constituting the mesa structure, electric field concentration on the side surface of the groove 5 can be prevented. Thereby, dielectric breakdown of the thermal oxide film 9 caused by the electric field concentration can be prevented.
[0063]
  Note that n in the first embodiment described above.^-In the step of forming the silicon carbide semiconductor layer 6, the p-type silicon carbide semiconductor layer 30 can be formed by ion implantation of, for example, aluminum instead of epitaxially growing the silicon carbide semiconductor layer. A vertical power MOSFET in the form can be manufactured. Furthermore, by depositing an aluminum alloy, a metal layer that can obtain the same effect as that of p-type silicon carbide semiconductor layer 30 can be formed. In these cases, the trenches can be formed without using the epitaxial growth method.5An electric field relaxation layer can be formed on the side surface.
[0064]
  (Third embodiment)
  Next, 3rd Embodiment concerning this invention is described based on FIG. In the first embodiment described above, the groove 5 sideOn the facen^-Although the type silicon carbide semiconductor layer 6 is only formed as an electric field relaxation layer, in this embodiment, n is used when a vertical power MOSFET is used.^-In order to always deplete type silicon carbide semiconductor layer 6, n is sandwiched between thermal oxide films 9 on the side surfaces of trench 5.^-Electrode layer 40 is provided on the opposite side of type silicon carbide semiconductor layer 6.
[0065]
The electrode layer 40 is n through a contact hole formed in the insulating film 11.⁺It is electrically connected to the mold source region 12. When the vertical power MOSFET is used, the electrode layer 40 is clamped at the same potential as the source electrode 12 so that n^-Electrons in the silicon carbide semiconductor layer 6 are eliminated, and n^-The type silicon carbide semiconductor layer 6 is always depleted. And in this way n^-By depleting type silicon carbide semiconductor layer 6, electric field concentration on the side surface of trench 5 can be prevented, so that dielectric breakdown of thermal oxide film 9 on the side surface of trench 5 can be prevented.
[0066]
Thereby, the dielectric breakdown of the thermal oxide film 9 can be further prevented as compared with the first embodiment.
In the present embodiment, the electrode layer 40 and the source electrode 12 are electrically connected.^-This is because the voltage of type silicon carbide semiconductor layer 6 is set to a voltage lower than the threshold voltage. If this condition is satisfied, the potential of electrode layer 40 may be set by means other than source electrode 12.
[0067]
In addition, the electrode layer 40 is formed at the same time in the step of forming the gate electrode layer 10 shown in FIG. 5A, and further when the contact hole is formed in the insulating film 1 shown in FIG. 5C. The vertical power MOSFET in this embodiment can be manufactured by simultaneously forming a contact hole that communicates 40 with the source electrode 12.
[0068]
(Fourth embodiment)
Next, a third embodiment according to the present invention will be described with reference to FIG.
In the second embodiment described above, the p-type silicon carbide semiconductor layer 30 is formed on the side surface of the groove 5. However, in this embodiment, the entire side surface and bottom surface of the groove 5 include a p-type dopant as an electric field relaxation layer. The electrode layer 50 is formed.
[0069]
FIG. 10 shows an electric field distribution when the vertical power MOSFET in FIG. 9 is used. As shown in this figure, it can be seen that the electric field terminates at the bottom surface of the groove 5 instead of the side surface of the groove 5 constituting the mesa structure. That is, by forming the electrode layer 50, the electric field concentration on the side surface of the groove 5 is moved to the bottom surface side of the groove 5.^-Depletion layer generated at the pn junction in the silicon carbide semiconductor layer 2^-In the type silicon carbide semiconductor layer 2, an avalanche breakdown is caused.
[0070]
Thus, in addition to the side surface of the groove 5 constituting the mesa structure, by forming the electrode layer 50 entirely on the bottom surface of the groove 5, electric field concentration does not occur on the side surface and bottom surface of the groove 5. A dielectric breakdown of the thermal oxide film 9 caused by electric field concentration can be prevented, and a vertical power MOSFET having a high breakdown voltage and a high avalanche breakdown voltage can be obtained.
[0071]
In the present embodiment, the electrode layer 50 is formed of an electrode layer containing a p-type dopant, but the electrode layer 50 may be formed of a silicon carbide layer. In this case, since the portion of the electrode layer 50 made of the silicon carbide layer is always depleted, the same effect as in the case of the electrode layer 50 containing the p-type dopant can be obtained.
Further, even when a metal such as Al—Ti is applied as the electrode layer 50, the same effect as described above can be obtained. When a metal such as Al—Ti is applied, the electric field relaxation layer can be formed by ion implantation of aluminum. For this reason, since the electric field relaxation layer can be formed by ion implantation without using epitaxial growth like a silicon carbide layer, the process for forming the electric field relaxation layer can be simplified.
[0072]
(Fifth embodiment)
Next, a fifth embodiment according to the present invention will be described with reference to FIG.
In the first embodiment described above, the side surface of the groove 5 constituting the mesa structure and the carrier forming region are connected by the p-type silicon carbide semiconductor layer 3. However, in this embodiment, the side surface of the groove 5 and the cell region are connected. By forming the groove 70 between the two, the side surface of the groove 5 and the carrier forming region are electrically separated (insulated and separated).
[0073]
That is, p-type silicon carbide semiconductor layer 3 and n^-Among the pn junctions formed by the silicon carbide semiconductor layer 2, the pn junction between the groove 70 and the groove 5 (hereinafter referred to as a side surface pn junction) and the pn junction between the groove 70 and the groove 7 (hereinafter referred to as “side junction pn junction”) Cell-side pn junction). The groove 70 is formed to be the same as or shallower than the groove 7, so that the electric field concentration in the thermal oxide film 9 formed in the groove 70 is reduced.
[0074]
FIG. 12 shows an electric field distribution when the vertical power MOSFET in FIG. 11 is used. If the side surface side of the groove 5 and the cell region side are electrically separated, the channel region and the region that gives the device withstand voltage can be separated, resulting in an electric field distribution as shown in FIG. When a high voltage is applied to the drain electrode 13, an avalanche breakdown current flows through the side pn junction, so that element breakdown at the cell side pn junction hardly occurs. As a result, it is possible to prevent the cell region from being damaged by the avalanche breakdown current flowing in the cell region, so that the lifetime of the vertical power MOSFET can be improved.
[0075]
(Sixth embodiment)
Next, a sixth embodiment to which the present invention is applied will be described with reference to FIG.
In the first embodiment described above, n is formed on the side surface of the groove 5 constituting the mesa structure.^-The type silicon carbide semiconductor layer 6 is formed, thereby preventing electric field concentration on the side surface of the trench 5 to prevent the dielectric breakdown of the thermal oxide film 9. In this embodiment, the silicon carbide semiconductor layer 6 is located at the bottom of the trench 5. n^-P-type silicon carbide semiconductor layer 80 is formed on the surface layer portion of silicon carbide semiconductor layer 2, and thermal oxide film 9 is broken down by p-type silicon carbide semiconductor layer 80 before thermal oxide film 9 causes dielectric breakdown. Prevents dielectric breakdown.
[0076]
Specifically, the vertical power MOSFET in the present embodiment includes the p-type silicon carbide semiconductor layer 80 described above. And n⁺The source region 12 is extended to the inside of the trench 5 and n through the contact hole formed in the insulating film 11 and the thermal oxide film 9.⁺Type source region 12 and p type silicon carbide semiconductor layer 80 are electrically connected. That is, p-type silicon carbide semiconductor layer 80 and n⁺The type source region 12 is set to the same potential.
[0077]
n^-Regarding the thickness of type silicon carbide semiconductor layer 2, the thickness L <b> 2 is thicker in the thickness L <b> 1 where the groove 5 is formed and the thickness L <b> 2 where the groove 5 is not formed. This is n^-It shows that the breakdown voltage in the silicon carbide semiconductor layer 2 is larger in the portion of the thickness L2 than in the portion of the thickness L1.
Therefore, p-type silicon carbide semiconductor layer 80 and n^-Pn junction (hereinafter referred to as an auxiliary junction) by p-type silicon carbide semiconductor layer 2, p-type silicon carbide semiconductor layer 3 and n^-When comparing a pn junction (hereinafter referred to as a main junction) with the silicon carbide semiconductor layer 2, the auxiliary junction breaks down at a lower voltage than the main junction.
[0078]
Thus, since breakdown occurs in the outer region separated from the cell region, it is possible to prevent the dielectric breakdown of the thermal oxide film 9 on the side surface of the groove 5 constituting the mesa structure. Further, unlike the dielectric breakdown of the thermal oxide film 9, the portion where the avalanche breakdown occurs is a breakdown in the semiconductor, so that the vertical power MOSFET does not fail even after the breakdown. For this reason, it can be set as the vertical power MOSFET which a permanent failure does not produce easily.
[0079]
(Seventh embodiment)
Next, a seventh embodiment to which the present invention is applied will be described with reference to FIG.
In the present embodiment, a structure capable of preventing the dielectric breakdown of the thermal oxide film 309 at the corner of the groove 5 formed at the periphery of the cell region will be described.
As shown in FIG. 14, a p-type layer region 201 is formed on the side closest to the cell region (groove corner side) of the bottom surface of the trench 5 formed in the trench gate type vertical power MOSFET. Yes. Since this p-type layer region 201 functions as a guard ring, the depletion layer can be extended to the periphery of the p-type layer region 201 as shown by the equipotential line (dotted line portion) in FIG.
[0080]
Specifically, when the electric field strength distribution at the AA cross section in FIG. 14 and the electric field strength at the BB cross section in FIG. 28 were examined, the results shown in FIGS. 15A and 15B, respectively. was gotten. As is clear from these figures, the electric field strength distribution at the corners of the groove 5 has a lower maximum electric field strength than the conventional case where the p-type layer region 201 is not formed, It can be seen that the electric field concentration is relaxed.
[0081]
For this reason, the electric field concentration at the corner of the groove 5 is relaxed, and the thermal oxide film 9 in this portion can be prevented from being broken down. Thereby, the breakdown voltage of the semiconductor device can be improved.
In the present embodiment, the p-type layer region 201 is formed only on the bottom surface of the corner of the groove 5, but the electric field concentration can be further reduced if the p-type layer region 201 is formed so as to cover the entire corner.
[0082]
Further, in the present embodiment, a case is shown in which the side surface of the groove 5 where electric field concentration is particularly likely to occur at the corner of the groove 5 is substantially perpendicular to the substrate surface, but the side surface of the groove 5 has a tapered shape. It can also be applied to cases.
Next, a method for manufacturing the vertical power MOSFET shown in FIG. 14 will be described based on the manufacturing process diagrams shown in FIGS. Only parts different from the method of manufacturing the vertical power MOSFET shown in the first embodiment will be described, and common parts will be omitted. In this figure, the case where the side surface of the groove 5 where electric field concentration is likely to occur at the corner of the groove 5 is substantially perpendicular to the substrate surface will be described.
[0083]
First, after the process shown in FIG. 3A, as shown in FIG. 16A, dry etching is performed to penetrate the p-type silicon carbide semiconductor layer 3 and n⁺A trench 5 reaching the mold source region 2 is formed.
Next, as shown in FIG. 16B, after a photo process, regions other than the corners of the trench 5 are covered with a mask material 200, and then p-type impurities are ion-implanted to form a p-type layer region. .
[0084]
Thereafter, as shown in FIG. 16C, epitaxial growth is performed, and the epitaxial growth layer is oxidized to form n on the side surface of the trench 5.^-A high resistance layer 6 made of a type silicon carbide semiconductor is formed. Thereafter, the vertical power MOSFET in this embodiment is completed through the steps shown in FIGS.
(Eighth embodiment)
Next, an eighth embodiment to which the present invention is applied will be described. In the present embodiment, the breakdown voltage can be improved when the field plate structure is employed in the outer peripheral region of the cell region. FIG. 17 shows a silicon carbide semiconductor device according to this embodiment.
[0085]
As shown in FIG. 17, in this embodiment, a planar type MOSFET is formed in the cell region. The overall structure of the planar type MOSFET is different from that of the trench gate type MOSFET shown in FIG. 1 in that a thin film layer 304 for forming a channel is formed without forming a groove. Since the other points are almost the same, only the different points will be specifically described, and the same parts will be omitted.
[0086]
Planar MOSFET is n⁺Type silicon carbide semiconductor substrate 301 and n^-N-type silicon carbide semiconductor layer 302 as a substrate, n^-A plurality of p-type silicon carbide semiconductor layers (hereinafter referred to as p-type base regions) 303 formed on the surface layer portion of type silicon carbide semiconductor layer 302 and a surface channel layer 304 parallel to the substrate surface. When a positive voltage is applied to the gate electrode 306, a channel is formed in the surface channel layer 304, and transistor operation is performed. Reference numeral 312 denotes a source electrode, and reference numeral 313 denotes a drain electrode. Reference numeral 320 denotes a gate electrode electrically connected to the gate electrode layer 306.
[0087]
A p-type region 307 for preventing breakdown and an electrode 322 forming a field plate are provided in the outer peripheral region of the cell region. The p-type region 307 is n^-It is formed in the surface layer portion of the type epitaxial layer 302 and is in contact with the electrode 322 through a contact hole formed in the insulating film 309.
The electrode 322 extends toward the outside of the cell region. Since the electrode 322 is equipotential, the depletion layer extends to the outer periphery of the cell region, so that the breakdown voltage can be improved.
[0088]
Furthermore, n below the electrode 322 forming the field plate is n^-On top of the type epitaxial layer 302, n^-N whose impurity concentration is lower than that of the epitaxial layer 302^-A type thin film layer (thin film semiconductor layer) 308 is provided. Specifically, n^-The impurity concentration of the type epitaxial layer 302 is 2 × 10¹⁶cm^-3And n^-The mold thin film layer 308 has an impurity concentration of 1 × 10¹⁵cm^-3The film thickness is 0.3 μm. N^-The width of the mold thin film layer 308 in the direction away from the cell region is such that the depletion layer is n even when a reverse bias is applied between the drain electrode 313 and the source electrode 312.^-It terminates in the mold thin film layer 308.
[0089]
N^-The mold thin film layer 308 is basically formed around the semiconductor device so as to surround the cell region over the entire semiconductor device.
Equipotential lines shown when a reverse bias is applied to the planar MOSFET configured in this way are indicated by dotted lines in FIG. Thus, n^-Mold thin film layer 308 is formed, and n^-Type thin film layer 308 is n^-Since the concentration is lower than that of the type epitaxial layer 2, it is possible to increase the lateral extension of the depletion layer when the reverse bias is applied.
[0090]
For reference, n^-18A and 18B show the results of measuring the maximum electric field strength in the depth direction below the field plate when the mold thin film layer 308 is formed and not formed, respectively.
When the distance shown in FIG. 18 is zero (Distance = 0), that is, when the maximum electric field strength at the interface of the thermal oxide film 309 is compared, it is 1.05 MV / cm in FIG. In (b), since it is 1.25 mv / cm, n^-It can be seen that the maximum electric field strength can be reduced by about 20% by forming the mold thin film layer 308.
[0091]
Thus, the electric field strength at the interface of the thermal oxide film 309 can be reduced, and the thermal oxide film 309 can be prevented from being broken down.
The p-type base region 303 is formed with a partially deep junction depth. By forming the region (second base region) 303a having a deep junction depth, the curvature of the bottom of the p-type base region 303 can be reduced, and the electric field strength can be increased. Therefore, an avalanche breakdown can be easily generated in this region 303a, and the breakdown voltage can be determined in the region 303a of the p-type base region 303 of the planar MOSFET. Note that the formation position of the region 303a can be set arbitrarily, so that the parasitic transistor formed by the planar MOSFET can be formed at a position where it is difficult to operate. If it does in this way, the back electromotive energy tolerance at the time of L load drive can be made high.
[0092]
In addition, n shown in FIG. 17, FIG. 20, and FIG.^-N connected to the mold thin film layer 308⁺The mold region 311 and the electrode 323 are called equipotential rings (EQR), and are used to make the potential of the semiconductor device around the semiconductor device equal throughout the semiconductor device. Basically, these are formed to surround the cell region around the semiconductor device, and the potential is a floating potential. In this embodiment, n⁺The mold region 311 is n^-Although connected to the mold thin film layer 308, it may be separated.
[0093]
Next, a method for manufacturing the planar MOSFET shown in FIG. 17 will be described with reference to FIGS.
[Step shown in FIG. 19 (a)]
Low resistance n⁺Type silicon carbide semiconductor substrate 301 is prepared.⁺High resistance n on the silicon carbide semiconductor substrate 301^-Type silicon carbide semiconductor layer 302 is epitaxially grown.
[0094]
[Step shown in FIG. 19B]
n^-Of the surface layer portion of type silicon carbide semiconductor layer 302, ion implantation is performed in a cell formation scheduled region to form p type base layer 303.
[Step shown in FIG. 19 (c)]
n including on the p-type base layer 303^-Impurity concentration is n by epitaxial growth on silicon carbide semiconductor layer 302^-N lower than that of the type silicon carbide semiconductor layer 302^-A mold thin film layer 350 is formed. This n^-The mold thin film layer 350 constitutes the surface channel layer 304 for channel formation and plays a role of reducing the electric field strength at the interface of the thermal oxide film 309 as described above.^-A mold thin film layer 308 is formed.
[0095]
Thus, the step of forming the surface channel layer 304 for channel formation, and n^-By combining the step of forming the mold thin film layer 308, the number of steps can be increased without increasing the number of steps.^-A mold thin film layer 308 can be formed.
[Step shown in FIG. 20 (a)]
An n-type impurity is ion-implanted, and n is implanted into a predetermined region on the p-type base layer 303.⁺N for contact with the mold source region 305 and a predetermined region of the outer peripheral region⁺A mold layer 311 is formed.
[0096]
[Step shown in FIG. 20B]
A p-type impurity is ion-implanted, and in the unit cell region, n is formed on the p-type base layer 303 so as to make contact with the p-type base layer 303^-Of the mold thin film layer 304, except for the portion where the channel is formed (in the figure, n⁺The p-type region 307 for preventing breakdown is formed in the outer peripheral region.
[0097]
At this time, ion implantation is performed so that the p-type impurity is implanted deeper than the p-type base region 303. For this reason, the p-type base region 303 includes a region 303a that is partially deeply formed. Thereby, an avalanche breakdown can be easily caused in a deeply formed portion of the p-type base region 303. The formation position of the region 303a can be arbitrarily changed by changing the ion implantation mask position.
[0098]
Note that although the region 303a is formed here, the formation of this region 303a is optional and may not be formed. In such a case, if the p-type region 307 is formed at the same time as the p-type base region 303, the process for forming the p-type region 307 can be simplified, so that the manufacturing process can be simplified. It is also possible to form the p-type region 307 at the same time as the p-type base region 303 and to form only the necessary position of the p-type region 307 at the same time as the region 303a, thereby increasing the junction depth of that portion. It is.
[0099]
[Step shown in FIG. 20 (c)]
Through a photolithography process, an oxide film (SiO 2 having a predetermined thickness is formed on the p-type region 307.₂) 360 is formed.
[Step shown in FIG. 21 (a)]
A thermal oxide film 309 is formed on the entire surface of the wafer by thermal oxidation. This thermal oxide film 309 forms a gate oxide film. Then, after depositing polysilicon or the like, the gate electrode 306 is formed by patterning.
[0100]
[Step shown in FIG. 21B]
An interlayer insulating film 318 is formed on the wafer including the thermal oxide film 309.
Thereafter, after forming a contact hole in the interlayer insulating film 318, the aluminum wiring is patterned to form a gate electrode 320, a source electrode 312 and an electrode 322 to be a field plate. Then, a passivation film 370 is formed on the gate electrode 320, the source electrode 312 and the electrode 322, and further a drain electrode 313 is formed on the back surface of the wafer, thereby completing the planar MOSFET shown in FIG.
[0101]
(Ninth embodiment)
Next, a ninth embodiment to which the present invention is applied will be described. In the present embodiment, the breakdown voltage can be improved when the guard ring structure is employed in the outer peripheral region of the cell region. FIG. 22 shows a silicon carbide semiconductor device according to this embodiment.
[0102]
As shown in FIG. 22, in this embodiment, a planar type MOSFET is used as the cell region. Since the overall configuration of the planar MOSFET is the same as that of FIG. 17, the same reference numerals as those of FIG.
A peripheral region of the cell region is provided with a p-type region 307 for preventing breakdown and a p-type region 409 having a predetermined width constituting a guard ring so as to surround the cell region. The p-type region 307 and the p-type region 409 are n^-Formed on the surface layer portion of type silicon carbide semiconductor layer 302. A plurality of p-type regions 409 are formed and are arranged at predetermined intervals from the p-type region 307 toward the outside of the unit cell region.
[0103]
Of the p-type region 409, the one located farthest from the cell region is electrically connected to the electrode 410 constituting the field plate.
Further, between each of the plurality of p-type regions 409 constituting the guard ring, between the p-type region 407 and the p-type region 409, and outside the cell region from the p-type region 409 located at the outermost periphery. (On the side away from the cell region), n^-N-type silicon carbide semiconductor layer 302 has n^-N whose impurity concentration is lower than that of the epitaxial layer 302^-A mold thin film layer 408 is provided. Specifically, n^-The mold thin film layer 408 has an impurity concentration of 1 × 10¹⁶cm^-3The film thickness is 0.3 μm.
[0104]
The equipotential lines shown when a high voltage is applied to the drain of the planar MOSFET configured in this way are represented by dotted lines in FIG. Thus, n^-Mold thin film layer 408 is formed and n^-Type thin film layer 408 is n^-Since the concentration is lower than that of type silicon carbide semiconductor layer 302, it is possible to increase the lateral extension of the depletion layer.
[0105]
Thus, the electric field strength at the interface of the oxide film can be reduced, and the thermal oxide film 309 can be prevented from being broken down.
Next, a method for manufacturing the planar MOSFET shown in FIG. 22 will be described with reference to FIGS.
[Step shown in FIG. 23 (a)]
Low resistance n⁺Type silicon carbide semiconductor substrate 301 is prepared.⁺High resistance n on the silicon carbide semiconductor substrate 301^-Type silicon carbide semiconductor layer 302 is epitaxially grown.
[0106]
[Step shown in FIG. 23B]
n^-In the surface layer portion of type silicon carbide semiconductor layer 302, p type base layer 303 is formed in the unit cell formation scheduled region.
[Step shown in FIG. 23 (c)]
n including on the p-type base layer 303^-N-type silicon carbide semiconductor layer 302 by epitaxial growth^-A mold thin film layer 450 is formed. This n^-The mold thin film layer 450 constitutes the surface channel layer 304 for channel formation, and also serves to reduce the electric field strength at the interface of the thermal oxide film 309 as described above.^-A mold thin film layer 408 is formed.
[0107]
[Step shown in FIG. 24 (a)]
An n-type impurity is ion-implanted, and n is implanted into a predetermined region on the p-type base layer 303.⁺N for contact with the mold source region 305 and a predetermined region of the outer peripheral region⁺A mold layer 311 is formed.
[Step shown in FIG. 24B]
A p-type impurity is ion-implanted, and in the unit cell region, n is formed on the p-type base layer 303 so as to make contact with the p-type base layer 303^-Of the mold thin film layer 304, except for the portion where the channel is formed (in the figure, n⁺The p-type region 307 for preventing breakdown is formed in the outer peripheral region, and a guard link is formed from the p-type region 307 toward the outside of the unit cell region. A plurality of p-type regions 409 are formed.
[0108]
At this time, by ion implantation so that the p-type impurity is implanted deeper than the p-type base layer 305, the p-type base region 305 can be partially formed deeply, and the breakdown voltage of the element can be improved. .
[Step shown in FIG. 24 (c)]
Through a photolithography process, an oxide film (SiO 2 having a predetermined thickness is formed on the p-type region 307.₂) 360 is formed.
[Step shown in FIG. 25 (a)]
A thermal oxide film 309 is formed on the entire surface of the wafer by thermal oxidation. This thermal oxide film 309 forms a gate oxide film. Then, after depositing polysilicon or the like, a gate electrode is formed by patterning.
[0109]
[Step shown in FIG. 25 (b)]
An interlayer insulating film 318 is formed over the wafer including the gate insulating film.
Thereafter, after forming a contact hole in the interlayer insulating film 318, the aluminum wiring is patterned to form the gate electrode 320, the source electrode 312 and the electrode 22 constituting the field plate. Then, a passivation film 370 is formed on the gate electrode 320, the source electrode 312, and the electrode 410, and n⁺A drain electrode 313 is formed on the back surface of type silicon carbide semiconductor substrate 301 to complete the planar MOSFET shown in FIG.
[0110]
(Other embodiments)
In addition, for example, n⁺Source electrode 12 formed on p-type source region 4 and p-type silicon carbide semiconductor layer 3, and n⁺Drain electrode 13 formed on the back surface of type silicon carbide semiconductor substrate 1 may be an electrode other than Ni.
In the above-described embodiment, the case where the present invention is applied to an n-channel vertical MOSFET has been described. However, the present invention may be applied to a p-channel vertical MOSFET, and further to a substrate regardless of a vertical type or a horizontal type. The present invention may be applied to a MOSFET in which the groove 7 is not dug.
[0111]
Further, the grooves 7 and 5 may be perpendicular to the substrate surface, V-groove type, or U-groove type. Further, the groove side surface does not have to be flat and may be a smooth curved surface.
In the first to seventh embodiments, the vertical power MOSFET using silicon carbide as the substrate has been described. However, the present invention is applied to a semiconductor device using a silicon substrate as the substrate. You can also.
[0112]
In the first embodiment, the mesa-shaped groove 5 and the groove 7 to be a channel region formed in the cell region are formed in separate steps. However, as shown in JP-A-9-74193, the side surface of the groove 7 is formed. In the case of forming a high resistance semiconductor layer to be a channel region, the high resistance semiconductor layer and the high resistance layer 6 can be formed at the same time, so that a special process for forming the groove 5 is not required. If it demonstrates using drawing, the semiconductor substrate 100 will be prepared as shown to Fig.3 (a), and the groove | channel 5 and the groove | channel 7 will be formed as shown to Fig.14 (a). Thereafter, the semiconductor device shown in FIG. 14B is formed by a process similar to that shown in FIG. In this way, a semiconductor device in which the groove 5 and the groove 7 are simultaneously formed can be completed.
[0113]
Even when the p-type layer region 201 is formed at the corner of the groove 5 as in the sixth embodiment, a high-resistance semiconductor layer serving as a channel region can be formed on the side surface of the groove 7. The high-resistance semiconductor layer and the high-resistance layer 6 serving as the channel region can be formed simultaneously.
In the eighth and ninth embodiments, n is formed before the p-type regions 307, 407, and 409 are formed.^-Although the mold thin film layers 304 and 404 are formed, they may be formed later.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a vertical power MOSFET in a first embodiment according to the present invention.
2 is a diagram showing an electric field distribution of the vertical power MOSFET shown in FIG. 1. FIG.
3 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 1. FIG.
4 is a diagram showing manufacturing steps subsequent to FIG. 3. FIG.
FIG. 5 is a diagram showing a manufacturing process subsequent to FIG. 4;
FIG. 6 is a cross-sectional view of a vertical power MOSFET in a second embodiment according to the present invention.
7 is a diagram showing an electric field distribution of the vertical power MOSFET shown in FIG. 6. FIG.
FIG. 8 is a sectional view of a vertical power MOSFET in a third embodiment according to the present invention.
FIG. 9 is a sectional view of a vertical power MOSFET in a fourth embodiment according to the present invention.
10 is a diagram showing an electric field distribution of the vertical power MOSFET shown in FIG. 9. FIG.
FIG. 11 is a cross-sectional view of a vertical power MOSFET according to a fifth embodiment of the present invention.
12 is a diagram showing an electric field distribution of the vertical power MOSFET shown in FIG. 11. FIG.
FIG. 13 is a sectional view of a vertical power MOSFET in a sixth embodiment according to the present invention.
FIG. 14 is a cross-sectional view of a vertical power MOSFET in a sixth embodiment according to the present invention.
15 is a diagram comparing electric field distributions of the vertical power MOSFET shown in FIG. 14 and a conventional vertical power MOSFET. FIG.
16 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 16;
FIG. 17 is a sectional view of a vertical power MOSFET in a seventh embodiment according to the present invention.
18 is a diagram comparing electric field distributions of the vertical power MOSFET shown in FIG. 14 and a conventional vertical power MOSFET. FIG.
FIG. 19 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 17;
20 is a diagram showing the manufacturing process of the vertical power MOSFET following FIG. 19. FIG.
FIG. 21 is a diagram showing the manufacturing process of the vertical power MOSFET following that of FIG. 20;
FIG. 22 is a sectional view of a vertical power MOSFET in an eighth embodiment according to the present invention.
FIG. 23 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG. 22;
FIG. 24 is a diagram illustrating the manufacturing process of the vertical power MOSFET following that of FIG. 23;
25 is a diagram showing the manufacturing process of the vertical power MOSFET following that of FIG. 24. FIG.
FIG. 26 is a diagram showing a manufacturing process of the vertical power MOSFET in another embodiment.
FIG. 27 is a diagram showing an electric field distribution of a vertical power MOSFET having a conventional mesa structure.
FIG. 28 is a diagram showing an electric field distribution of a vertical power MOSFET having a conventional mesa structure.
FIG. 29 is a diagram showing an electric field distribution of a vertical power MOSFET employing a conventional field plate structure.
[Explanation of symbols]
1 ... n⁺Type silicon carbide semiconductor substrate, 2... N^-Type silicon carbide semiconductor layer,
3 ... p-type silicon carbide semiconductor layer, 4 ... n⁺Type source area,
5 ... groove constituting mesa structure, 6 ... high resistance layer, 7 ... groove, 9 ... thermal oxide film,
DESCRIPTION OF SYMBOLS 10 ... Gate electrode, 11 ... Insulating film, 12 ... Source electrode, 13 ... Drain electrode,
30 ... p-type silicon carbide semiconductor layer, 40 ... electrode layer, 50 ... electrode layer, 70 ... groove,
80 ... p-type silicon carbide semiconductor layer, 201 ... p-type layer region,
301 ... n⁺Type silicon carbide semiconductor substrate, 302... N^-Type silicon carbide semiconductor layer,
303 ... p-type base region, 304 ... surface channel layer,
305 ... n⁺Type source region, 306... Gate electrode layer, 307... P type region,
308 ... n^-Type thin film layer, 309 ... thermal oxide film, 312 ... source electrode,
313 ... Drain electrode, 320 ... Gate electrode, 322 ... Electrode,
408 ... n^-Type thin film layer, 409... P-type region.

Claims (4)

A first conductivity type low resistance layer (1), a first conductivity type first semiconductor layer (2) formed on the low resistance layer and having a higher resistance than the low resistance layer, and the first conductivity type A semiconductor substrate (100) having a second conductivity type second semiconductor layer (3) formed on the semiconductor layer and having a surface of the second semiconductor layer as a main surface;
A first-conductivity-type semiconductor region (4) formed in the second semiconductor layer and formed such that a junction portion terminates at the main surface;
A first groove (7) that penetrates the semiconductor region and the second semiconductor layer from the main surface and constitutes a cell portion;
A second groove (5) formed to surround the first groove and forming a mesa structure through the second semiconductor layer;
Formed on a side surface of the second groove (5) so as to be disposed between a boundary portion of the first semiconductor layer and the second semiconductor layer and a side surface of the second groove (5). And an electric field relaxation layer ( 6 ) made of a first conductivity type material having a higher resistance than that of the first semiconductor layer ,
An insulating film (9) formed on the main surface including the surface of the electric field relaxation layer and the first groove (7);
A gate electrode (10) formed inside the insulating film in the first trench;
A first electrode (12) in electrical contact with the semiconductor region;
A second electrode (13) in electrical contact with the back side of the semiconductor substrate;
At the time of breakdown, an electric field concentration in the insulating film is caused by the electric field relaxation layer by causing an avalanche breakdown in the vicinity of a region where the electric field relaxation layer, the first semiconductor layer (2), and the second semiconductor layer intersect. A semiconductor device characterized by being relaxed.   An electrode layer (40) connected to the first electrode is provided on the surface of the insulating film formed on the surface of the electric field relaxation layer, and the electric field relaxation layer is made to have a predetermined threshold voltage by the electrode layer. The semiconductor device according to claim 2, wherein a low voltage is set. 3. The semiconductor device according to claim 1, wherein the low resistance layer, the first semiconductor layer, the second semiconductor layer, and the electric field relaxation layer are made of silicon carbide. Semiconductor device. A first conductivity type low resistance layer (1), a first conductivity type first semiconductor layer (2) formed on the low resistance layer and having a higher resistance than the low resistance layer, and the first conductivity type Forming a semiconductor substrate (100) having a second semiconductor layer (3) of the second conductivity type formed on the semiconductor layer and having the surface of the second semiconductor layer as a main surface;
Forming a first conductivity type semiconductor region (4) having a junction terminated at the main surface in the second semiconductor layer;
Forming a mesa structure forming groove (5) constituting a mesa structure penetrating the second semiconductor layer from the main surface;
Forming at least a side in the electric field relaxation layer of the first first conductivity type material and a higher resistance than the semiconductor layer (6) of the mesa structure forming grooves,
Forming a cell forming groove (7) constituting a cell portion penetrating from the main surface through the semiconductor region and the second semiconductor layer after forming the electric field relaxation layer;
Forming an insulating film (9) on the surface of the second semiconductor layer including the mesa structure forming groove and the cell portion forming groove;
Forming a gate electrode (10) inside the insulating film in the cell portion forming groove;
Forming a first electrode (11) in electrical contact with the semiconductor region;
Forming a second electrode (13) in electrical contact with the back side of the semiconductor substrate ,
In the step of forming the electric field relaxation layer (6), at the time of breakdown, to cause avalanche breakdown in the region near where the electric field relaxation layer and the front Symbol first semiconductor layer (2) and said second semiconductor layer intersect The method of manufacturing a semiconductor device, wherein the electric field relaxation layer (6) is formed of a semiconductor layer that relaxes electric field concentration in the insulating film .

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