JP2007258742A - High breakdown-voltage semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a semiconductor device, having high reliability which has high-breakdown voltage and low ON-voltage. <P>SOLUTION: The semiconductor device includes p-type layers formed by an epitaxial method and used for electric charge injection; and both a mesa structure used for relieving an electric field when a reverse bias is applied and a JTE formed by ion implantation, wherein a mesa slope and a mesa bottom surface which are in the minimum distance from a corner of a passivation film constituted of an inorganic film are constituted of the p-type layers. An impurity concentration of the p-type layers, formed on a mesa corner and the mesa bottom surface, is set at a prescribed range, and the thickness of the passivation film at least on the mesa corner part is made at least ≥0.5 μm. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high withstand voltage power semiconductor device that controls a large current.

  Wide gap semiconductor materials such as silicon carbide (SiC) have excellent characteristics such as about 10 times higher dielectric breakdown field strength than silicon (Si), and high withstand voltage power with high reverse voltage resistance. It attracts attention as a material suitable for semiconductor devices. However, the diffusion coefficient of SiC impurities is much smaller than that of Si. Therefore, advanced technology is required to manufacture a semiconductor device using SiC. In particular, it has been difficult to realize a high voltage semiconductor device having a high voltage pn junction.

  As a conventional wide gap high breakdown voltage semiconductor device using SiC, for example, there is a high breakdown voltage diode having a planar structure as shown in the cross-sectional view of FIG. 9, which has a breakdown voltage of about 3.4 KV. This high-breakdown-voltage diode is disclosed on pages 136 to 137 (Non-patent Document 1) of a draft of the 1997 International Conference on Silicon Carbide, III-Nitride and Related Materials. In this conventional example, the n-type drift layer 2 is formed on the other surface of the drain region 1 of the n-type SiC having the cathode electrode 50 on one surface, and the p-type layer 3 is formed in the central portion of the n-type drift layer 2. is doing. An anode electrode 51 is provided on the p-type layer 3. Termination p-type layers 34 are formed on both sides of the p-type layer 3. “Termination” refers to a special structure in the vicinity of the end portion in order to suppress electric field concentration at the end portion of the high voltage semiconductor element. Between the pn junction between the p-type layer 3 and the n-type drift layer 2 for injecting electric charge to flow current, and between the termination p-type layer 34 and the n-type drift layer 2 for relaxing the electric field. The pn junction is formed by an ion implantation technique such as boron or aluminum.

  As another conventional example, there is a high voltage diode shown in the cross-sectional view of FIG. In this conventional example, a pn junction between the p-type layer 13 for injecting charges and the n-type drift layer 2 is formed by an epitaxial growth technique, and a termination region T for relaxing an electric field is formed by mesa etching. The breakdown voltage is about 4.5 kV. This high voltage diode is disclosed in the 1995 academic journal Applied Physics Letter, Vol. 67, pages 1561 to 1563 (Non-patent Document 2). As shown in the cross-sectional view of FIG. 10, this high breakdown voltage diode is formed by mesa etching of both end portions of the p-type epitaxial layer 13 having a thickness of 1.5 μm formed on the entire surface of the n-type drift layer 2 to a depth of 2 μm. Remove. The surface is protected by a silicon dioxide film (hereinafter referred to as a passivation film) 10 having a thickness of 0.4 μm except for the portion having the anode electrode 51.

FIG. 11 is a cross-sectional view of a high voltage diode described in pages 1600 to 1601 (non-patent document 3) of the annual conference of the Institute of Electrical Engineers of Japan [4]. In the drawing, a p-type layer 3 is formed by an epitaxial growth technique in a region on the left side of an n-type drift layer 2 formed on an n-type SiC drain region 1, and an anode electrode 51 is provided on the p-type layer 3. Thereby, a pn junction for injecting charges is formed between the p-type layer 3 and the n-type drift layer 2. In order to form a termination region T for relaxing the electric field at the end portion of the semiconductor device, the region on the right side of the drawing is shallowly mesa-etched. A p-type layer 44 is formed in the vicinity of the mesa bottom surface 18 by ion implantation of boron, aluminum, or the like, and a pn junction is formed in the n-type drift layer 2. The termination region T and the region other than the anode electrode 51 of the p-type layer 3 are protected by a passivation film 6 having a thickness of about 0.4 μm.
Pages 136 to 137 of the 1997 International Conference on Silicon Carbide, III-Nitride and Related Materials 1995 Academic Journal Applied Physics Letter, Volume 67, pages 1561 to 1563 1600 to 1601 pages of the annual conference of the Institute of Electrical Engineers of Japan [4]

  In the case of the high breakdown voltage diode having the planar structure shown in FIG. 9, since the p-type layer 3 is formed by ion implantation, crystal defects are formed in and around the p-type layer 3. Therefore, the charge injection efficiency during forward bias (when the anode 51 is positive) is low, and the on-voltage is relatively high. In addition, the leakage current during reverse bias is large. Therefore, it is difficult to realize a semiconductor device with low loss and high breakdown voltage.

In the case of the diode of FIG. 10, since the p-type layer 3 is formed by the epitaxial growth method, there are few crystal defects and the charge injection efficiency at the time of forward bias is relatively high. The leak current at the time of reverse bias is also about 5 × 10 ⁻³ A / cm ² and is relatively small. However, if the reverse voltage exceeds 4.5 kV, it will break down and cannot be said to be a high breakdown voltage semiconductor device.

In the case of the diode of FIG. 11, since the p-type layer 3 is formed by the epitaxial growth method, there are few crystal defects and the charge injection efficiency at the time of forward bias is relatively high. Further, the leakage current at the time of reverse bias is as small as about 1 × 10 ⁻³ A / cm ² . Although the breakdown voltage is as high as 5.8 kV, a high electric field is applied to the passivation film 6 of the mesa corner portion 6A, so that a failure is likely to occur, and high reliability cannot be maintained for a long time.

  An object of the present invention is to provide a highly reliable semiconductor device with low on-voltage and high withstand voltage. In particular, in a wide gap semiconductor material such as SiC, the critical electric field value is close to the dielectric breakdown electric field value of the passivation film. Accordingly, it is an object of the present invention to solve the problem that when a passivation film is exposed to a high electric field for a long period of time, the leakage current increases and the reliability of the semiconductor device decreases.

  The high withstand voltage semiconductor device of the present invention includes a first conductivity type first layer (drift layer) formed on a substrate of a wide gap semiconductor material, and a second layer formed on the first layer by an epitaxial growth method. A second layer of a conductivity type (charge injection layer for charge injection), a first layer forming a mesa bottom surface of a mesa groove adjacent to the second layer, formed from the mesa bottom surface side, And a surface protective film formed on the termination region, the second layer, and the first layer, and the second layer, the first layer, A joining surface of the mesa groove that is higher than the bottom surface of the mesa, a mesa corner portion that is a portion where the mesa side surface of the mesa groove including the side surface of the second layer intersects the bottom surface of the mesa, and the termination region Between the end on the mesa corner side , The direction of thickness perpendicular to the mesa bottom surface of the surface protective film, than the distance between the mesa bottom and the joint surface, being greater.

  The thickness in the direction perpendicular to the mesa bottom surface of the surface protective film between the mesa corner portion and the end of the termination region on the mesa corner portion side is between the joint surface and the mesa bottom surface. The electric field at the mesa corner is not so high as compared with other parts. As a result, the reliability when used for a long time is improved.

  A semiconductor device according to another aspect of the present invention includes a first conductivity type first layer (drift layer) formed on a substrate of a wide gap semiconductor material, an epitaxial growth method formed on the first layer, A second layer of conductivity type (charge injection layer for charge injection), the first layer forming the mesa bottom surface of the mesa groove adjacent to the second layer, formed from the mesa bottom surface side; A second conductivity type termination region; and a surface protection film formed on the termination region, the second layer, and the first layer, and the second layer, the first layer, The end face of the termination region on the second layer side is on the mesa side surface of the mesa groove including the side surface of the second layer, The termination region has a mesa side surface and a mesa bottom surface. Characterized in that it covers the mesa corner portion is Waru moiety.

  The end of the termination region on the second layer side is on the mesa side surface, and the termination region covers the mesa corner portion, whereby the termination region in the vicinity of the mesa corner portion and the first region A depletion layer spreads from the junction with this layer toward the substrate. This depletion layer alleviates the electric field concentration on the surface protective film at the mesa corner, so that the withstand voltage is increased.

  A semiconductor device according to another aspect of the present invention includes a first conductivity type first layer (drift formed on the other surface of a substrate of a wide gap semiconductor material having a first electrode (drain electrode) on one surface. Layer), a second layer of a second conductivity type (body layer) formed on the first layer by an epitaxial growth method, and a first conductivity type of first layer formed on a part of the second layer. A trench formed so as to penetrate the first region and the second layer and reach the first layer, and a second formed on the inner wall surface of the trench via an insulating film An electrode (gate electrode), a second conductivity type termination region formed on the first layer forming the mesa bottom surface of the mesa groove adjacent to the second layer from the mesa bottom surface side, A third electrode (source electrode) formed over the region and the second layer, and the front It has a surface protection film formed on the side surfaces of the termination region, the first layer, and the second layer, and the bonding surface between the second layer and the first layer is higher than the mesa bottom surface. And the end of the termination region on the second layer side is on the mesa side surface of the mesa groove including the side surface of the second layer, and the termination region includes the mesa side surface and the mesa bottom surface. It is characterized by covering the mesa corner, which intersects with

  The end of the termination region on the second layer side is on the mesa side surface, and the termination region covers the mesa corner portion, thereby relaxing the electric field in the vicinity of the mesa corner portion. it can.

  In the semiconductor device of the present invention, the angle formed by the slope of the p-type layer near the mesa corner and the surface of the termination region is an obtuse angle. Then, the impurity concentration of the p-type layer is set within a predetermined range, and at least the passivation film in the mesa corner portion is made thicker than the distance between the junction surface of the p-type layer and the n-type drift layer and the mesa bottom surface. Thereby, the electric field concentration on the passivation film in the mesa corner portion is alleviated, and the withstand voltage and reliability of the semiconductor device are improved. Furthermore, by increasing the thickness of the passivation film, not only can the electric field concentration at the mesa corner of the film be reduced, but also the influence of local electric field concentration on the SiC surface due to alkali ions such as Na ions adhering to the surface of the passivation film. Can be relaxed. Furthermore, the influence of moisture and the like stays in the vicinity of the surface of the passivation film and hardly reaches the internal SiC.

  A preferred embodiment of the present invention will be described below with reference to FIGS. 1 to 8 are cross-sectional views of the right half of the semiconductor device of each embodiment, and the left half having a symmetric configuration with the right half configuration is not shown. Each semiconductor device has a long stripe shape in a direction perpendicular to the paper surface of each drawing.

<< First Example >>
FIG. 1 is a sectional view of a SiC (silicon carbide) pn diode having a breakdown voltage of 6.5 kV according to the first embodiment of the present invention. In the figure, a low impurity concentration n-type SiC drift layer 2 having a thickness of about 50 μm is formed on a drain region 1 having a thickness of about 350 μm and a high impurity concentration having a cathode electrode 50 on the lower surface. ing. A low impurity concentration p-type layer 3 for charge injection having a thickness of about 2 μm is formed on the left portion of the drift layer 2 by an epitaxial growth method. Drift layer 2 is etched shallowly by a kind of reactive ion etching method of mesa etching method to form termination region T. A p-type termination region (termination portion) 4 is formed by ion implantation of boron or aluminum into the surface of the termination region T. At the right end of the termination region T, an n-type channel stopper 5 is formed. In order to prevent alkali ions such as moisture and Na ions from adhering to the surface of the semiconductor device, the passivation film 16 is a surface protection film made of a thin film such as silicon dioxide or silicon nitride on the entire surface including the surface of the p-type termination region 4. Form. The thickness of most of the passivation film 16 is about 0.4 μm, but the film thickness at the mesa corner portion 20 at the boundary between the p-type layer 3 and the termination region 4 is significantly increased to 1 to 2 μm. . As a result, the region between the mesa corner portion 20 and the position A within the termination region T sufficiently separated from the mesa corner portion 20 is formed between the junction surface 3A of the p-type layer 3 and the drift layer 2 and the mesa bottom surface 18. It is covered with a passivation film 16 thicker than the distance L therebetween. The mesa angle θ, which is an angle formed between the side surface of the charge injection layer (3) and the mesa bottom surface 18, is 90 to 150 degrees.

In the SiC pn diode of this example, since the p-type layer 3 is formed by the epitaxial growth method, there are very few crystal defects. Therefore, when a voltage is applied in the forward direction (hereinafter referred to as a forward bias), a sufficient amount of holes are injected from the p-type layer 3 to the n-type drift layer 2, conductivity modulation occurs, and the on-voltage decreases. The on-voltage was 4.9 V when the current per unit area (current density) was 100 A / cm ² . When a voltage is applied in the reverse direction (hereinafter referred to as reverse bias), the junction electrode 3A between the p-type layer 3 and the n-type drift layer 2 is applied to the cathode electrode 50 and the anode electrode 51 provided on the p-type layer 3. The depletion layer spreads toward you. Since there are few crystal defects in the p-type layer 3, a critical electric field almost as the theoretical value can be obtained. When the applied voltage is increased, the depletion layer spreading in the drift layer 2 spreads to the rightmost region of the figure by the action of the p-type termination region 4. This depletion layer provides a high reverse withstand voltage. When the impurity concentration of the p-type termination region 4 is high, the electric field concentrates on the end portion 4A of the p-type termination region 4 that is far from the mesa corner portion 20.

On the other hand, when the impurity concentration of the p-type termination region 4 is low, the electric field of the p-type region 3 and the passivation film 16 in the vicinity of the mesa corner portion 20 becomes high. When the mesa angle θ is 90 degrees or less, the depletion layer does not spread so much in the p-type layer 3 in the vicinity of the mesa corner portion 20, and electric field concentration occurs in the mesa corner portion 20. On the other hand, when the mesa angle θ is 150 degrees or more, the electric field concentration in the mesa corner portion 20 is relaxed, but the electric field is concentrated on the passivation film 16, and the electric field in the drift layer 2 near the mesa corner portion 20 is caused by the interaction. Get higher. Therefore, when the impurity concentration of the p-type termination region 4 is in the range of 10 ¹⁶ to 10 ¹⁸ atm / cm ³ and the mesa angle is in the range of 90 to 150 degrees, the breakdown voltage is as high as 6.5 kV. In particular, when the impurity concentration of the p-type termination region 4 is about 5 × 10 ¹⁷ atm / cm ³ or less, a depletion layer spreads over the entire p-type termination region 4 when the cathode voltage is 6 kV. As a result, the voltage is shared across the entire p-type termination region 4, and a high breakdown voltage diode is obtained. If the passivation film 16 in the mesa corner portion 20 is as thin as the conventional passivation film 6 in FIG. 9, the electric field in the mesa corner portion 20 becomes a high electric field of 2 MV / cm, which is similar to the critical electric field of SiC. As a result, the leakage current increases and the reliability when used for a long time is deteriorated. In this embodiment, the passivation film 16 in the mesa corner portion 20 is thickened to 1 to 2 μm using PSG (Phospho-Silicate Grass) or the like. Thereby, the electric field of the mesa corner portion 20 can be set to 1 MV / cm or less, and the reliability when used for a long time is improved. The passivation film 16 may be formed of two or more kinds of materials.

<< Second Embodiment >>
FIG. 2 is a sectional view of a SiCpn diode having a breakdown voltage of 6.5 kV according to the second embodiment of the present invention. In the diode of this embodiment, the passivation film 26 in the entire termination region T is made thicker than the distance L between the bonding surface 3A and the mesa bottom surface 18 as compared with the diode of the first embodiment shown in FIG. Yes. The thickness is preferably 0.5 μm to 3 μm, but may be 3 μm or more. Other configurations are substantially the same as those of the first embodiment. By increasing the thickness of the passivation film 26, the electric field concentration at the mesa corner portion 20 can be alleviated and the breakdown voltage can be increased. Further, local electric field concentration on the surfaces of the drift region 2 and the p-type termination region 4 caused by alkali ions such as Na ions attached to the surface of the passivation film 26 can be reduced. Further, even if moisture or the like adheres to the surface of the passivation film 26, the moisture does not enter the inside, so that the influence can be prevented from reaching the inside. As a result, the high withstand voltage semiconductor device of the second embodiment is further improved in reliability when used for a long time.

<< Third embodiment >>
FIG. 3 is a sectional view of a SiCpn diode having a breakdown voltage of 6.9 kV according to the third embodiment of the present invention. In the diode of this embodiment, the p-type termination region 14 extends to the mesa corner portion 20. In the conventional high voltage semiconductor technology, it has been considered that the left end of the p-type termination region 14 needs to be separated from the p-type layer 3 in order to improve the forward characteristics. In this embodiment, ion implantation for forming the p-type termination region 14 is performed to the vicinity of the mesa corner portion 20 in the mesa slope region, and the left end portion of the p-type termination region 14 is connected to the p-type layer 3. It was confirmed by experiment that it was acceptable. In the experiment, a diode having this configuration was prototyped, and the forward characteristics of the diode were changed in the first case where the left end of the p-type termination region 14 and the p-type layer 3 were connected and in the second case where the p-type layer 3 was not connected. Examined. As a result, there was no difference in forward characteristics between the first case and the second case. It has been found that there is no adverse effect even if the left end of the p-type termination region 14 is connected to the p-type layer 3.

  Further, a passivation film 6 having a thickness of about 0.4 μm is formed on the entire surface of the termination region T including the p-type termination region 14. Other configurations are substantially the same as those of the first embodiment. With this configuration, in addition to the depletion layer described in the first embodiment, the junction between the p-type termination region 14 and the n-type drift layer 2 in the vicinity of the mesa corner portion 20 is also directed toward the cathode electrode 50. The depletion layer spreads. This depletion layer relaxes the electric field concentration on the passivation film 6 in the mesa corner portion 20 and increases the withstand voltage. When a reverse voltage of 3 KV was applied to the diode of this example, the electric field of the passivation film 6 in the mesa corner portion 20 was 0.19 MV / cm. Since the diode of the conventional example is about 1.3 MV / cm, the value of this example is reduced to about 15% of that of the conventional example. As a result, the high withstand voltage semiconductor device of this embodiment can achieve a high withstand voltage and can achieve higher reliability.

<< 4th Example >>
FIG. 4 is a sectional view of a SiCpn diode having a breakdown voltage of 6.9 kV according to the fourth embodiment of the present invention. In the diode of this embodiment, the entire passivation film 26 including the termination region T is made much thicker than the distance L between the bonding surface 3A and the mesa bottom surface 18 as compared with the diode of the third embodiment shown in FIG. ing. Its thickness is 2 μm to 3 μm. It may be 3 μm or more. Other configurations are substantially the same as those of the third embodiment. By thickening the passivation film 26, the electric field concentration in the mesa corner portion 20 can be reduced. Furthermore, the influence of alkali ions such as Na ions attached to the surface of the passivation film 26 on local electric field concentration on the SiC surface is alleviated. Furthermore, the influence of moisture or the like attached on the passivation film 26 remains in the vicinity of the surface of the passivation film 26 and does not reach the inside.

<< 5th Example >>
FIG. 5 is a sectional view of a SiC pn diode having a breakdown voltage of 7.5 kV according to a fifth embodiment of the present invention. The diode of this embodiment is obtained by dividing the p-type termination region 14 of the diode of the third embodiment shown in FIG. 3 into two regions 14A and 14B. Other configurations are the same as those of the third embodiment. The impurity concentration in the region 14A near the mesa corner portion 20 is higher than the impurity concentration in the far region 14B. When a positive voltage is applied to the cathode electrode 50, a depletion layer first spreads in the region 14A and withstands a reverse voltage by this depletion layer. When the positive voltage of the cathode electrode 50 is further increased, when the impurity concentration of the p-type termination region 14 is about 5 × 10 ¹⁷ atm / cm ³ or less, the depletion layers are formed in all the regions 14A and 14B of the p-type termination region 14. Spread and the voltage is shared by the regions 14A and 14B. Thereby, it is possible to prevent the electric field from concentrating on the end portion 14C of the p-type termination region 14 and to increase the breakdown voltage of the diode. Further, when the impurity concentration of the p-type termination region is higher than about 5 × 10 ¹⁷ atm / cm ³ , when the positive voltage of the cathode electrode 50 is further increased, a depletion layer spreads in the region 14B, but the upper layer of the region 14A The depletion layer does not spread in the part, and the voltage is shared by the lower part of the region 14B and the region 14A. For this reason, a large voltage is not applied to the mesa corner portion 20, and the electric field of the passivation film 6 in the mesa corner portion 20 is relaxed. Thereby, a highly reliable diode can be obtained.

<< Sixth embodiment >>
FIG. 6 is a sectional view of a SiC pn diode having a breakdown voltage of 7.5 kV according to the sixth embodiment of the present invention. In the diode of this embodiment, the p-type termination region 14 of the diode of the third embodiment shown in FIG. 3 is divided into a plurality of regions, for example, four regions 14D, 14E, 14F, and 14G. The regions 14D to 14G are separated from each other, and the regions 14D to 14G may be substantially the same size. However, it is desirable that the region 14D near the mesa corner portion 20 is larger than the other regions 14E to 14G. The impurity concentrations in the regions 14D to 14G are substantially the same. The impurity concentrations of the regions 14D to 14G may be different from each other. Other configurations are the same as those of the third embodiment. When a positive voltage is applied to the cathode electrode 50 of the diode of this embodiment, the depletion layer spreads from the region 14D of the p-type termination region 14 toward the region 14G, and the depletion layer withstands the reverse voltage. According to experiments, the breakdown voltage of the diode increased as the number of p-type regions 14D to 14G was increased. Since the plurality of p-type regions 14D to 14G and the drift layer 2 between them also share the voltage, the electric field of the passivation film 6 in the mesa corner portion 20 is relaxed, and a highly reliable diode can be realized.

<< Seventh embodiment >>
FIG. 7 is a sectional view of an n-channel SiC MOSFET having a breakdown voltage of 2500 V according to the seventh embodiment of the present invention. In the figure, the thickness of the high impurity concentration n-type drain region 11 having the drain electrode 52 on the lower surface is about 200 μm, and the thickness of the n-type drift layer 2 formed on the drain region 11 is about 20 μm. The p-type body layer 33 partially formed on the n-type drift layer 2 has a thickness of about 4 μm, and the n-type source layer 7 formed on a part of the p-type body layer 33 has a thickness of about 0.5 μm. is there. A trench (groove) 60 is formed substantially at the center of the p-type body layer 33. The depth of the trench 60 is about 6 μm and the width is about 3 μm. The thickness of the gate insulator layer 8 in the trench 60 is about 1 μm at the bottom of the trench 60 and about 0.1 μm at the side. In this embodiment, the trench 60 and the gate electrode 54 have a stripe shape extending in a direction perpendicular to the drawing sheet, but the shape may be, for example, a circle or a rectangle.

The manufacturing method of the MOSFET of this example is as follows. In FIG. 7, an n-type SiC substrate of 10 ¹⁸ to 10 ²⁰ atm / cm ^{3 that} functions as the drain region 11 is prepared, and an SiCn-type drift layer 2 of 10 ¹⁵ to 10 ¹⁶ atm / cm ³ is formed on the upper surface thereof by epitaxial growth. To do. An SiCp type body layer 33 of about 10 ¹⁶ atm / cm ³ is formed on the n type drift layer 2 by vapor phase epitaxy or the like. The p-type body layer 33 is left only in the left part of the figure, and the other p-type body layer is removed by mesa etching to form a termination region T. A p-type termination region 14 having an impurity concentration of 10 ¹⁶ to 10 ¹⁸ atm / cm ³ is formed by ion implantation in the termination region T. In the central region of the remaining p-type body layer 33, an n-type source region 7 of about 10 ¹⁸ atm / cm ^{3 is} formed by ion implantation of nitrogen, phosphorus or the like. Next, a trench 60 penetrating the p-type body layer 33 and having the bottom reaching the n-type drift layer 2 is formed by anisotropic etching. After the SiO ₂ gate insulating film 8 is formed on the inner wall of the trench 60, polysilicon containing high-concentration phosphorus is deposited to fill the trench 60. The polysilicon film attached to the inner wall of the trench 60 is left, and other polysilicon is removed to form a gate electrode 54 of the polysilicon film. A source electrode 53 is formed on the surface of the n-type region 7 and the p-type body layer 33 with aluminum, nickel, or the like, and a drain electrode 52 is formed in the drain region 11. Finally, a passivation film 26 having a thickness of 0.5 μm or more is formed in the termination region T to complete.

In the configuration of FIG. 7, the left end portion of the p-type termination region 14 covers the mesa corner portion 20, but it does not necessarily have to be covered. Since the thickness of the passivation film 26 is 0.5 μm or more, and is thicker than the distance L between the junction surface 33A of the p-type body layer 33 and the n-type drift layer 2 and the mesa bottom surface 18, the mesa corner portion 20 of the passivation film 26 is obtained. The electric field in the vicinity can be relaxed. Furthermore, the influence of alkali ions such as Na ions which adhere to the surface of the passivation film 26 and cause local electric field concentration on the SiC substrate surface can be mitigated. Further, the influence of moisture adhesion etc. stays in the vicinity of the surface of the passivation film 26 and does not reach the inside. Since the p-type body layer 33 is formed by an epitaxial growth method, there are very few crystal defects. As a result, the mobility of the channel region formed at the interface between the p-type body layer 33 and the gate insulating film 8 when turned on is as high as 83 cm ² / Vs.

<< Eighth embodiment >>
FIG. 8 is a sectional view of a breakdown voltage 8500 V class SiC IGBT according to an eighth embodiment of the present invention. The IGBT of this embodiment has a collector electrode 62 on one surface of the collector region 12 of the SiCp type substrate. Drift layer 2 is formed on the other surface of collector region 12. The thickness of the drift layer 2 is about 70 μm, and the impurity concentration is about 5 × 10 ¹⁴ atm / cm ³ . Since the p-type body layer 33 is formed by epitaxial growth like the MOSFET of the fifth embodiment, there are very few crystal defects. An emitter region 57 is formed in part of the p-type body layer 33, and an emitter electrode 63 is provided in the emitter region 57. With this configuration, the mobility of the channel region formed at the interface between the p-type body layer 33 and the gate insulating film 8 when turned on has a high value of 92 cm ² / Vs. Since holes are injected from the collector region 12 into the drift layer 2 at the time of ON, conductivity modulation occurs and the ON voltage can be lowered. When the current density is 100 A / cm ² , the on-voltage is 4.3V.

  The present invention is not limited to the above-described embodiments, but covers more application ranges or derived structures.

  In each of the above embodiments, only a semiconductor device using SiC has been described as an example, but the present invention can be effectively applied to a semiconductor device using other wide gap semiconductor materials such as diamond and gallium nitride.

  In the first to eighth embodiments, the drift layer 2 is described as an example of an n-type semiconductor device. When the drift layer 2 is a p-type semiconductor device, the configuration of the present invention can be applied by replacing the n-type region of another element with a p-type region and the p-type region with an n-type region. Furthermore, the present invention can be applied to all semiconductor devices having a p-type region (or n-type region) in the slope and drift layer sandwiching the mesa corner portion 20. Furthermore, the structure of the present invention can be applied even when the passivation film is formed of two or more types of materials.

Sectional drawing of pn diode of 1st Example of this invention Sectional drawing of the pn diode of 2nd Example of this invention. Sectional drawing of the pn diode of 3rd Example of this invention. Sectional drawing of the pn diode of 4th Example of this invention. Sectional drawing of the pn diode of 5th Example of this invention. Sectional drawing of the pn diode of 6th Example of this invention. Sectional drawing of MOSFET of 7th Example of this invention Sectional drawing of IGBT of 8th Example of this invention. Sectional view of a conventional pn diode Sectional view of another conventional pn diode Sectional view of another conventional pn diode

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Cathode region 2 Drift layer 3 P-type layer 4, 14 p-type termination region 5 Channel stopper 6, 16, 26 Passivation film 7 Source region 8 Gate insulating film 11 Drain region 20 Mesa corner part 26 Passivation film 33 P-type body layer 50 Cathode electrode 51 Anode electrode 52 Drain electrode 53 Source electrode 54 Gate electrode

Claims (8)

A first layer of a first conductivity type formed on a substrate of wide gap semiconductor material;
A second layer of a second conductivity type formed on the first layer by an epitaxial growth method;
A second conductivity type termination region formed on the first layer forming a mesa bottom surface of a mesa groove adjacent to the second layer from the mesa bottom surface side; and the termination region and the second layer And a surface protective film formed on the first layer,
The bonding surface between the second layer and the first layer is higher than the mesa bottom surface,
The surface between a mesa corner portion that is a portion where a mesa side surface of the mesa groove including a side surface of the second layer intersects with a mesa bottom surface, and an end portion on the mesa corner portion side of the termination region. The high withstand voltage semiconductor device according to claim 1, wherein a thickness of the protective film in a direction perpendicular to the mesa bottom surface is larger than a distance between the bonding surface and the mesa bottom surface. 2. The high withstand voltage semiconductor device according to claim 1, wherein an impurity concentration of the termination region of the second conductivity type is in a range of 10 ¹⁶ to 10 ¹⁸ atm / cm ³ .   2. The high withstand voltage semiconductor device according to claim 1, wherein an angle formed between a side surface of the second layer and a bottom surface of the mesa is in a range of 90 degrees to 150 degrees.   2. The high withstand voltage semiconductor device according to claim 1, wherein a thickness of the surface protective film in the mesa corner portion in a direction perpendicular to the mesa bottom surface is 1 μm or more.   2. The high withstand voltage semiconductor device according to claim 1, wherein the thickness of the surface protective film is 0.5 [mu] m or more.   2. The high withstand voltage semiconductor device according to claim 1, wherein an impurity concentration of the termination region of the second conductivity type is increased in a portion close to the mesa corner portion and decreased in a portion far from the mesa corner portion. .   2. The high withstand voltage semiconductor device according to claim 1, wherein the termination region of the second conductivity type has a plurality of divided regions, and the plurality of divided regions have substantially the same impurity concentration.   The high withstand voltage semiconductor device according to claim 1, wherein the second conductivity type termination region has a plurality of divided regions, and the plurality of divided regions have different impurity concentrations.

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