JPH1174524A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a breakdown of an insulation film (heat oxide film) caused by an electric field concentration. SOLUTION: An n<-> -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3 are laminated on an n<+> -type silicon carbide semiconductor substrate 1, a groove 7 forming a cell region and a groove 5 forming a tapered mesa structure of the p-type silicon carbide semiconductor layer 3 and the nθtype silicon carbide semiconductor layer 2 are formed on a semiconductor substrate 100 with its main surface comprising the surface of the p-type silicon carbide semiconductor layer 3. In the heat oxide film 9 and the layer between, the nθtype silicon semiconductor layer 2 and the p-type silicon carbide semiconductor layer 3 on the side of the groove 5, a high resistance layer 6 comprising an electric field suppression layer suppressing an electric field concentration at the heat oxide film 9, for instance, n<-> -type semiconductor having higher resistance than the n<-> -type silicon carbide semiconductor layer 2, and p-type silicon carbide semiconductor layer, are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and is particularly suitable for application to an insulated gate field effect transistor (hereinafter referred to as "power MOSFET"), especially to a vertical power MOSFET.

[0002]

2. Description of the Related Art There are a field plate structure and a guard ring structure as a structure applied to a chip peripheral region (peripheral region of a unit cell) of a semiconductor device. As an example of these structures, a storage channel type planar MOSFET to which a field plate structure is applied is shown in FIG.

As shown in FIG. 27, a planar type MO
In the outer peripheral region of the cell region where the SFET 500 is formed, a p-type layer region extending toward the outside of the cell region in the surface layer portion of the n ⁻ -type semiconductor layer 502 formed on the n ⁺ -type semiconductor substrate 501 507 are provided. This p
The mold layer region 507 serves to prevent breakdown by forming a PN junction with the n ⁻ -type semiconductor layer 502.

Further, an electrode 522 which is in contact with the p-type layer 507 through a contact hole formed in the insulating film 518 and extends toward the outside of the cell region is provided in the outer peripheral region. I have. The electrode 522 is a field plate, and the withstand voltage is improved by making the electrode 522 extending toward the outside of the cell region have the same potential and extending the depletion layer to the outer periphery of the cell region. .

In general, the withstand voltage of a semiconductor device is determined by the shape of the region where the pn junction is terminated. To obtain a semiconductor device with a high withstand voltage, there is a termination technique for uniformly reducing the electric field in this region. As one of the termination techniques, a mesa structure as disclosed in Japanese Patent Application Laid-Open No. 4-239778 has been proposed. FIG. 28 shows an n-channel vertical power MOSFET as a semiconductor device having a mesa structure, and the mesa structure will be described with reference to FIG.

The semiconductor substrate 120 of this vertical power MOSFET has an n ⁻ type silicon carbide semiconductor substrate 101 with n ⁻
-Type silicon carbide semiconductor layer 102 and p-type silicon carbide conductor layer 103
A groove 107 is formed in this substrate, an oxide film 109 and a gate electrode 110 are formed, and a source region 104 is formed around the groove 107 to form a cell region. . Then, a groove 105 surrounding the periphery of the cell region is formed. For example, the side surface of the groove 105 is tapered. A mesa structure in which the pn junction formed of the n ⁻ -type silicon carbide semiconductor layer 102 and the p-type silicon carbide conductor layer 103 around the cell region is terminated at the side surface of the groove 105 as described above.

It has been attempted to increase the breakdown voltage of a semiconductor device by employing such a mesa structure. As shown in FIG. 29, in the mesa structure, the side surface of the groove 105 may not be tapered, but may be substantially perpendicular to the substrate surface.

[0008]

However, it has been found that the above structure has the following problems. First, in the field plate structure shown in FIG. 27, when silicon carbide is used as the semiconductor material, the critical electric field strength at which avalanche breakdown occurs is one order of magnitude higher than when silicon is used, and the n-type drain layer Has an advantage that the resistance value of the drain layer (n ⁺ -type semiconductor layer 501) can be reduced and the on-resistance can be reduced. However, on the other hand, when the impurity concentration is set to such a high level, the extension of the depletion layer to the outside of the cell region is suppressed, and electric field concentration occurs at the interface of the insulating film 509. Therefore, once avalanche breakdown occurs at this interface, A problem arises in that hot carriers having high energy are injected into the insulating film 509 and dielectric breakdown occurs. This problem also occurs when a guard ring structure is employed.

On the other hand, in the mesa structure shown in FIG. 28, a portion of the side surface of trench 105 constituting the mesa structure, specifically, n ^- type silicon carbide semiconductor layer 102 and p-type silicon carbide semiconductor layer 103 are formed. There is a problem that electric field concentration occurs at a connection portion between the interface and the oxide film 109, and the dielectric breakdown of the oxide film 109 at the electric field concentration portion occurs. Further, in the case of the mesa structure, particularly when the side surface of the groove 105 is made substantially perpendicular to the substrate surface as shown in FIG. 29, the groove 105 is formed as shown by an equipotential line in the figure. There is also a problem that electric field concentration is likely to occur even at the corners of FIG.

The present invention has been made in view of the above problems, and has as its object to prevent dielectric breakdown of an insulating film caused by electric field concentration in a silicon carbide semiconductor device.

[0011]

In order to achieve the above object, the following technical means are employed. According to the first aspect of the present invention, the first conductive type low-resistance layer (1) and the first conductive type first semiconductor layer formed on the low-resistance layer and having a higher resistance than the low-resistance layer. (2) and a semiconductor substrate (100) having a second conductivity-type second semiconductor layer (3) formed on the first semiconductor layer, and having a surface of the second semiconductor layer as a main surface. ) To form a first groove (7) forming a cell region and a second groove (5) forming a mesa structure, and to form an insulating film (9) on a side surface of the second groove. An electric field relaxation layer (6, 30, 50) for reducing electric field concentration in an insulating film is formed between the second semiconductor layer and the first semiconductor layer.

As described above, even when the cell region has a groove shape, the insulating film on the side surface of the second groove and the second
Forming an electric field relaxation layer (6) between the first semiconductor layer and the first semiconductor layer, thereby forming a mesa-type portion of the second trench, that is, the first semiconductor layer and the second semiconductor layer. The electric field concentration at the connection between the interface of the insulating film and the insulating film can be reduced, and dielectric breakdown of the insulating film can be prevented.

Further, the same effect can be obtained by forming the electric field relaxation layer (50) from the side surface to the bottom surface of the second groove. further,
In this case, the electric field concentration at the corner of the groove can be reduced, and the dielectric breakdown of the insulating film at this portion can be prevented. According to a third aspect of the present invention, the electric field relaxation layer is formed of a first conductivity type material and has a higher resistance than the first semiconductor layer.

As described above, by forming the electric field relaxation layer with the first conductivity type material having a higher resistance than the first semiconductor layer,
The extension of the depletion layer is increased by this electric field relaxation layer.
The electric field concentration at the connection between the interface between the semiconductor layer and the second semiconductor layer and the insulating film can be reduced. Further, in the invention according to claim 4, an electrode layer (12) for controlling the potential of the electric field relaxation layer is provided on the surface of the insulating film formed on the surface of the electric field relaxation layer, and the electric field relaxation layer is formed by this electrode layer. Is set to a voltage lower than the threshold voltage.

As described above, by setting the voltage of the electric field relaxation layer lower than the threshold voltage, the electric field relaxation layer can be always depleted, so that the first semiconductor layer and the second semiconductor layer can be depleted.
Electric field concentration can be prevented from occurring at the connection between the interface of the semiconductor layer and the insulating film. According to a fifth aspect of the invention, the electric field relaxation layer is formed of a second conductivity type material.

By forming the electric field relaxation layer of the second conductivity type material as described above, the electric field in the first semiconductor layer escapes in the direction of the bottom surface of the second groove.
Electric field concentration can be prevented from occurring at the connection between the interface between the semiconductor layer and the second semiconductor layer and the insulating film. Further, when the electric field relaxation layer is formed from the side surface to the bottom surface of the second groove, a depletion layer generated at a pn junction formed by the electric field relaxation layer and the first semiconductor layer causes the depletion layer in the first semiconductor layer. Causing avalanche breakdown,
The dielectric breakdown of the insulating film can be more effectively prevented.

According to a sixth aspect of the present invention, there is provided a third groove (70) formed between the first groove and the second groove and penetrating from the main surface to the second semiconductor layer. The second semiconductor layer is electrically divided by the third groove. As described above, by electrically dividing the second semiconductor layer between the first groove and the second groove by the third groove, the avalanche breakdown current flows through the cell region, and the cell region is damaged. Can be prevented. Thus, the life of the semiconductor device can be improved.

According to a seventh aspect of the present invention, there is provided a silicon carbide in which the low resistance layer, the first semiconductor layer, the second semiconductor layer, and the electric field relaxation layer are made of silicon carbide. It is preferable to apply to a semiconductor device. According to an eighth aspect of the present invention, in the first to sixth aspects, the low resistance layer, the first semiconductor layer, and the second semiconductor layer are made of silicon carbide.
The electric field relaxation layer may be made of an aluminum alloy. In this case, since the aluminum alloy can be formed by a method other than the epitaxial growth method, the step of forming the electric field relaxation layer can be simplified.

According to the ninth aspect of the present invention, the second semiconductor region (80) of the second conductivity type formed in the first semiconductor layer (2) at the bottom of the second groove (5) is formed. And
A first electrode (1) in electrical contact with the first semiconductor region
2) and the second semiconductor region are electrically contacted with each other. The first semiconductor layer on the bottom surface of the second groove is thinner than the portion where the second groove is not formed. For this reason, by forming the second semiconductor region of the second conductivity type in the first semiconductor layer on the bottom surface of the second groove, the pn junction formed by the first semiconductor layer and the second semiconductor region is formed. , The first semiconductor layer and the second
Withstand voltage lower than the pn junction formed by the semiconductor layer (3).

Therefore, if the first electrode which is in electrical contact with the first semiconductor region and the second semiconductor region are in electrical contact, the first semiconductor layer (2) and the second semiconductor layer An avalanche breakdown is caused by a pn junction formed by the first semiconductor layer and the second semiconductor region before electric field concentration occurs at a connection portion between the interface of the layers and the insulating film (9) and the insulating film is broken down. be able to. Thereby, dielectric breakdown of the insulating film can be prevented.

According to a tenth aspect of the present invention, there is provided a groove (5) forming a mesa structure, and an insulating film (9) formed on the groove, and the first film on the side surface of the groove. An electric field relaxation layer (6, 30, 50) for reducing electric field concentration in the insulating film is formed between the semiconductor layer (2) and the second semiconductor layer (3) and the insulating film. I do.

As described above, if the electric field relaxation layer is formed between the first semiconductor layer and the second semiconductor layer on the side surface of the groove and the insulating film, the portion of the groove forming the mesa structure, that is, the first Electric field concentration at the connection between the interface between the first semiconductor layer and the second semiconductor layer and the insulating film can be reduced. As described above, the dielectric breakdown of the insulating film can be prevented by forming the electric field relaxation layer not only in the trench gate type but also in another type of silicon carbide semiconductor device having a mesa structure.

According to the eleventh aspect of the present invention, after forming the mesa structure forming groove (5), the electric field relaxation layer (6, 30, 50) is formed on at least the side surface of the mesa structure forming groove.
And then forming a cell region forming groove (7). As described above, since the formation of the cell region forming groove is performed after the formation of the electric field relaxing layer, the electric field relaxing layer is not formed in the cell region forming groove. For this reason, it is possible to freely select, for example, to form another semiconductor layer in the cell region forming groove, and to change parameters in the semiconductor device.

According to a twelfth aspect of the present invention, the mesa structure forming groove (5) and the cell region forming groove (7) are formed simultaneously. As described above, by simultaneously forming the mesa structure forming groove and the cell region forming groove, the manufacturing process can be simplified. According to the thirteenth aspect of the present invention, the second conductive type semiconductor region (20) is formed in the surface layer of the first semiconductor layer (2) at the corner of the groove (5).
1) is formed.

As described above, by forming the semiconductor region of the second conductivity type at the corner of the groove, the PN junction between the first semiconductor layer (2) and the second semiconductor layer (3) is formed. Even when a high voltage is applied, the depletion layer can be expanded around the semiconductor region. For this reason, the electric field concentration at the corners of the groove can be reduced by the semiconductor region, and dielectric breakdown of the insulating film (9) can be prevented.

According to the present invention, the second groove (5) is formed so as to surround the periphery of the first groove (7) in which the unit cell region is formed. A second semiconductor region (201) of the second conductivity type is formed in a surface layer portion of the first semiconductor layer (2) at a corner of the groove. As described above, by forming the second conductivity type second semiconductor region at the corner of the trench in the trench gate type silicon carbide semiconductor device, the first semiconductor region (4)
Even if a high voltage is applied between the second electrode layer and the second electrode layer, the dielectric breakdown of the insulating film can be prevented in the same manner as in the thirteenth aspect.

In the invention according to claim 15, the second
An electric field relaxation layer (6) made of a semiconductor of the first conductivity type is formed on the side surface of the groove. Accordingly, the same effect as that of the fourteenth aspect can be obtained, and the same effect as that of the first aspect can be obtained. According to a sixteenth aspect of the present invention, the second semiconductor region is formed including a portion where the side surface and the bottom surface of the second groove are in contact with each other.

Among the corners of the groove, the place where the electric field concentration occurs most is where the side surface and the bottom surface of the second groove are in contact.
If the second semiconductor region is formed including this portion, the electric field concentration can be reduced most effectively.
Forming a second semiconductor region of a second conductivity type in a surface layer of the first semiconductor layer at a corner of the trench for forming a mesa structure; Accordingly, a silicon carbide semiconductor device having the effect of claim 13 can be obtained.

Further, by forming the mesa-type structure forming groove and the cell region forming groove in the same step, the manufacturing process can be simplified. In the invention according to claim 19, the insulating film (309) disposed under the field plate (322) and the first
A semiconductor thin film layer (308) of the first conductivity type having a higher resistance than the first semiconductor layer is formed between the first semiconductor layer and the semiconductor layer (302).

As described above, by forming the semiconductor thin film layer having a higher resistance than the first semiconductor layer below the field plate, a reverse bias voltage is applied between the first and second electrodes (312, 313). When the voltage is applied, the element isolation layer (3
07), the extension of the depletion layer to the outside of the cell formation region can be increased, so that the electric field intensity at the interface between the insulating film and silicon carbide under the field plate can be reduced. Thereby, dielectric breakdown of the insulating film can be prevented.

Incidentally, the semiconductor thin film layer can be formed by growing an epitaxial film on the first semiconductor layer. in this way,
By forming the semiconductor thin film layer using an epitaxial film, the semiconductor thin film layer can have an impurity concentration lower than that of the first semiconductor layer with good controllability. For example, in the case where the semiconductor thin film layer is formed in the first semiconductor layer by ion implantation, it is difficult to compensate the impurity concentration of the semiconductor thin film layer to be lower than that of the first semiconductor layer.

In the invention according to claim 22, the second conductive type second semiconductor layer (40) having a predetermined width and arranged in plural at predetermined intervals from the element isolation layer (307).
9), and on the first semiconductor layer (302) between the second semiconductor layer and the element isolation layer,
A semiconductor thin film layer (408) of the first conductivity type having a higher resistance than the first semiconductor layer is formed.

As described above, the semiconductor thin film layer (40) is interposed between the guard ring structures formed by the second semiconductor layer (409).
By forming 8), the extension of the depletion layer between the second semiconductor layers can be increased, and the insulating film (309) formed therebetween can be prevented from dielectric breakdown. In this case, a semiconductor of the first conductivity type having a higher resistance than the first semiconductor layer is provided between the insulating film below the field plate (322) and the first semiconductor layer. If the thin film layer (408) is formed, the same effect as the nineteenth aspect can be further obtained.

In the invention according to claim 24, the first
Forming a first conductive type thin film layer having a lower concentration than the first semiconductor layer on the first semiconductor layer (302);
Is characterized in that a surface channel layer (304) connected to the base region (303) is formed simultaneously with a thin film semiconductor layer (308) arranged around the cell formation planned region.

As described above, by simultaneously forming the surface channel layer and the thin film semiconductor layer, the manufacturing process can be simplified. In the invention according to claim 25, the predetermined region of the first base region and the element isolation layer (30
The method is characterized in that a second conductivity type second base region (303a) having a junction depth deeper than the first base region is formed in the predetermined region of (7).

As described above, by forming the second base region having a junction depth deeper than that of the first base region, the curvature in this region can be reduced and the electric field intensity can be increased. For this reason, the first and second electrodes (312, 312
If a reverse bias voltage is applied during 13), the second
Avalanche breakdown can occur in the base region.

Since the formation position of the second base region can be arbitrarily determined by the mask position, for example, when forming an FET as a cell, the FE
It can be formed at a position where the parasitic transistor of T becomes difficult to operate. Therefore, the second position
By forming the base region described above, it is possible to increase the resistance to back electromotive energy when driving the L load.

In the twenty-sixth aspect of the present invention, the first
A first semiconductor layer (30) on the first semiconductor layer (302).
By forming a first conductivity type thin film layer having a lower concentration than in 2), the surface channel layer (304) connected to the first base region and the thin film semiconductor layer (408) around the cell formation planned region are formed. ) Is formed. As described above, even when the guard ring structure is adopted, the manufacturing process can be simplified by simultaneously forming the surface channel layer and the thin film semiconductor layer.

In the invention according to claim 27, the first aspect
A plurality of first base regions (303) of a second conductivity type having a predetermined depth in a region where a cell is to be formed in a surface layer portion of the semiconductor layer (301); And a plurality of ring layers of the second conductivity type (40) arranged at predetermined intervals around the device isolation layer.
9) is formed.

As described above, by forming the first base region, the element isolation layer, and the ring layer in the same process, the manufacturing process can be simplified. In the invention according to claim 28, a first-conductivity-type semiconductor electric-field relaxation region that is in contact with the surface of the first-conductivity-type semiconductor layer and has higher resistance than the first-conductivity-type semiconductor layer is formed in the peripheral region. It is characterized by being.

In such a configuration, in the peripheral region around the cell region of the semiconductor device, the semiconductor electric field relaxation region of the first conductivity type having a higher resistance than the semiconductor layer of the first conductivity type, that is, a lower impurity concentration, is formed. Since the first conductivity type semiconductor layer is formed in contact with the one conductivity type semiconductor layer, the depletion layer formed between the second conductivity type semiconductor region and the first conductivity type semiconductor layer extends in the peripheral region. Larger than that of the semiconductor layer. As a result, the withstand voltage in the peripheral region located on the outer periphery of the cell region of the semiconductor device can be improved.

In particular, when silicon carbide (SiC) is used as the semiconductor, the concentration of the first conductivity type semiconductor layer can be increased due to the characteristics of the material. Although there is a concern that the withstand voltage in the peripheral region in the outer peripheral portion may be ensured, it may be one means for ensuring the withstand voltage in the peripheral region by the above-described semiconductor electric field relaxation region of the first conductivity type.

According to a twenty-ninth aspect, in the peripheral region, the second conductive type semiconductor layer is formed on the first conductive type semiconductor layer, and the first conductive type semiconductor layer extends from the surface of the second conductive type semiconductor layer. A groove reaching the semiconductor layer of the mold is formed, and the semiconductor electric field relaxation region is formed on a side surface of the groove. As described above, by forming the electric field relaxation region on the groove side surface, the electric field concentration between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer appearing on the groove side surface is reduced by the semiconductor electric field relaxation region. it can.

On the other hand, the invention according to claim 30 is characterized in that the first conductivity type semiconductor electric field relaxation region is formed on the first conductivity type semiconductor layer in the peripheral region, The electric field which tends to concentrate in the first conductivity type semiconductor layer can be reduced by the semiconductor electric field relaxation region formed on the semiconductor layer of the first conductivity type.

[0045]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. (First Embodiment) FIG. 1 shows n according to an embodiment of the present invention.
1 shows a cross-sectional view of a channel type vertical power MOSFET. Hereinafter, the structure of the vertical power MOSFET will be described with reference to FIG.

On an n ⁺ -type silicon carbide semiconductor substrate 1 as a low-resistance semiconductor layer made of hexagonal silicon carbide, an n ⁻ -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3 as a high-resistance semiconductor layer are sequentially formed. These n ⁺ -type silicon carbide semiconductor substrate 1, n ⁻ -type silicon carbide semiconductor layer 2 and first p-type silicon carbide semiconductor layer 2 are stacked.
Semiconductor substrate 100 made of single-crystal silicon carbide is formed from type silicon carbide semiconductor layer 3. The upper surface of the semiconductor substrate 100 is substantially a (0001-) carbon surface.

An n ⁺ -type source region 4 as a semiconductor region is formed in a predetermined region in a surface layer portion in p-type silicon carbide semiconductor layer 3. In addition, a groove 7 is formed in a predetermined region of the n ⁺ type source region 4. This trench 7 penetrates n ⁺ -type source region 4 and p-type silicon carbide semiconductor layer 3,
^- it has reached the -type silicon carbide semiconductor layer 2. A groove 5 is formed in a predetermined region of p-type silicon carbide semiconductor layer 3,
The groove 5 is formed to be the same as or deeper than the groove 7.
The groove 5 is formed so as to surround the groove 7 serving as a cell region in a circular shape with the center as a center. The groove 5 forms a mesa structure.

An n ⁻ -type high-resistance layer 6 as an electric field relaxation layer made of a silicon carbide semiconductor is formed on the groove side surface of groove 5. This high resistance layer 6 has a higher resistance than the n ⁻ -type silicon carbide semiconductor layer 2 and is formed to have a concentration lower by about one digit in terms of impurity concentration. Further, a thermal oxide film 9 as a gate insulating film is formed on the substrate including the grooves 7 and 5. A base electrode 10 made of polysilicon is formed in a channel forming portion in the groove 5, and an insulating film 11 is formed on a semiconductor substrate 100 including the gate electrode 10.

[0049] Further, on the thermal oxide film 9 is the source electrode 12 is formed, the source electrode 12 through a contact hole formed in the thermal oxide film 9 and the insulating film 10 is n ⁺ -type source region 4 and the p-type carbide It is electrically connected to the silicon semiconductor layer 3. The surface of the n ⁻ -type silicon carbide semiconductor layer 2 forming the bottom surface of the trench 5 has a high concentration of n ⁺ so as to surround the cell region.
Type silicon carbide semiconductor layer 15 is formed. This n ⁺ -type silicon carbide semiconductor layer 15 is electrically connected to electric wiring 16 through contact holes formed in thermal oxide film 9 and insulating film 10. The periphery of the cell is maintained at the same potential by the wiring 16, so that the depletion layer in the pn junction formed by the p-type silicon carbide semiconductor layer 3 and the n ⁻ -type silicon carbide semiconductor layer 2 extends uniformly.

Thus, the vertical power MOSFET is
The structure is such that an n ⁻ -type high-resistance layer 6 is provided on the outermost groove side surface. The n ⁻ -type high resistance layer 6 is formed in the thermal oxide film 9 near the interface between the n ⁻ -type silicon carbide semiconductor layer 2 and the p-type silicon carbide semiconductor layer 3, that is, in the thermal oxide film 9 in the portion forming the mesa structure. It plays a role in preventing dielectric breakdown.

Further, the vertical power M thus configured
When a predetermined drive voltage is applied to gate electrode 10 of the OSFET, p-type silicon carbide semiconductor layer 3 between n ⁻ -type silicon carbide semiconductor layer 2 and n ⁺ -type source region 4 serves as a channel region to flow current. In addition, the vertical power MOSFE
The gate, source, and drain potentials at T are represented by VG, VS, and VD, respectively.

FIG. 2 shows the vertical power MOSFET shown in FIG.
An electric field distribution curve in n ⁻ -type silicon carbide semiconductor layer 2 when T is used is shown by a dotted line. As shown in this figure, the electric field in n ⁻ -type silicon carbide semiconductor layer 2 shows a distribution that spreads two-dimensionally due to the mesa structure. The electric field is concentrated near the high resistance layer 6. Then, the electric field distribution curve ends through the high resistance layer 6.

At this time, since the electric field is concentrated in the high resistance layer 6, the electric field concentration is also observed in the thermal oxide film 9. However, even if the breakdown occurs in the high resistance layer 6, the breakdown is high. Resistance layer 6 and p-type silicon carbide semiconductor layer 3
Since the mold is not a breakdown at the interface between the silicon carbide semiconductor layer 2 and the p-type silicon carbide semiconductor layer 3 ^- and n ^- type becomes avalanche breakdown in a region near the intersection of the silicon carbide semiconductor layer 2, the thermal oxide film 9 and the n The breakdown of the thermal oxide film 9 is suppressed by the breakdown. As described above, since the dielectric breakdown of the thermal oxide film 9 can be prevented, the withstand voltage of the vertical power MOSFET can be improved.

Next, a manufacturing process of the trench gate type power MOSFET will be described with reference to FIGS. [Step shown in FIG. 3A] First, the main surface is (0001)
-) A low-resistance n ⁺ -type silicon carbide semiconductor substrate 1 having a carbon surface is prepared, an n ⁻ -type silicon carbide semiconductor layer 2 is epitaxially grown on the surface thereof, and a p ^- type silicon carbide semiconductor layer 2 is further formed on the n ⁻ -type silicon carbide semiconductor layer 2. Silicon carbide semiconductor layer 3 is epitaxially grown. Thereby, n ⁺ type silicon carbide semiconductor substrate 1 and n ⁻
Double-epi semiconductor substrate 100 including p-type silicon carbide semiconductor layer 2 and p-type silicon carbide semiconductor layer 3 is formed.

Then, ion implantation of, for example, nitrogen or the like is performed on the p-type silicon carbide semiconductor layer 3 using a mask material.
An n ⁺ -type source region 4 is formed in a predetermined region of a surface layer portion of p-type silicon carbide semiconductor layer 3. [Step shown in FIG. 3B] Dry etching is performed, and p
A groove 5 penetrating through n ^- type silicon carbide semiconductor layer 2 to reach n ⁻ -type silicon carbide semiconductor layer 2 is formed. At this time, the groove 5 is formed so as to form a substantially circular shape with the n ⁺ type source region 4 serving as a cell region as a center.

[Step shown in FIG. 3 (c)] A high-resistance layer 6 made of an n ⁻ -type silicon carbide semiconductor is formed on the side surface of the trench 5 by epitaxial growth and thermally oxidizing the epitaxial growth layer. However, the high-resistance layer 6, n ^- lower concentration than type silicon carbide semiconductor layer 2, i.e. n ^- than -type silicon carbide semiconductor layer 2 is formed of a high resistance. In this epitaxial growth and thermal oxidation, n ^- since the -type silicon carbide semiconductor layer 2 and the p-type silicon carbide semiconductor layer 3 having a hexagonal crystal structure, the anisotropy of the anisotropic or oxidation of epitaxial growth n ^- Type silicon carbide semiconductor layer 6 is formed uniformly and with good control (Japanese Patent Application Laid-Open Nos. Hei 7-326755, Hei 9-74193, Japanese Patent Application Hei 8-962).
5).

[0057] the central portion of the n ⁺ -type source region 4 step shown in FIGS. 4 (a)], to form a groove 7 extending through the n ⁺ -type source region 4 and the p-type silicon carbide semiconductor 3. At this time, the depth of the groove 7 is made equal to or shallower than the groove 5. Also,
Since the step of forming groove 7 is performed after the step of forming n ⁻ -type silicon carbide semiconductor layer 6, no silicon carbide semiconductor layer is formed in groove 7. Therefore, when it is desired to form a semiconductor layer in trench 7, a semiconductor layer of a conductivity type different from n ⁻ -type silicon carbide semiconductor layer 6, a semiconductor layer of the same conductivity type but different in concentration, or a thickness in trench 7 is set. Different semiconductor layers can be formed separately. As a result, the parameters of the vertical power MOSFET can be varied.

[Step shown in FIG. 4B] Nitrogen is ion-implanted into the n ⁻ -type silicon carbide semiconductor layer 2 at the portion where the groove 5 is formed using a mask material, and a cell is formed at the bottom of the groove 5. An n ⁺ -type silicon carbide semiconductor layer 8 surrounding the region is formed. [Step shown in FIG. 4C] A thermal oxide film 9 is formed on the surface of the semiconductor substrate 100 including the grooves 5 and 7 by thermal oxidation.
At this time, thermal oxidation is performed in a wet atmosphere. Then, the temperature of the double epi substrate is raised to 1000 ° C., and a thermal oxide film 9 having a thickness of, for example, 100 nm is formed on the side surface of the groove and a thickness of, for example, 500 nm is formed on the bottom surface of the groove.

[Step shown in FIG. 5A] Semiconductor substrate 10
And a gate electrode layer 1 on the surface of the thermal oxide film 9 in the groove 7 by photo-etching.
0 is formed. [Step shown in FIG. 5B] The insulating film 1 is formed on the upper surface of the gate electrode layer 10 by a vapor deposition method (for example, a chemical vapor deposition method). Then, contact holes are selectively formed in predetermined regions by photo-etching.

[Step shown in FIG. 5C] The source region 4 including the surface of the insulating film 11 and the surface of the p-type silicon carbide semiconductor layer 3 are
For example, a source electrode 12 made of Ni is formed. Then, on the back side of the n ⁺ type silicon carbide semiconductor substrate 1, for example, Ni
When the drain electrode 13 is formed, a vertical power MOSFET having the configuration shown in FIG. 1 is completed.

(Second Embodiment) Next, a second embodiment to which the present invention is applied will be described with reference to FIG. In the above-described first embodiment, n ⁻ -type silicon carbide semiconductor layer 6 is formed on side surface 5 of trench 5 as an electric field relaxation layer. However, in the present embodiment, n ⁻ -type silicon carbide semiconductor layer 6 is replaced with p-type silicon carbide semiconductor layer 6. The silicon semiconductor layer 30 is formed on the side surface of the groove 6 as an electric field relaxation layer.

FIG. 7 shows the vertical power MOSF shown in FIG.
4 shows an electric field distribution when ET is used. As shown in this figure, the electric field changes due to the depletion layer generated by the pn junction in p-type silicon carbide semiconductor layer 30 and n ⁻ -type silicon carbide semiconductor layer 2, and the electric field distribution curve extends toward the bottom surface of trench 5. It is shown in a state. As described above, by forming p-type silicon carbide semiconductor layer 30 on the side surface of groove 5 forming the mesa structure, electric field concentration on the side surface of groove 5 can be prevented. Thus, dielectric breakdown of the thermal oxide film 9 caused by the electric field concentration can be prevented.

Note that n ⁻ in the first embodiment described above.
In the step of forming silicon carbide semiconductor layer 6, p-type silicon carbide semiconductor layer 30 can be formed by ion implantation of aluminum, for example, instead of epitaxially growing the silicon carbide semiconductor layer. The vertical power MOSFET in the form can be manufactured. Further, by depositing an aluminum alloy, it is possible to form a metal layer capable of obtaining the same effect as p-type silicon carbide semiconductor layer 30. In these cases,
The electric field relaxation layer can be formed on the side surface of the groove 6 without using the epitaxial growth method.

(Third Embodiment) Next, a third embodiment according to the present invention will be described with reference to FIG. In the above-described first embodiment, only the n ⁻ -type silicon carbide semiconductor layer 6 is formed on the side surface 5 of the trench 5 as an electric field relaxation layer. However, in the present embodiment, when a vertical power MOSFET is used, n ⁻ type silicon carbide semiconductor layer 6 is formed.
^- in order to always depleted type silicon carbide semiconductor layer 6, the groove 5
The electrode layer 40 is provided on the side opposite to the n ⁻ -type silicon carbide semiconductor layer 6 with the thermal oxide film 9 interposed therebetween.

This electrode layer 40 is electrically connected to n ⁺ -type source region 12 through a contact hole formed in insulating film 11. When a vertical power MOSFET is used, the electrons in n ⁻ -type silicon carbide semiconductor layer 6 are eliminated by clamping electrode layer 40 to the same potential as source electrode 12, whereby n ⁻ -type silicon carbide semiconductor layer 6 is always depleted. And, this way, n ^-
By depleting type silicon carbide semiconductor layer 6, electric field concentration on the side surface of trench 5 can be prevented, so that dielectric breakdown of thermal oxide film 9 on the side surface of groove 5 can be prevented.

As a result, the dielectric breakdown of the thermal oxide film 9 can be further prevented as compared with the first embodiment.
Note that, in the present embodiment, the electrode layer 40 and the source electrode 12 are electrically connected, but this is for setting the voltage of the n ⁻ -type silicon carbide semiconductor layer 6 to a voltage lower than the threshold voltage. Yes, if this condition is satisfied, the potential of the electrode layer 40 may be set by means other than the source electrode 12.

The electrode layer 40 is formed simultaneously in the step of forming the gate electrode layer 10 shown in FIG. 5A, and when the contact hole is formed in the insulating film 1 shown in FIG. By simultaneously forming a contact hole for connecting the electrode layer 40 and the source electrode 12 to each other, the vertical power MOSFET according to the present embodiment can be manufactured.

(Fourth Embodiment) Next, a third embodiment according to the present invention will be described with reference to FIG. In the above-described second embodiment, the p-type silicon carbide semiconductor layer 30 is formed on the side surface of the groove 5, but in this embodiment, substantially the entire side surface and bottom surface of the groove 5 contain a p-type dopant as an electric field relaxation layer. The electrode layer 50 is formed.

FIG. 10 shows the vertical power MOS shown in FIG.
4 shows an electric field distribution when an FET is used. Shown in this figure
As described above, the electric field is generated on the side surface of the groove 5 forming the mesa structure.
However, it can be seen that it is terminated at the bottom of the groove 5. One
In other words, by forming the electrode layer 50,
The electric field concentration is moved to the bottom side of the groove 5 and the
And n^-Occurs at the pn junction in the p-type silicon carbide semiconductor layer 2
The depletion layer ^-In the silicon carbide semiconductor layer 2
Lanche breakdown is caused.

As described above, by forming the electrode layer 50 entirely on the bottom surface of the groove 5 in addition to the side surface of the groove 5 constituting the mesa structure, electric field concentration occurs on the side surface and the bottom surface of the groove 5. Therefore, dielectric breakdown of the thermal oxide film 9 caused by electric field concentration can be prevented, and a vertical power MOSFET having a high withstand voltage and a large avalanche withstand voltage can be obtained.

In this embodiment, the electrode layer 50
Was formed with an electrode layer containing a p-type dopant,
0 may be formed by a silicon carbide layer. In this case, since the portion of electrode layer 50 made of a silicon carbide layer is always in a depleted state, electrode layer 50 containing a p-type dopant
The same effect as in the case of can be obtained. Further, even when a metal such as Al-Ti is applied as the electrode layer 50, the same effect as described above can be obtained. When a metal such as Al-Ti is applied, the electric field relaxation layer can be formed by ion implantation of aluminum. Therefore, unlike the silicon carbide layer, the electric field relaxation layer can be formed by ion implantation without using epitaxial growth, so that the process for forming the electric field relaxation layer can be simplified.

(Fifth Embodiment) Next, a fifth embodiment according to the present invention will be described with reference to FIG. In the above-described first embodiment, the side surface of the trench 5 forming the mesa structure and the carrier forming region are connected by the p-type silicon carbide semiconductor layer 3. However, in the present embodiment, the side surface of the trench 5 and the cell region are connected. The side surfaces of the groove 5 and the carrier forming region are electrically separated (insulated) by forming a groove 70 between them.

That is, p-type silicon carbide semiconductor layer 3 and n ⁻
Junction between the groove 70 and the groove 5 (hereinafter, referred to as a side pn junction) and a pn junction between the groove 70 and the groove 7 among the pn junctions formed by the silicon carbide semiconductor layer 2.
A junction (hereinafter, referred to as a cell-side pn junction) is electrically separated. The groove 70 is formed to be the same as or shallower than the groove 7 so that the electric field concentration in the thermal oxide film 9 formed in the groove 70 is reduced.

FIG. 12 shows the vertical power MO shown in FIG.
4 shows an electric field distribution when an SFET is used. If the side surface of the trench 5 is electrically separated from the cell region, the channel region and the region for withstanding the device can be separated.
An electric field distribution as shown in FIG. When a high voltage is applied to the drain electrode 13, the avalanche breakdown current flows to the side-side pn junction.
Element destruction at bonding is less likely to occur. Thus, the cell region can be prevented from being damaged by the avalanche breakdown current flowing through the cell region, so that the lifetime of the vertical power MOSFET can be improved.

(Sixth Embodiment) Next, a sixth embodiment to which the present invention is applied will be described with reference to FIG. In the above-described first embodiment, n ⁻ -type silicon carbide semiconductor layer 6 is formed on the side surface of groove 5 forming the mesa structure, thereby preventing electric field concentration on the side surface of groove 5 and thermally oxide film 9.
Is prevented, but in the present embodiment,
A p-type silicon carbide semiconductor layer 80 is formed on the surface layer of n ⁻ -type silicon carbide semiconductor layer 2 located at the bottom of groove 5, and is formed by p-type silicon carbide semiconductor layer 80 before thermal oxide film 9 causes dielectric breakdown. Breakdown prevents dielectric breakdown of the thermal oxide film 9.

More specifically, the vertical power MOSFET according to the present embodiment includes the p-type silicon carbide semiconductor layer 80 described above. Then, the n ⁺ type source region 12
Is extended to the inside of the groove 5 to electrically connect the n ⁺ -type source region 12 and the p-type silicon carbide semiconductor layer 80 via the contact holes formed in the insulating film 11 and the thermal oxide film 9. . That is, p-type silicon carbide semiconductor layer 80 and n ⁺ -type source region 12 have the same potential.

In the thickness of the n ⁻ -type silicon carbide semiconductor layer 2, the thickness L 2 of the portion where the groove 5 is formed and the thickness L 2 of the portion where the groove 5 is not formed is larger. thick. This indicates that the breakdown voltage of the n ⁻ -type silicon carbide semiconductor layer 2 is greater in the portion having the thickness L2 than in the portion having the thickness L1. Therefore, p-type silicon carbide semiconductor layer 80 and n
^- pn junction by type silicon carbide semiconductor layer 2 (hereinafter, referred to as auxiliary bonding) and, p-type silicon carbide semiconductor layer 3 and the n ^- pn junction by type silicon carbide semiconductor layer 2 (hereinafter, referred to as the main junction) Comparing, auxiliary Avalanche breakdown occurs at the junction at a lower voltage than the main junction.

As described above, since breakdown occurs in the outer region separated from the cell region, dielectric breakdown of the thermal oxide film 9 on the side surface of the groove 5 constituting the mesa structure can be prevented. Also, the portion where the avalanche breakdown occurs is different from the dielectric breakdown of the thermal oxide film 9 and is a breakdown in the semiconductor. Therefore, even after the breakdown, the vertical power MOSFET does not fail. For this reason, a vertical power MOS that is unlikely to cause permanent failure
It can be an FET.

(Seventh Embodiment) Next, a seventh embodiment to which the present invention is applied will be described with reference to FIG. In the present embodiment, a structure that can prevent dielectric breakdown of the thermal oxide film 309 at the corner of the groove 5 formed on the periphery of the cell region will be described. As shown in FIG. 14, the p-type layer region 20 is located on the side (corner side of the trench) closest to the cell region on the bottom surface of the trench 5 formed in the trench gate type vertical power MOSFET.
1 is formed. Since the p-type layer region 201 functions as a guard ring, the depletion layer can be extended to the periphery of the p-type layer region 201 as shown by the equipotential lines (dotted line) in FIG.

Specifically, when the electric field intensity distribution at the AA cross section in FIG. 14 and the electric field intensity at the BB cross section in FIG. 28 were examined, the results are shown in FIGS. 15 (a) and (b), respectively. The results shown were obtained. As is clear from these figures, the groove 5
It can be seen that the electric field intensity distribution at the corners of FIG. 7 is lower in the case where the p-type layer region 201 is formed than in the conventional case where the p-type layer region 201 is not formed, and the electric field concentration is reduced.

Therefore, the concentration of the electric field at the corner of the groove 5 is reduced, and the thermal oxide film 9 at this portion can be prevented from being dielectrically broken down. Thereby, the withstand voltage of the semiconductor device can be improved. In the present embodiment, the p-type layer region 201 is formed only on the bottom surface of the corner of the groove 5. However, if the p-type layer region 201 is formed so as to entirely cover the corner, the electric field concentration can be further reduced.

In this embodiment, the case where the side surface of the groove 5 where the electric field concentration is particularly likely to occur at the corner of the groove 5 is substantially perpendicular to the substrate surface is shown, but the side surface of the groove 5 has a tapered shape. It can be applied to such cases. Next, a method of manufacturing the vertical power MOSFET shown in FIG. 14 will be described with reference to FIG.
Description will be made based on manufacturing process diagrams shown in FIGS. In addition,
Only the parts different from the method of manufacturing the vertical power MOSFET shown in the first embodiment will be described, and the common parts will be omitted. In this figure, the case where the side surface of the groove 5 where the electric field concentration is likely to occur at the corner of the groove 5 is substantially perpendicular to the substrate surface will be described.

First, after the process shown in FIG.
As shown in FIG. 16A, dry etching is performed,
N ⁺ -type source region 2 penetrating p-type silicon carbide semiconductor layer 3
Is formed. Next, as shown in FIG. 16B, a region other than the corners of the groove 5 is covered with a mask material 200 through a photo process, and then a p-type impurity is ion-implanted to form a p-type layer region. .

Thereafter, as shown in FIG. 16C, epitaxial growth is performed, and the epitaxially grown layer is oxidized to form a high resistance layer 6 made of an n ⁻ -type silicon carbide semiconductor on the side surface of the groove 5. Thereafter, through the steps shown in FIGS. 4 and 5, the vertical power MOSFET according to the present embodiment is formed.
T is completed. (Eighth Embodiment) Next, an eighth embodiment to which the present invention is applied will be described. In the present embodiment, the withstand voltage can be improved when the field plate structure is adopted in the outer peripheral region of the cell region. FIG. 17 shows a silicon carbide semiconductor device according to the present embodiment.

As shown in FIG. 17, in this embodiment, a planar MOSFET is formed in a cell region. The overall configuration of the planar type MOSFET is different from the trench gate type MOSFET shown in FIG. 1 in that a thin film layer 304 for forming a channel is formed without forming a groove. Since other points are almost the same, only the differences will be specifically described, and the same parts will be omitted.

The planar type MOSFET has an n ⁺ -type silicon carbide semiconductor layer 301 and an n ⁻ -type silicon carbide semiconductor layer 302 as substrates, and a plurality of p-type silicon carbide layers formed on the surface of n ⁻ -type silicon carbide semiconductor layer 302. A silicon semiconductor layer (hereinafter, referred to as a p-type base region) 303 and a surface channel layer 304 parallel to the substrate surface are provided. Then, the gate electrode 30
When a positive voltage is applied to 6, a channel is formed in the surface channel layer 304, so that a transistor operation is performed. Reference numeral 312 denotes a source electrode;
Is a drain electrode. Reference numeral 320 denotes a gate electrode which is electrically connected to the gate electrode layer 306.

The outer peripheral region of the cell region is provided with a p-type region 307 for preventing breakdown and an electrode 322 forming a field plate. The p-type region 307 is n
^It is formed in the surface portion of the ⁻ type epitaxial layer 302 and is in contact with the electrode 322 via a contact hole formed in the insulating film 309. The electrode 322 extends toward the outside of the cell region. Since the electrode 322 has the same potential, the depletion layer extends to the outer periphery of the cell region, and the breakdown voltage can be improved.

Further, the electrode 3 forming the field plate
At the bottom of 22^-Type epitaxial layer 302
On top, n^-Impurity than the epitaxial layer 302
Low concentration n^-Type thin film layer (thin film semiconductor layer) 308 is provided
Have been. Specifically, n ^-Type epitaxial layer 30
The impurity concentration of 2 is 2 × 10¹⁶cm^-3And n^-Type thin film
The layer 308 has an impurity concentration of 1 × 10^Fifteencm^-3And the film thickness is 0.
It is 3 μm. Also, n^-Type thin film layer 308
The width in the direction away from the cell region is equal to the drain electrode 313.
When a reverse bias is applied between the transistor and the source electrode 312
The depletion layer is n^-End in the mold thin film layer 308
It has become a degree.

The n ⁻ type thin film layer 308 is basically formed around the semiconductor device so as to surround the cell region over the entire semiconductor device. The planar type M thus configured
Equipotential lines shown when a reverse bias is applied to the OSFET are shown by dotted lines in FIG. Thus, n
^- -type thin film layer 308 is formed, n ^- -type thin film layer 30
8 has a lower concentration than the n ⁻ -type epitaxial layer 2, so that the extension of the depletion layer in the lateral direction when the reverse bias is applied can be increased.

For reference, the results of measuring the maximum electric field strength in the depth direction under the field plate when the n ⁻ -type thin film layer 308 is formed and when it is not formed are shown in FIGS. 18A and 18B, respectively. ). When the distance shown in FIG. 18 is zero (Distance = 0), that is, when the maximum electric field strength at the interface of the thermal oxide film 309 is compared, it is 1.05 MV / cm in FIG.
In FIG. 8B, since it is 1.25 mv / cm, n ⁻
It can be seen that the maximum electric field intensity can be reduced by about 20% by forming the mold thin film layer 308.

As described above, the electric field intensity at the interface of thermal oxide film 309 can be reduced, and dielectric breakdown of thermal oxide film 309 can be prevented. Further, the p-type base region 303 is formed with a partially deep junction. By forming the region (second base region) 303a having a large junction depth, the curvature at the bottom of the p-type base region 303 can be reduced, and the electric field strength can be increased. Therefore, this region 3
03a can easily cause avalanche breakdown, and the breakdown voltage can be determined in the region 303a of the p-type base region 303 of the planar MOSFET. Note that since the formation position of the region 303a can be set arbitrarily, it can be formed at a position where the parasitic transistor formed by the planar MOSFET is difficult to operate. By doing so, the back electromotive energy tolerance during L load driving can be increased.

The n ⁺ -type region 311 and the electrode 323 connected to the n ⁻ -type thin film layer 308 shown in FIGS. 17, 20, and 21 are called an equipotential ring (EQR). The potential of the semiconductor device around the semiconductor device is made equal over the entire semiconductor device.
Basically, these are formed so as to surround the cell region around the semiconductor device, and the potential is a floating potential. In this embodiment, the n ⁺ type region 3
11 is connected to the n ⁻ -type thin film layer 308, but may be separated.

Next, the planar type MOS shown in FIG.
A method of manufacturing the FET will be described with reference to FIGS. [Step shown in FIG. 19A] A low-resistance n ⁺ -type silicon carbide semiconductor substrate 301 is prepared, and a high-resistance n ^-- type silicon carbide semiconductor layer 302 is epitaxially grown on this n ⁺ -type silicon carbide semiconductor substrate 301. .

[Step shown in FIG. 19B] In a surface layer portion of the n ⁻ -type silicon carbide semiconductor layer 302, ions are implanted into a region where a cell is to be formed, thereby forming a p-type base layer 303. [Step shown in FIG. 19C] On the n ⁻ -type silicon carbide semiconductor layer 302 including the p-type base layer 303, the impurity concentration is set to n ⁻ -type silicon carbide semiconductor layer 30 by epitaxial growth.
An n ⁻ -type thin film layer 350 lower than 2 is formed. The n ^-
Type thin film layer 350 is a surface channel layer 30 for forming a channel.
4 and the n ⁻ -type thin film layer 308 that plays a role in reducing the electric field intensity at the interface of the thermal oxide film 309 as described above.

As described above, since the step of forming the surface channel layer 304 for forming the channel and the step of forming the n ⁻ -type thin film layer 308 are also used, the number of additional steps can be increased as compared with the conventional case. Thus, the n ⁻ -type thin film layer 308 can be formed. [Step shown in FIG. 20 (a)] An n-type impurity is ion-implanted, and an n ⁺ -type source region 305 is provided in a predetermined region on the p-type base layer 303, and a contact n is provided in a predetermined region in the outer peripheral region.
^{The +} type layer 311 is formed.

[Step shown in FIG. 20B] A p-type impurity is ion-implanted, and the p-type base layer 3 is formed in the unit cell region.
03 so that the p-type base layer 30
In the n ⁻ -type thin film layer 304 on the substrate 3, portions other than the portion where the channel is formed (between the n ⁺ -type source layers 305 in the figure) are inverted to p-type. A region 307 is formed.

At this time, the p-type impurity is
Ion implantation is performed so that implantation is deeper than 03.
For this reason, the p-type base region 303 is configured to have a region 303a formed partially deep. This gives p
Avalanche breakdown can easily occur in a deeply formed portion of the mold base region 303. The formation position of the region 303a can be arbitrarily changed by changing the ion implantation mask position.

Although the region 303a is formed here, the formation of the region 303a is optional.
It need not be formed. In such a case, the p-type region 3
If the step 07 is formed simultaneously with the p-type base region 303, the step of forming the p-type region 307 can be simplified, so that the manufacturing process can be simplified. Also, the p-type region 3
07 is formed simultaneously with the p-type base region 303,
It is also possible to form only a necessary position in the mold region 307 at the same time as the region 303a, and to increase the junction depth at that portion.

[Step shown in FIG. 20C] An oxide film (SiO ₂ ) 360 having a predetermined thickness is formed on the p-type region 307 through a photolithography step. [Step shown in FIG. 21A] A thermal oxide film 309 is formed on the entire surface of the wafer by thermal oxidation. This thermal oxide film 309 forms a gate oxide film. After depositing polysilicon or the like, the gate electrode 306 is formed by patterning.

[Step shown in FIG. 21B] Thermal oxide film 30
An interlayer insulating film 318 is formed on the wafer including the substrate 9. Thereafter, after forming a contact hole in the interlayer insulating film 318, the aluminum wiring is patterned and the gate electrode 32 is formed.
0, a source electrode 312 and an electrode 322 serving as a field plate are formed. Then, the passivation film 3 is formed on the gate electrode 320, the source electrode 312, and the electrode 322.
70, and a drain electrode 31 is formed on the back surface of the wafer.
3 is completed to complete the planar MOSFET shown in FIG.

(Ninth Embodiment) Next, a ninth embodiment to which the present invention is applied will be described. In the present embodiment, the withstand voltage can be improved when the guard ring structure is employed in the outer peripheral region of the cell region. FIG.
2 shows a silicon carbide semiconductor device according to the present embodiment.

As shown in FIG. 22, in this embodiment, a planar MOSFET is used as a cell region. Since the overall configuration of the planar MOSFET is the same as in FIG. 17, the same components are denoted by the same reference numerals as in FIG. A p-type region 307 for preventing breakdown is formed around the cell region so as to surround the cell region.
And a p-type region 409 having a predetermined width that forms a guard ring. p-type region 307 and p-type region 409
Are formed on the surface of n ⁻ -type silicon carbide semiconductor layer 302. A plurality of p-type regions 409 are formed.
They are arranged at predetermined intervals from the mold region 307 toward the outside of the unit cell region.

[0103] Of the p-type regions 409, the one farthest from the cell region is electrically connected to the electrode 410 constituting the field plate. Further, between each of the plurality of p-type regions 409 constituting the guard ring, between the p-type region 407 and the p-type region 409,
Of the p-type regions 409 and further out of the cell region (on the side away from the cell region) from those located at the outermost periphery, the n ^- type silicon carbide semiconductor layer 302 has a higher impurity than the n ^- type epitaxial layer 302 An n ⁻ -type thin film layer 408 having a low concentration is provided. Specifically, the n ⁻ -type thin film layer 408 has an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a thickness of 0.3 μm.

The planar type MOSF thus constructed
Equipotential lines shown when a high voltage is applied to the drain of the ET are indicated by dotted lines in FIG. Thus, the n ⁻ type thin film layer 408 is formed, and the n ⁻ type thin film layer 408 is
^{Since the} concentration is lower than that of-type silicon carbide semiconductor layer 302, the lateral extension of the depletion layer can be increased.

As described above, the electric field intensity at the interface of the oxide film can be reduced, and the dielectric breakdown of the thermal oxide film 309 can be prevented. Next, a method of manufacturing the planar type MOSFET shown in FIG.
This will be described with reference to FIG. [Step shown in FIG. 23 (a)] A low-resistance n ⁺ -type silicon carbide semiconductor substrate 301 is prepared, and a high-resistance n ^-- type silicon carbide semiconductor layer 302 is epitaxially grown on the n ⁺ -type silicon carbide semiconductor substrate 301. .

[Step shown in FIG. 23B] A p-type base layer 303 is formed in a region where a unit cell is to be formed in a surface layer portion of n ⁻ -type silicon carbide semiconductor layer 302. [Step shown in FIG. 23C] An n ⁻ -type thin film layer 450 is formed on the n ⁻ -type silicon carbide semiconductor layer 302 including the p-type base layer 303 by an epitaxial growth method. The n ^-
Type thin film layer 450 is a surface channel layer 30 for forming a channel.
4 and an n ⁻ -type thin film layer 408 that plays a role in reducing the electric field intensity at the interface of the thermal oxide film 309 as described above.

[Step shown in FIG. 24A] An n-type impurity is ion-implanted, and n ^{+ is} implanted into a predetermined region on the p-type base layer 303.
An n ⁺ -type layer 311 for contact is formed in the mold source region 305 and a predetermined region in the outer peripheral region. [Step shown in FIG. 24B] A p-type impurity is ion-implanted, and in the unit cell region, an n ⁻ -type thin film layer 304 is formed on the p-type base layer 303 so as to make contact with the p-type base layer 303. Out of the portion other than the portion where the channel is to be formed (between the n ⁺ -type source layers 305 in the figure) is inverted to p-type, and in the outer peripheral region, a p-type region 307 for preventing breakdown is formed and this p-type region is formed. A plurality of p-type regions 409 serving as guard links are formed from 307 to the outside of the unit cell region.

At this time, by implanting ions so that the p-type impurity is implanted deeper than the p-type base layer 305, the p-type base region 305 can be formed partially deeper.
The withstand voltage of the element can be improved. [Step shown in FIG. 24C] An oxide film (Si) having a predetermined thickness is formed on the p-type region 307 through a photolithography step.
O ₂ ) 360 is formed. [Step shown in FIG. 25A] A thermal oxide film 309 is formed on the entire surface of the wafer by thermal oxidation. This thermal oxide film 309 forms a gate oxide film. After depositing polysilicon or the like, patterning is performed to form a gate electrode.

[Step shown in FIG. 25B] An interlayer insulating film 318 is formed on the wafer including the gate insulating film. Thereafter, after forming a contact hole in the interlayer insulating film 318, the aluminum wiring is patterned to form a gate electrode 320,
The source electrode 312 and the electrode 22 forming the field plate are formed. Then, passivation film 370 is formed on gate electrode 320, source electrode 312, and electrode 410, and n ⁺ -type silicon carbide semiconductor substrate 30
The drain electrode 313 is formed on the back surface of the semiconductor device 1 to complete the planar MOSFET shown in FIG.

(Other Embodiments) In addition, for example, the source electrode 12 formed on the n ⁺ -type source region 4 and the p-type silicon carbide semiconductor layer 3 and the back side surface of the n ⁺ -type silicon carbide semiconductor substrate 1 The leaving drain electrode 13 may be an electrode other than Ni. In the above-described embodiment, the n-channel vertical M
The case where the present invention is applied to the OSFET has been described. However, the present invention may be applied to a p-channel vertical MOSFET. May be applied.

Further, the grooves 7 and 5 may be perpendicular to the substrate surface, V-groove type, or U-groove type. Further, the groove side surface does not need to be flat, and may be a smooth curved surface. In the first to seventh embodiments, the description has been given of the case where the present invention is applied to the vertical power MOSFET using silicon carbide for the substrate. However, the present invention is applied to a semiconductor device using a silicon substrate for the substrate. You can also.

In the first embodiment, the mesa-shaped groove 5 and the groove 7 serving as a channel region formed in the cell region are formed in separate steps, but as shown in Japanese Patent Application Laid-Open No. In the case where a high-resistance semiconductor layer serving as a channel region is formed on the side surface of the semiconductor device 7, the high-resistance semiconductor layer and the high-resistance layer 6 can be formed at the same time. . Referring to the drawings, a semiconductor substrate 100 is prepared as shown in FIG.
A groove 5 and a groove 7 are formed as shown in FIG. Thereafter, the semiconductor device shown in FIG. 14B is formed by steps similar to those shown in FIG. 4C and thereafter. Thus, a semiconductor device in which the groove 5 and the groove 7 are simultaneously formed can be completed.

Note that, as in the sixth embodiment, the corners of the groove 5 are formed.
When the p-type layer region 201 is formed in
Form a high-resistance semiconductor layer to be a channel region on the side.
In this case as well, the high resistance that becomes the channel
The anti-semiconductor layer and the high resistance layer 6 can be formed simultaneously.
You. In the eighth and ninth embodiments, the p-type regions 307 and 40
Before forming 7, 409, n ^-Type thin film layers 304 and 404
Is formed, but may be formed later.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a vertical power MOSFET according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an electric field distribution of the vertical power MOSFET shown in FIG.

FIG. 3 is a view showing a manufacturing process of the vertical power MOSFET shown in FIG. 1;

FIG. 4 is a view showing a manufacturing step following FIG. 3;

FIG. 5 is a view showing a manufacturing step following FIG. 4;

FIG. 6 is a sectional view of a vertical power MOSFET according to a second embodiment of the present invention.

7 is a diagram showing an electric field distribution of the vertical power MOSFET shown in FIG.

FIG. 8 is a cross-sectional view of a vertical power MOSFET according to a third embodiment of the present invention.

FIG. 9 is a cross-sectional view of a vertical power MOSFET according to a fourth embodiment of the present invention.

10 is a diagram showing an electric field distribution of the vertical power MOSFET shown in FIG.

FIG. 11 is a cross-sectional view of a vertical power MOSFET according to a fifth embodiment of the present invention.

12 is a diagram showing an electric field distribution of the vertical power MOSFET shown in FIG.

FIG. 13 is a sectional view of a vertical power MOSFET according to a sixth embodiment of the present invention.

FIG. 14 is a sectional view of a vertical power MOSFET according to a sixth embodiment of the invention.

15 is a diagram comparing electric field distributions of the vertical power MOSFET shown in FIG. 14 and a conventional vertical power MOSFET.

FIG. 16 is a view showing a manufacturing process of the vertical power MOSFET shown in FIG. 16;

FIG. 17 is a sectional view of a vertical power MOSFET according to a seventh embodiment of the present invention.

18 is a diagram comparing electric field distributions of the vertical power MOSFET shown in FIG. 14 and a conventional vertical power MOSFET.

19 is a view illustrating a manufacturing process of the vertical power MOSFET illustrated in FIG. 17;

20 is a view illustrating a manufacturing step of the vertical power MOSFET following FIG. 19;

FIG. 21 is a view illustrating a manufacturing step of the vertical power MOSFET following FIG. 20;

FIG. 22 is a sectional view of a vertical power MOSFET according to an eighth embodiment of the present invention.

FIG. 23 is a view illustrating a manufacturing process of the vertical power MOSFET illustrated in FIG. 22;

FIG. 24 is a view illustrating a manufacturing step of the vertical power MOSFET following FIG. 23;

FIG. 25 is a view showing a manufacturing step of the vertical power MOSFET following FIG. 24;

FIG. 26 is a vertical power MOSFET according to another embodiment.
It is a figure showing the manufacturing process of T.

FIG. 27 is a diagram showing an electric field distribution of a conventional vertical power MOSFET having a mesa structure.

FIG. 28 is a diagram showing an electric field distribution of a conventional vertical power MOSFET having a mesa structure.

FIG. 29 is a diagram showing an electric field distribution of a conventional vertical power MOSFET employing a field plate structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n ^<+> type silicon carbide semiconductor substrate, 2 ... n < ^- > type silicon carbide semiconductor layer, 3 ... p-type silicon carbide semiconductor layer, 4 ... n ^<+> type source region, 5 ... groove | channel which comprises a mesa structure, 6 ... high Resistance layer, 7
... groove, 9 ... thermal oxide film, 10 ... gate electrode, 11 ... insulating film, 12 ... source electrode, 13 ... drain electrode, 30 ... p
Type silicon carbide semiconductor layer, 40 ... electrode layer, 50 ... electrode layer, 7
0 ... groove, 80 ... p-type silicon carbide semiconductor layer, 201 ... p-type layer region, 301 ... n ⁺ -type silicon carbide semiconductor substrate, 302 ...
n ⁻ type silicon carbide semiconductor layer, 303... p type base region, 3
04 ... surface channel layer, 305 ... n ⁺ type source region, 3
06 ... gate electrode layer, 307 ... p-type region, 308 ... n ^-
Mold thin film layer, 309: thermal oxide film, 312: source electrode, 3
13 ... drain electrode, 320 ... gate electrode, 322 ... electrode, 408 ... n ^- type thin film layer, 409 ... p-type region.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Rajesh Kumar 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Inside Denso Corporation (72) Inventor Mitsuhiro Kataoka 1-1-1, Showa-cho, Kariya City, Aichi Prefecture Inside

Claims (30)

[Claims] 1. A low-resistance layer of a first conductivity type, and a first semiconductor layer of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. A semiconductor substrate (100) having a second conductivity-type second semiconductor layer (3) formed on the first semiconductor layer, and having a surface of the second semiconductor layer as a main surface; A first conductivity type semiconductor region (4) formed in the second semiconductor layer and formed such that a junction is terminated at the main surface; and the semiconductor region and the second semiconductor region extending from the main surface. First and second grooves (7, 5) penetrating the semiconductor layer of (1), an electric field relaxation layer (6, 30, 50) formed on a side surface of the second groove (5); An insulating film (9) formed on the main surface including the surface of the first groove and the first groove (7); A gate electrode formed on the side (10), a first electrode in electrical contact with the semiconductor region (12)
And a second electrode (13) that is in electrical contact with the back side of the semiconductor substrate, wherein the electric field relaxation layer reduces electric field concentration in the insulating film. apparatus. 2. The semiconductor device according to claim 1, wherein said electric field relaxation layer is formed from a side surface of said second groove to a bottom surface of said second groove. 3. The electric field relaxation layer according to claim 1, wherein the electric field relaxation layer is formed of a first conductivity type material and has a higher resistance than the first semiconductor layer. Semiconductor device. 4. An electrode layer (12) for controlling a potential of the electric field relaxation layer on a surface of the insulating film formed on a surface of the electric field relaxation layer, and the electric field relaxation layer is formed by a predetermined amount by the electrode layer. 4. A voltage lower than a threshold voltage.
3. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the electric field relaxation layer is formed of a second conductivity type material. 6. A third groove (70) formed between the first groove and the second groove and penetrating from the main surface to the second semiconductor layer. The semiconductor device according to claim 1, wherein the second semiconductor layer is electrically divided by (70). 7. The semiconductor device according to claim 1, wherein said low-resistance layer, said first semiconductor layer, said second semiconductor layer, and said electric field relaxation layer are made of silicon carbide. A silicon carbide semiconductor device, characterized by: 8. The semiconductor device according to claim 1, wherein said low resistance layer, said first semiconductor layer, and said second semiconductor layer are made of silicon carbide, and said electric field relaxation layer is made of aluminum. A silicon carbide semiconductor device comprising an alloy. 9. A low-resistance layer of a first conductivity type and a first semiconductor layer of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. A semiconductor substrate (100) having a second conductivity-type second semiconductor layer (3) formed on the first semiconductor layer, and having a surface of the second semiconductor layer as a main surface; A first conductivity type semiconductor region (4) formed in the second semiconductor layer and formed such that a junction terminates at the main surface; and the semiconductor region and the second semiconductor region extending from the main surface. First and second grooves (7, 5) penetrating the semiconductor layer of (1), an insulating film (9) formed at least on the surface of the first and second grooves, and the first groove (7). A gate electrode (10) formed inside the insulating film and a first semiconductor layer forming a bottom surface of the second groove (5). Of a second conductivity type made second semiconductor region (80)
A first electrode (12) in electrical contact with the second semiconductor region and the first semiconductor region; and a second electrode (13) in electrical contact with the back side of the semiconductor substrate. A semiconductor device comprising: 10. A substrate of a first conductivity type, a first semiconductor layer of a first conductivity type formed on the substrate and having a higher resistance than the substrate, and a first semiconductor. A second semiconductor layer (3) of a second conductivity type formed on the layer; a groove (5) penetrating through the second semiconductor layer and reaching the first semiconductor layer; A first semiconductor layer formed in the first semiconductor layer and having a junction terminated on a surface of the second semiconductor layer;
A conductive semiconductor region (4), and an insulating film (9) formed on the channel region and the trench with the second semiconductor layer between the first semiconductor layer and the semiconductor region as a channel region. A gate electrode formed on the channel region via the insulating film; and a first electrode electrically connected to the semiconductor region.
And a second electrode (1) electrically contacting the back side of the substrate.
And 3) forming an electric field relaxation layer for reducing electric field concentration in the insulating film between the first semiconductor layer and the second semiconductor layer on the side surface of the groove and the insulating film. A semiconductor device characterized by the above-mentioned. 11. A low-resistance layer of a first conductivity type and a first semiconductor layer of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. And a second semiconductor layer (3) of the second conductivity type formed on the first semiconductor layer, and a semiconductor substrate (100) having a surface of the second semiconductor layer as a main surface is formed. Forming a first conductivity type semiconductor region (4) in which a junction terminates at the main surface in the second semiconductor layer; and forming the semiconductor region and the second semiconductor region from the main surface. Forming a mesa structure forming groove (5) forming a mesa structure penetrating the semiconductor layer; and forming an electric field relaxation layer (6, 30, 50) on at least a side surface of the mesa structure forming groove. And after the formation of the electric field relaxation layer, the semiconductor region and the second semiconductor are separated from the main surface. Forming a cell forming groove (7) constituting a cell part penetrating the layer; and an insulating film on a surface of the second semiconductor layer including the mesa structure forming groove and the cell part forming groove. Forming (9); forming a gate electrode (10) inside the insulating film in the cell portion forming groove; and a first electrode (11) electrically contacting the semiconductor region.
And a step of forming a second electrode (13) that is in electrical contact with the back surface of the semiconductor substrate. 12. A low-resistance layer of a first conductivity type, and a first semiconductor layer of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. And a second semiconductor layer (3) of the second conductivity type formed on the first semiconductor layer, and a semiconductor substrate (100) having a surface of the second semiconductor layer as a main surface is formed. Forming a first conductivity type semiconductor region (4) in which a junction terminates at the main surface in the second semiconductor layer; and forming the semiconductor region and the second semiconductor region from the main surface. Simultaneously forming a mesa structure forming groove (5) forming a mesa structure penetrating a semiconductor layer and a cell forming groove (7) forming a cell portion; and forming the mesa structure forming groove and the cell. Forming an insulating film (9) on the surface of the second semiconductor layer including a portion forming groove; Forming a gate electrode (10) on the inside of the insulating film in forming a groove, a first electrode in electrical contact with the semiconductor region (11)
And a step of forming a second electrode (13) that is in electrical contact with the back surface of the semiconductor substrate. 13. A low-resistance layer of a first conductivity type, and a first semiconductor layer of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. A semiconductor substrate (100) having a second conductivity-type second semiconductor layer (3) formed on the first semiconductor layer, and having a surface of the second semiconductor layer as a main surface; A first electrode layer (12) disposed on at least the second semiconductor layer of the main surface of the semiconductor substrate via an insulating film (9); and a first electrode layer (12) formed on the back surface side of the semiconductor substrate. The second electrode layer (1
3); a groove (5) penetrating through the second semiconductor layer to reach the first semiconductor layer; and a second conductivity type formed in a surface layer of the first semiconductor layer at a corner of the groove. And a semiconductor region (201). 14. A low-resistance layer of a first conductivity type, and a first semiconductor layer of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. A semiconductor substrate (100) having a second conductivity-type second semiconductor layer (3) formed on the first semiconductor layer, and having a surface of the second semiconductor layer as a main surface; A first conductivity type first semiconductor region (4) formed in a predetermined region of the second semiconductor layer and formed such that a junction terminates at the main surface; A first groove that penetrates a semiconductor region and the second semiconductor layer; a first groove that is formed to be spaced apart from the first groove and to surround the first groove; And the second
A second groove (5) penetrating through the semiconductor layer, and a second semiconductor region (201) of the second conductivity type formed in a surface portion of the first semiconductor layer at a corner of the second groove.
An insulating film (9) formed on the main surface including the first and second grooves (7, 5); and an insulating film formed inside the insulating film in the first groove. A gate electrode layer (10) and a first electrode (12) that is in electrical contact with the semiconductor region
And a second electrode layer (1) formed on the back side of the semiconductor substrate.
3) A silicon carbide semiconductor device comprising: 15. The second groove on a side surface of the second groove.
15. The silicon carbide semiconductor device according to claim 14, wherein an electric field relaxation layer (6) made of a semiconductor of the first conductivity type is provided on the surfaces of the semiconductor layer and the first semiconductor layer. . 16. The silicon carbide semiconductor device according to claim 14, wherein the second semiconductor region includes a portion where a side surface and a bottom surface of the second groove are in contact with each other. . 17. A low-resistance layer of a first conductivity type, and a first semiconductor layer of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. And a second semiconductor layer (3) of the second conductivity type formed on the first semiconductor layer, and a semiconductor substrate (100) having a surface of the second semiconductor layer as a main surface is formed. Forming a first conductive type first semiconductor region (4) having a junction terminated at the main surface in the second semiconductor layer; and forming the semiconductor region and the semiconductor region from the main surface. Forming a mesa structure forming groove (5) penetrating the second semiconductor layer; and forming a second conductivity type second groove in a surface layer portion of the first semiconductor layer at a corner of the mesa structure forming groove. 2 semiconductor regions (20
Forming a cell portion forming groove (7) constituting a cell portion penetrating the first semiconductor region and the second semiconductor layer from the main surface; and forming the mesa type. Forming an insulating film on the surface of the second semiconductor layer including the structure forming groove and the cell portion forming groove; and forming a gate electrode inside the insulating film in the cell portion forming groove. Forming a first electrode (11) that is in electrical contact with the first semiconductor region; and forming a second electrode (11) that is in electrical contact with the back side of the semiconductor substrate. 13) forming a semiconductor device. 18. The method according to claim 17, wherein the mesa structure forming groove and the cell portion forming groove are formed in the same step. 19. A low-resistance layer of a first conductivity type, and a first semiconductor layer of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. A unit cell formed in a predetermined region of the first semiconductor layer; and a unit cell provided around the cell region in which the unit cell is formed. A second element separation extending in a direction away from
A conductive element isolation layer (307); and a field plate (322) disposed on the element isolation layer via an insulating film (309) and extending beyond the element isolation layer outside the cell region. ), A first electrode (312) electrically in contact with the unit cell and the element isolation layer, and a second electrode (313) in electrical contact with the back side of the semiconductor substrate. And a first conductive type semiconductor thin film layer (308) having a higher resistance than the first semiconductor layer is provided between the insulating film disposed below the field plate and the first semiconductor layer. A silicon carbide semiconductor device characterized by being formed. 20. The semiconductor thin film layer, wherein when a predetermined reverse bias voltage is applied between the second electrode and the first electrode, the insulating film and the semiconductor thin film are separated from the element isolation layer. 20. The silicon carbide semiconductor device according to claim 19, wherein said silicon carbide semiconductor device is formed to be larger than a depletion layer extending outward in said semiconductor thin film layer along a layer interface. 21. The silicon carbide semiconductor device according to claim 19, wherein said semiconductor thin film layer is an epitaxial film grown on said first semiconductor layer. 22. A low-resistance layer of a first conductivity type (301), and a first semiconductor layer (302) of a first conductivity type formed on the low-resistance layer and having a higher resistance than the low-resistance layer. A unit cell formed in a predetermined region of the first semiconductor layer; and a unit cell provided around the cell region in which the unit cell is formed, in a direction away from the cell region in a surface layer portion of the first semiconductor layer. An extended element isolation layer (307) of element isolation type for element isolation, and an element isolation layer on a side of the surface layer of the first semiconductor layer farther from the cell region than the element isolation layer. A plurality of second semiconductor layers (409) of a second conductivity type having a predetermined width and arranged at predetermined intervals from each other, between each of the second semiconductor layers, and between the second semiconductor layer and the second semiconductor layer. Formed on the first semiconductor layer between the device isolation layer A first conductive type semiconductor thin film layer (408) having a higher resistance than the first semiconductor layer and a second semiconductor layer disposed on the element isolation layer via an insulating film (309). A field plate (322) that is electrically connected to the side farthest from the cell region and protrudes outside the cell region beyond the element isolation layer; and electrically connects the unit cell and the element isolation layer. First contact
And a second electrode (313) that is in electrical contact with the back surface of the semiconductor substrate. 23. A semiconductor thin film layer of a first conductivity type having a higher resistance than the first semiconductor layer, between the insulating film below the field plate and the first semiconductor layer.
23. The silicon carbide semiconductor device according to claim 22, wherein 24. A first conductive type first semiconductor layer (302) having a lower dopant concentration than the semiconductor substrate is formed on a main surface of a first conductive type semiconductor substrate (301) made of silicon carbide. Forming a plurality of second conductivity type first base regions (303) having a predetermined depth in a cell formation scheduled region of a surface layer portion of the first semiconductor layer; Forming a thin film layer (350) of a first conductivity type having a lower concentration than the first semiconductor layer on the first semiconductor layer, thereby forming a surface channel layer connected to the first base region; (304), a step of forming a thin film semiconductor layer (308) around the cell formation scheduled area, and a second conductivity type element for element isolation between the first base region and the thin film semiconductor layer. Forming a separation layer (307); Forming a first conductivity type source region (305) shallower than a depth of the first base region in a predetermined region of a surface layer portion of the source region; insulating the surface of the surface channel layer and the element isolation layer from each other; Forming a film (309), forming a gate electrode (320) on at least the insulating film on the surface channel layer, and forming a source electrode (contact with the first base region and the source region). 312); and forming a field plate (322) electrically connected to the gate electrode or the source electrode via the insulating film from above the element isolation layer to the outside. A method for manufacturing a silicon carbide semiconductor device. 25. A second conductive type second base region (303) deeper than the first base region in a predetermined region of the first base region and a predetermined region of the element isolation layer.
3. The method according to claim 2, further comprising the step of forming a).
5. The method for manufacturing a silicon carbide semiconductor device according to item 4. 26. A first conductive type first semiconductor layer (302) having a lower dopant concentration than the semiconductor substrate is formed on a main surface of a first conductive type semiconductor substrate (301) made of silicon carbide. Forming a plurality of second conductivity type base regions (303) having a predetermined depth in predetermined regions of a surface portion of the first semiconductor layer; Forming a first conductivity type thin film layer (450) having a lower concentration than the first semiconductor layer, thereby forming a surface channel layer (3) connected to the base region.
04), a step of forming a thin film semiconductor layer (408) around the cell formation planned region, and a second conductive type second region having a junction depth deeper than the base region in a predetermined region of the base region. A base region is formed, and an element isolation layer (307) for element isolation arranged around the base area and a plurality of ring layers for electric field relaxation arranged at predetermined intervals around the element isolation layer ( 4
09); forming a first conductivity type source region (305) having a junction depth shallower than a depth of the base region in a predetermined region of a surface layer portion in the base region; Forming an insulating film (309) on the surface of the channel layer and the device isolation layer; forming a gate electrode (320) on the insulating film at least on the surface channel layer; Forming a source electrode (312) in contact with the region, wherein the outermost one of the ring layers is electrically connected so as to protrude from the ring layer to the outside of the cell formation planned region. Forming a field plate (410) with the insulating film interposed therebetween. 27. A first conductive type first semiconductor layer (302) having a lower dopant concentration than the semiconductor substrate is formed on a main surface of a first conductive type semiconductor substrate (301) made of silicon carbide. Forming a plurality of second conductivity type base regions (303) having a predetermined depth in a cell formation planned region of a surface layer portion of the first semiconductor layer, and forming a plurality of base regions around the base region. The second conductivity type element isolation layer (30)
7) and a step of forming a plurality of second conductivity type ring layers (409) arranged at predetermined intervals around the element isolation layer; and forming the first semiconductor layer on the first semiconductor layer. Forming a first conductivity type thin film layer having a lower concentration than the semiconductor layer to form a surface channel layer (304) connected to the base region;
A thin-film semiconductor layer (408) around the area where the cell is to be formed;
Forming a first region connected to the surface channel layer in a predetermined region of a surface layer of the base region, the first region being shallower than a depth of the base region.
Forming a source region of conductivity type; forming an insulating film on the surface of the surface channel layer and the element isolation layer; and forming a gate electrode on the insulating film at least on the surface channel layer. (320)
Forming a source electrode (312) in contact with the base region and the source region; and connecting the outermost one of the ring layers to the base layer and the source region. Forming a field plate (410) with the insulating film interposed therebetween so as to protrude outside the cell formation scheduled region. 28. A semiconductor substrate including a semiconductor layer of a first conductivity type, a semiconductor region of a second conductivity type formed on the semiconductor layer of the first conductivity type, and a semiconductor region of a first conductivity type formed thereon. A semiconductor device comprising: a cell region having a semiconductor region; and a peripheral region located around the cell region, wherein the peripheral region is in contact with a surface of the semiconductor layer of the first conductivity type. A semiconductor device, wherein a first conductivity type semiconductor electric field relaxation region having a higher resistance than the first conductivity type semiconductor layer is formed. 29. In the peripheral region, a semiconductor layer of the second conductivity type is formed on the semiconductor layer of the first conductivity type, and the semiconductor layer of the second conductivity type is formed from the surface of the semiconductor layer of the second conductivity type. 29. The semiconductor device according to claim 28, wherein a groove reaching the semiconductor layer is formed, and the semiconductor electric field relaxation region is formed on a side surface of the groove. 30. The semiconductor device according to claim 28, wherein the first conductivity type semiconductor electric field relaxation region is formed on the first conductivity type semiconductor layer in the peripheral region.