JP2001127285A - Vertical field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical field-effect transistor which decreases in on-state resistance without reducing resistance to pressure between a drain electrode and a source electrode. SOLUTION: On the bottoms and the sides of a plurality of P-type base regions 24 provided on an N-type drain region 22, P-type electric field relaxing layers 31 are provided which are 1×1015 atoms/cm3 to 1×10 atoms/cm3 in concentration of impurity. And then, a region between the adjacent electric field relaxing layers 31 is formed as an N-type connecting region 23a, which is substantially equal to the electric field relaxing layer 31 in impurity concentration. A surface layer of the N-type connecting region 23a is formed as an N-type connecting region 23b, which is equal to the drain region 22 in impurity concentration. A distance is set between the adjacent electric field relaxing layers 31 such that the connecting regions 23a and 23b are depleted completely while an off-control voltage is applied to the gate electrode and a reverse voltage applied between the drain electrode 30 and the source electrode 29 is set at 100 V or lower.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a vertical field effect transistor, and more particularly to an insulated gate vertical field effect transistor having high output characteristics.

[0002]

2. Description of the Related Art A gate planar type power MOSFET which is a vertical field effect transistor of this kind is disclosed in Japanese Patent No. 2771.
No. 172 publication. Hereinafter, a MOSFET substantially the same as the MOSFET disclosed in this publication will be described with reference to FIG. A low-concentration N- type drain region 2 is formed on a high-concentration N + type semiconductor substrate 1 by an epitaxial growth method. Next, N-type impurity ions are implanted by ion implantation, and thermal diffusion is performed to form an N @ + -type connection region 3a. Next, P-type impurity ions are ion-implanted from above the N + -type connection region 3a to reduce the N-type impurity concentration on the surface of the N + -type connection region 3a, and the same as the concentration of the N − -type drain region 2. N-type connection region 3b is formed. Next, a gate oxide film 8a is formed, and a polycrystalline layer is grown thereon to form a gate electrode 7. Next, an insulating film 8b is formed on the gate electrode 7 to insulate the gate electrode 7. next,
A P-type base region 4, a P + -type diffusion layer 5, an N + -type source region 6, a source electrode 9 and a drain electrode 10 are formed by ion implantation, CVD, dry etching, metal deposition, or the like.

[0003]

However, when downsizing a vertical field effect transistor chip of this kind, it is necessary to reduce the on-resistance Ron per unit area so as not to increase the total on-resistance of the chip. However, this has been realized by increasing the number of cells per unit area by reducing the size of the unit cell and improving the gate width per unit area as the integration technology improves. . However, in the case of the MOSFET having the above configuration,
As the miniaturization progresses, the width of the connection regions 3a and 3b between the base regions 4 also decreases, and the resistance R _JFET due to the JFET component in the connection regions 3a and 3b becomes smaller than the ON resistance Ron.
Becomes dominant, so that if the size is further reduced, the on-resistance Ron will not decrease. Then, the resistance R
_In order to lower the _JFET , it is conceivable to increase the impurity concentration of the N + -type connection region 3a. However, if the impurity concentration of the N + -type connection region 3a is to be increased, as shown in FIG. When a control voltage is applied and a reverse voltage is applied between the drain electrode and the source electrode, the extension of the depletion layer spreading to the N side of the PN junction between the base region 4 and the connection regions 3a and 3b is reduced, and the N + type connection region 3a Is not completely depleted, the depletion layer is no longer flat, and an electric field is concentrated around the R-shaped corner formed by the bottom surface and the side surface of the base region 4, and the curvature of the corner of the base region 4 causes the drain electrode and the source electrode The breakdown voltage is determined, and the breakdown voltage is lower than when the depletion layer is flat. In order to completely deplete the N + type connection region 3a after increasing the impurity concentration, it is necessary to narrow the space between the base regions 4. On the other hand, the resistance _RJFET is increased, and eventually the on-resistance Ron is reduced. Can not. This reduction in withstand voltage can be avoided to some extent by increasing the thickness of the drain region 2 to reduce the electric field concentration around the corner of the base region 4.
The resistance Rd is increased by increasing the thickness of
As a result, the on-resistance Ron cannot be reduced. An object of the present invention is to provide a vertical field effect transistor in which the on-resistance Ron is reduced without lowering the withstand voltage between the drain electrode and the source electrode.

[0004]

(1) In a vertical field effect transistor according to the present invention, an on-control voltage is applied to a gate electrode, and a voltage applied between a drain electrode and a source electrode causes an adjacent other conductivity type transistor to be turned on. In a vertical field-effect transistor in which a current flows through a channel of a base region through a connection region of one conductivity type sandwiched between base regions, the base region has the same conductivity type as the base region around the bottom surface and side surfaces of the base region. The other conductivity type electric field relaxation layer having a lower impurity concentration range is arranged, and the impurity concentration range of the connection region is the same as that of the electric field relaxation layer. When an off control voltage is applied to the gate electrode, the drain electrode and the source are reduced. The connection region is completely depleted when the reverse voltage applied between the electrodes is within 100 V. According to the above means, when an off-control voltage is applied to the gate electrode and a reverse voltage is applied between the drain electrode and the source electrode, the electric field in the vicinity of the R-shaped corner formed by the bottom surface and the side surface of the electric field relaxation layer by the electric field relaxation layer The concentration can be alleviated, and the spread of the depletion layer to the one conductivity type side of the PN junction between the electric field relaxation layer and the connection region can be flattened. Therefore, the breakdown voltage can be determined substantially by the thickness and resistivity of the drain region. In order to ensure the same level of breakdown voltage as before, the thickness of the drain region can be reduced or the resistivity can be reduced, so that the resistance Rd determined by the thickness and the resistivity of the drain region can be reduced.
The on-resistance Ron per unit area can be reduced. (2) In the vertical field effect transistor according to the present invention, in the above item (1), the impurity concentration range of the electric field relaxation layer is in a range of 1 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . It is characterized by being. (3) In the vertical field effect transistor according to the present invention, in the above item (1) or (2), the impurity concentration of the connection region is determined by a resistivity obtained by epitaxial growth. (4) In the vertical field effect transistor according to the present invention, in any one of the above items (1) to (3), the electric field relaxation layer and the connection region are arranged on a low-concentration one-conductivity-type drain region; The connection region has a low-concentration one-conductivity-type connection region in a surface layer thereof, which is the same as the impurity concentration range of the drain region. (5) A vertical field-effect transistor according to the present invention includes a one-conductivity-type drain region formed on a semiconductor substrate at a low concentration;
One conductivity type connection region formed at a medium concentration on the drain region, a gate electrode formed on the connection region via a gate oxide film, and a plurality of other conductive regions formed on the connection region using the gate electrode as a mask. A base region, and a different conductivity type electric field relaxation layer in which the gate electrode is used as a mask and the base region is deeper and lower in concentration than the base region at the same location as each base region, and the impurity concentration range is the same as the connection region. A source region of one conductivity type formed at a high concentration in the base region using the gate electrode as a mask. (6) In the vertical field effect transistor according to the present invention, in the above item (5), the electric field relaxation layer and the connection region have an impurity concentration of 1 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ at.
oms / cm ³ . (7) In the vertical field effect transistor according to the present invention, in the above item (5) or (6), the connection region is formed by epitaxial growth. (8) In the vertical field effect transistor according to the present invention, in the above item (6) or (7), the distance between the adjacent electric field relaxation layers among the plurality of electric field relaxation layers is set to the drain region and the source region. 100V reverse voltage applied between
Within this range, the connection region is completely depleted. (9) In the vertical field-effect transistor according to the present invention, in any one of the above-mentioned items (5) to (8), the connection region is formed such that the drain region and the impurity concentration range are formed in a surface layer below the gate oxide film. It has one conductive type connection region formed identically.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An N-channel MOSFET according to an embodiment of the present invention will be described below with reference to FIG. First, the structure will be described. In the figure, reference numeral 21 denotes an N + -type semiconductor substrate having a high concentration and one conductivity type, and an N − -type drain layer 22 having a low concentration and one conductivity type is provided on the semiconductor substrate 21. An impurity concentration of 1 × 10 ¹⁵ on the drain layer 22
It has a plurality of P − -type electric field relaxation layers 31 of low concentration and other conductivity type in the range of atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . The surface layer of each electric field relaxation layer 31 has a P-type base region 24 of a medium concentration and other conductivity type having a higher impurity concentration than that of the electric field relaxation layer 31. And a P + -type diffusion layer 25 of another conductivity type. The depth between adjacent electric field relaxation layers 31 of the electric field relaxation layers 31 is substantially the same as the depth of the electric field relaxation layers 31 and the impurity concentration is 1 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / c.
N-type connection region 23 of a medium-concentration one conductivity type in the range of m ³
a and the impurity concentration formed on this surface layer
2 and an N-type connection region 23b of the same order. Part of source region 26, base region 24, electric field relaxation layer 31
And a gate electrode 27 on the N @-type connection region 23b via a gate oxide film 28a.
A source electrode 29 electrically contacts the P + type diffusion layer 25 and the source region 26 through the contact window 8b, and a drain electrode 30 electrically contacts the semiconductor substrate 21 on the back surface of the chip. . The space between adjacent electric field relaxation layers 31 is completely depleted when the off-control voltage is applied to the gate electrode 27 and a reverse voltage is applied between the drain electrode 30 and the source electrode 29 when the N-type connection region 23a is 100 V or less. Are separated from each other.

According to the above configuration, when an off-control voltage is applied to the gate electrode 27 and a reverse voltage is applied between the drain electrode 30 and the source electrode 29, the electric field relaxation layer 31 causes the bottom surface and the side surfaces of the electric field relaxation layer 31 to move. Since the electric field concentration around the corners of the R shape can be alleviated and the depletion layer of the PN junction between the electric field relaxation layer 31 and the connection regions 23a and 23b on the N side can be flattened as shown in FIG. The withstand voltage can be determined by the thickness and the resistivity of the drain region 22, and when the same level of withstand voltage as in the related art is ensured, the thickness of the drain region 22 can be reduced or the resistivity can be reduced. And the resistance Rd determined by the resistivity can be reduced, and therefore, the on-resistance Ron per unit area can be reduced.

Next, the manufacturing method will be described with reference to FIGS.
This will be described with reference to FIG. First, as shown in FIG. 2A, after the completion of this step, a first step is performed so that a withstand voltage of, for example, 600 V or more can be secured on the N + type semiconductor substrate 21.
After an N − -type drain region 22 having a selected thickness and resistivity is formed by an epitaxial growth method, an impurity concentration of, for example, 5 μm and an impurity concentration of 1 × 1 is formed on the drain region 22.
An N-type connection region 23a having a resistivity selected from a range of 0 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ is formed by epitaxial growth, and an extremely shallow surface layer of the N-type connection region 23a is drained. P-type impurity ions are ion-implanted by selecting ion-implantation conditions by the ion-implantation method so that the impurity concentration becomes substantially equal to the impurity concentration of the region 22, the N-type impurity concentration in the surface layer is reduced, and the N− type connection is performed. The region 23b is formed.

Next, in a second step, FIG.
As shown in FIG. 2B, after the completion of the first step, a gate oxide film 28a is formed on the surface of the N @-type connection region 23b by thermal oxidation, and a polycrystalline silicon layer is grown on the surface by the CVD method. The gate electrode 2 is formed by selectively leaving the crystalline silicon layer by photolithography and dry etching.
7 is formed. Thereafter, using gate electrode 27 as a mask, the diffusion depth is substantially the same as the boundary between N − type drain region 22 and N type connection region 23a, the concentration of P type impurity is lower than that of base region 24, and 1 × 10 ¹⁵ atoms / cm ³ -1 × 10
^A P − -type electric field relaxation layer 31 having a range of ¹⁶ atoms / cm ³ is formed by selecting an ion implantation condition and a thermal diffusion condition by an ion implantation method and a thermal diffusion method. The distance between the adjacent electric field relaxation layers 31 is determined by the distance between the drain electrode 30 and the source electrode 2.
During the application of a reverse voltage, the N-type connection regions 23a are completely depleted within 100 V during the application of the reverse voltage.

The following P-type base region 24, P + -type base region 25, N + -type source region 26, insulating film 28b, source electrode 29 and drain electrode 30 are formed by a known method.

In the above embodiment, the N-type is used as one conductivity type and the P-type is used as another conductivity type, but the P-type may be used as one conductivity type and the N-type may be used as another conductivity type. Further, the N-type connection region 23a has been described as being formed by the epitaxial growth method. However, the N-type connection region 23a may be formed in the surface layer of the N − -type drain region 22 by the ion implantation method or the diffusion method. Further, although the description has been given of the case where the N− type connection region 23b is formed on the surface layer of the N− type connection region 23a, the N− type connection region 23b may not be formed.

[0011]

According to the present invention, an electric field relaxation layer of the other conductivity type having the same conductivity type as the base region and having a lower concentration than the base region is provided around the bottom surface and side surfaces of the base region. Is approximately the same as the electric field relaxation layer, and when an off-control voltage is applied to the gate electrode and a reverse voltage is applied between the drain electrode and the source electrode, the adjacent low-concentration other conductive layers are completely depleted within 100 V when the connection region is completely depleted. Since the interval between the mold base regions is increased, the on-resistance Ron per unit area can be reduced without lowering the withstand voltage, and the chip can be further reduced in size as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a vertical power MOSF according to an embodiment of the present invention.
Sectional drawing of the principal part of ET.

FIG. 2 is an essential part cross sectional view showing a manufacturing step of the vertical power MOSFET of FIG. 1;

FIG. 3 is a schematic cross-sectional view showing how a depletion layer is formed in the vertical power MOSFET of FIG.

FIG. 4 is a sectional view of a main part of a conventional vertical power MOSFET.

FIG. 5 is a schematic cross-sectional view showing how a depletion layer is formed in the vertical power MOSFET of FIG.

[Explanation of symbols]

 Reference Signs List 21 semiconductor substrate 22 N- type drain region 23a N-type connection region 23b N- type connection region 24 P-type base region 25 P + -type diffusion layer 26 N + -type source region 27 Gate electrode 28a Gate oxide film 28b Insulating film 29 Source electrode Reference Signs List 30 drain electrode 31 P- type electric field relaxation layer

Claims (9)

[Claims] An ON control voltage is applied to a gate electrode, and a voltage applied between a drain electrode and a source electrode is applied to a base region via a connection region of one conductivity type sandwiched between adjacent base regions of another conductivity type. A vertical field-effect transistor that allows a current to flow through the channel of the other conductivity type around the bottom surface and side surfaces of the base region, the other conductivity type electric field relaxation layer having the same conductivity type as the base region and a lower impurity concentration range than the base region. The connection region is completely depleted when the reverse concentration applied between the drain electrode and the source electrode is within 100 V when an off-control voltage is applied to the gate electrode, with the impurity concentration range of the connection region being the same as that of the electric field relaxation layer. A vertical field-effect transistor, characterized in that the transistor is formed into a vertical field-effect transistor. 2. An impurity concentration range of said electric field relaxation layer is 1 × 1.
2. The vertical field effect transistor according to claim 1, wherein the range is from 0 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ . 3. The vertical field effect transistor according to claim 1, wherein the impurity concentration of the connection region is determined by a resistivity obtained by epitaxial growth. 4. The low-concentration one-conductivity-type connection, wherein the electric-field relaxation layer and the connection region are disposed on a low-concentration one-conductivity-type drain region. The vertical field effect transistor according to claim 1, further comprising a region. 5. A drain region of one conductivity type formed at a low concentration on a semiconductor substrate, a connection region of one conductivity type formed at a medium concentration on the drain region, and a gate oxide film formed on the connection region. A gate electrode, a plurality of other conductivity type base regions formed in the connection region using the gate electrode as a mask, and a lower concentration deeper than the base region at the same location as the base region using the gate electrode as a mask, and A vertical field effect transistor comprising: a different conductivity type electric field relaxation layer having the same impurity concentration range as the connection region; and a one conductivity type source region formed at a high concentration in the base region using the gate electrode as a mask. 6. An impurity concentration of the electric field relaxation layer and the connection region is 1 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm.
6. The vertical field-effect transistor according to claim 5, which is in a range of cm ³ . 7. The vertical field effect transistor according to claim 5, wherein said connection region is formed by epitaxial growth. 8. When the distance between adjacent electric field relaxation layers of the plurality of electric field relaxation layers is controlled to be off, the connection region is completely formed when a reverse voltage applied between the drain region and the source region is within 100V. The vertical field-effect transistor according to claim 6 or 7, wherein the depletion distance is set to a depletion distance. 9. The connection region according to claim 5, wherein the connection region has a one-conductivity-type connection region formed in the surface layer below the gate oxide film and having the same impurity concentration range as the drain region. Vertical field effect transistor.