JP3496509B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to an insulated gate field effect transistor, and more particularly to a vertical power MOSFET for high power.

[0002]

2. Description of the Related Art Conventionally, there is a storage channel type silicon carbide semiconductor device in which a thin film semiconductor layer (side wall channel film) is formed on the side surface of a groove and a storage channel can be formed by this thin film semiconductor layer. As an example of this storage channel type silicon carbide semiconductor device, Japanese Patent Application Laid-Open No. 9-741
There is a trench gate type power MOSFET disclosed in Japanese Patent No. 91. This groove gate type power MOSFET will be described with reference to FIG.

In the trench gate type power MOSFET, n ⁺
Type single crystal silicon carbide (SiC) semiconductor substrate (hereinafter referred to as n ⁺
Type silicon carbide substrate) 1 and n ⁻ type epitaxial layer 2
And a semiconductor substrate 4 made of hexagonal single-crystal silicon carbide constituted by the p-type epitaxial layer 3 is used. A semiconductor device is formed with the upper surface (main surface) of the semiconductor substrate 4 as a substantially (0001−) carbon surface.

Predetermined area on the surface of the p-type epitaxial layer 3
In the area, n⁺The mold source region 5 is formed, and n⁺Type
A trench 7 is formed at a predetermined position in the source region 5.
Has been. This groove 7 is n⁺Type source region 5 and p type epi
Penetrating through the axial layer 3 ^-Type epitaxial layer 2
The side surface 7 that has reached and is substantially perpendicular to the surface of the p-type epitaxial layer 3.
a bottom surface 7b parallel to the surfaces of the a and p type epitaxial layers 3
have.

On the side surface 7a of the groove 7, a thin film of n ^-- type silicon carbide formed on the surfaces of the n ⁺ -type source region 5, the p-type epitaxial layer 3 and the n ^-- type epitaxial layer 2 by the epitaxial growth method. A semiconductor layer 80 is provided. A gate insulating film (gate oxide film) 9 is formed inside the groove 7, a gate electrode layer 10 is filled in the gate oxide film 9, and an interlayer insulating film 11 is formed on the gate electrode layer 10. It is arranged. Further, a source electrode layer 12 is formed on the surface of the n ⁺ type source region 5 and on the surface of the p type epitaxial layer 3 including on the interlayer insulating film 11, and the source electrode layer 12 serves as the n ⁺ type source region 5. Both are in contact with the p-type epitaxial layer 3. A drain electrode layer 13 is formed on the front surface (back surface of semiconductor substrate 4) of n ⁺ type silicon carbide semiconductor substrate 1.

Groove gate type power M configured as described above
In the OSFET, the thin film semiconductor layer 80 is used as a channel forming region, and a voltage is applied to the gate electrode layer 10 to apply a voltage to the gate oxide film 9
An electric field is applied to the thin film semiconductor layer 80 to induce a storage-type channel so that a current flows between the source electrode layer 12 and the drain electrode layer 13. By doing so, the impurity concentration of the p-type epitaxial layer 3 and the impurity concentration of the n-type thin film semiconductor layer 80 in which the channel is formed can be controlled independently, and the impurity concentration of the p-type epitaxial layer 3 can be increased. , N ⁺ type source region 5
The thickness of the p-type epitaxial layer 3 sandwiched between the n ⁻ -type epitaxial layer 2 and the n ⁻ -type epitaxial layer 2 is reduced, the channel length is shortened, and the trench gate type power MOSFET has high breakdown voltage and low on-resistance.

[0007]

In the above-mentioned conventional trench gate type power MOSFET, the thin film semiconductor layer 80 for forming the storage channel is formed by digging the trench 7 and then by epitaxial growth. Therefore, epitaxial growth is required to form the thin film semiconductor layer 80, and there is a problem that the manufacturing process becomes long.

The present invention has been made in view of the above points, and an object of the present invention is to make it possible to form a channel layer for forming a storage channel provided on a side surface of a groove without using epitaxial growth.

[0009]

In order to achieve the above object, the following technical means are adopted. In the invention according to claims 1 to 4, a semiconductor substrate (4) including a groove (7).
An oxide film (33) is formed on the main surface of, and ion implantation is performed using the oxide film (33) as a mask to form the groove (7).
The thin film semiconductor layer (8) of the first conductivity type is formed on the side surface (7a).

Thus, when the oxide film (33) is formed on the main surface of the semiconductor substrate (4) including the groove (7), the oxide film (33) is thin on the side surface (7a) of the groove (7), The other parts are thickly formed. Therefore, this oxide film (3
By performing ion implantation using 3) as a mask, the thin film semiconductor layer (8) for forming the storage channel can be formed without using epitaxial growth.

The invention according to claim 3 is characterized in that the side surface (7a) of the groove (7) is tapered. By thus forming the groove (7) in a tapered shape, the ion implantation for forming the thin film semiconductor layer (8) can be performed from the direction normal to the surface of the semiconductor substrate (4). It is possible to simplify.

By controlling the thickness of the thin film semiconductor layer (8) in this way, the characteristics of the semiconductor device can be made a normally-off type. According to the invention described in claim 4, the thickness of the oxide film on the bottom surface of the groove can be made larger than the thickness on the side surface. As a result, the thin film semiconductor layer for forming the storage channel can be reliably formed only on the side surface by ion implantation.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention shown in the drawings will be described. FIG. 1 shows a normally-off type n-channel type trench gate type power MOS according to the present embodiment.
A sectional view of an FET (hereinafter, referred to as a vertical power MOSFET) is shown. This device is preferably applied to an inverter or a vehicle alternator rectifier.

The structure of the vertical power MOSFET will be described with reference to FIG. However, the vertical power MOSFET in this embodiment is the MOSFET shown in FIG. 9 described above.
Since it has almost the same structure as T, only different parts will be described. In the vertical power MOSFET of this embodiment, the same parts as those of the MOSFET shown in FIG. 9 are denoted by the same reference numerals.

In the MOSFET shown in FIG. 9, the thin film semiconductor layer 80 for forming the storage channel is formed by epitaxial growth. However, it is assumed that the thin film semiconductor layer 80 plays a role similar to that of the thin film semiconductor layer 80 in this embodiment.
Are formed by ion implantation. The manufacturing process of the vertical power MOSFET shown in FIG. 1 will be described with reference to FIGS.

[Step shown in FIG. 2 (a)] First, n ^{+ of} about 400 μm whose main surface is a (0001−) carbon surface.
A type silicon carbide substrate 1 is prepared, an n ⁻ type epitaxial layer 2 having a thickness of about 10 μm is grown on the surface thereof, and a p type epitaxial layer 3 having a thickness of about 2.5 μm is further grown on the n ⁻ type epitaxial layer 2. Thus, the semiconductor substrate 4 including the n ⁺ type silicon carbide substrate 1, the n ⁻ type epitaxial layer 2 and the p type epitaxial layer 3 is formed. In addition,
The crystal axis of the n ⁺ -type silicon carbide substrate 1 is tilted by 3.5 ° to 8 ° to form the n ⁻ -type epitaxial layer 2 and the p-type epitaxial layer 3
Therefore, the plane orientation of the main surface of the semiconductor substrate 4 is approximately a (0001−) carbon plane.

[Step shown in FIG. 2B] Next, an n type impurity (for example, nitrogen) is ion-implanted into a predetermined region of the surface layer portion of the p type epitaxial layer 3 to form an n ⁺ type source region 5. . [Step shown in FIG. 2C] A silicon nitride film (Si ₃ N 3) is formed on the p-type epitaxial layer 3 including the n ⁺ -type source region.
₄ film) 31 is formed, and then a silicon nitride film 31
An LTO film 32 is formed on top. Then, photo etching is performed to remove the silicon oxide film 31 and the LTO film 32 in the groove formation planned region. At this time, the photo
In the etching, the groove 7 to be formed later is [112-0].
The mask is aligned so that it is substantially parallel to the direction. Since the interface state density is the minimum in the [112-0] direction,
The breakdown voltage can be improved due to the reduction of the interface state density. Since the groove 7 is formed under such conditions, the groove 7
When viewed from above, the planar shape of the side surface 7a of the groove 7 is a hexagon having the same interior angle.

If the groove 7 is made substantially parallel to the [11-0] direction instead of the [112-0] direction,
The carbon atom density can be reduced, and by selecting this direction, it is possible to reduce the interface state density due to the carbon atoms. Subsequently, by using RIE as a dry etching method, the n ⁺ type source region 5 is formed.
And a groove 7 penetrating both the p-type epitaxial layer 3 and the n ⁻ -type epitaxial layer 2 is formed. At this time, R
By controlling the IE gas component (ratio) and etching time, the side surface 7a of the groove 7 forms a predetermined angle with the bottom surface 7b (the surface direction of the semiconductor substrate 4).
In the present embodiment, the side surface 7a of the groove 7 is 1 with respect to the bottom surface 7b.
The angle is set to 05 °, that is, the side surface 7a of the groove 7 is tapered.

As an example, SF ₆ + O _{2 is} used as an etching solution.
Is adopted and the ratio of O ₂ is changed, the groove 7
FIG. 5 shows how the inclination of the side surface 7a changes. The angle of the side surface 7a of the groove 7 shown in this figure is
The angle formed with respect to the normal direction of the semiconductor substrate 4 is shown, and the angle formed by the side surface 7a of the groove 7 and the bottom surface 7b is 90 degrees.
This corresponds to α when expressed as + α °. Based on this figure
In the present embodiment, the side surface 7a of the groove 7 is 1 with respect to the bottom surface 7b.
The O ₂ ratio is set to about 50% so as to be 05 °.

[Step shown in FIG. 3A] By heat treatment,
An oxide film 33 is formed on the entire upper surface of the wafer including the inside of the groove 7. At this time, the oxide film 33 is formed thin on the side surface 7a of the groove 7 and thick on the other portions. Oxide film 33
The specific film thickness of is different depending on the heat treatment conditions. For example, when heat treatment is performed at 1080 ° C. for 6 hours in a wet oxidizing atmosphere, the side surface 7a of the groove 7 has a thickness of about 60 nm, and the other portions are It becomes about 300 nm.

[Step shown in FIG. 3B] Then, using the oxide film 33 as a mask, ions of n-type impurities are ion-implanted from the direction normal to the semiconductor substrate 4 (above the plane of the drawing). As a result, the thin film semiconductor layer 8 is formed by transmitting n-type impurity ions into the side surface of the groove 7 through the side surface 7a of the groove 7 of the oxide film 33, which is thin.

At this time, as described above, the side surface 7a of the groove 7 is formed.
Is tapered and the (0001-) C plane is the main surface, a thin oxide film can be selectively formed on the side surface 7a due to the anisotropy of oxidation, and the ion implantation from the normal direction of the semiconductor substrate 4 is performed. Since the thin film semiconductor layer 8 can be formed by this, the direction of ion implantation can be easily set.

The conditions of ion implantation at this time differ depending on the thickness of the oxide film 33, but at least the oxide film 33 is used.
It is necessary to set the energy so that the n-type impurity ions do not pass through the portion other than the side surface 7a of the groove 7 and the thin film semiconductor layer 8 formed on the side surface 7a of the groove 7 has a desired thickness. For example, in this embodiment, the thickness of the thin film semiconductor layer 8 is set to 200 to 300 nm.

Here, in order to make the vertical power MOSFET a normally-off type, the thickness of the thin film semiconductor layer 8 is determined based on the following mathematical formula. Vertical power MOSFET
In order to make the transistor normally-off type, it is necessary that the depletion layer spreading in the n ⁻ type layer has a sufficient barrier height so as to prevent electric conduction when the gate voltage is not applied. This condition is shown by the following equation.

[0025]

[Equation 1]

However, Tepi is the size of the depletion layer spreading in the n ^- type layer. The first term on the right-hand side shown in Equation 2 is the extension amount of the depletion layer due to the built-in voltage Vbuilt of the PN junction between the thin film semiconductor layer 8 and the p-type epitaxial layer 3, that is, the depletion spreading from the p-type epitaxial layer 3 to the thin-film semiconductor layer 8. The second term is the amount of extension of the depletion layer due to the charges of the gate insulating film 7 and φms, that is, the amount of extension of the depletion layer extending from the gate insulating film 7 to the thin film semiconductor layer 8. Therefore, if the sum of the extension amount of the depletion layer extending from the p-type epitaxial layer 3 and the extension amount of the depletion layer extending from the gate insulating film 7 is equal to or larger than the thickness of the thin film semiconductor layer 8, the vertical power MOSFET is normally off. Since it can be formed into a mold, the thin film semiconductor layer 8 is formed under ion implantation conditions that satisfy this condition.

Such a normally-off type vertical power M
Even if a voltage cannot be applied to the gate electrode of the OSFET due to a failure or the like, current can be prevented from flowing, and therefore, safety can be ensured as compared with the normally-on type. Further, as shown in FIG. 1, the p-type epitaxial layer 3 is in contact with the source electrode 10 and is in a grounded state. Therefore, the thin-film semiconductor layer 8 can be pinched off by utilizing the built-in voltage Vbuilt of the PN junction between the thin-film semiconductor layer 8 and the p-type epitaxial layer 3. For example, p-type epitaxial layer 3
Is not grounded and is in a floating state, it is not possible to extend the depletion layer from the p-type epitaxial layer 3 using the built-in voltage Vbuilt, so that the p-type epitaxial layer 3 contacts the source electrode 10. It can be said that this is an effective structure for pinching off the thin film semiconductor layer 8. By increasing the impurity concentration of the p-type epitaxial layer 3, the built-in voltage Vbuilt can be used more greatly.

Further, in this embodiment, the vertical power MOSFET is manufactured by using silicon carbide. However, if it is attempted to manufacture this by using silicon, impurity layers such as the p-type epitaxial layer 3 and the thin film semiconductor layer 8 are formed. Since it is difficult to control the diffusion amount of thermal diffusion when performing, it is difficult to manufacture a normally-off type MOSFET having the same configuration as described above. Therefore, by using SiC as in the present embodiment, the vertical power MOSFET can be manufactured with higher accuracy than in the case of using silicon.

A normally-off vertical power MOS
In order to make an FET, it is necessary to set the thickness of the thin film semiconductor layer 8 so as to satisfy the condition of the above-mentioned formula 1. However, when V is used when silicon is used, the thickness of the thin film semiconductor layer 8 is thin. Therefore, it can be said that it is very difficult to manufacture in consideration of the fact that it is necessary to form it with a low impurity concentration and control the diffusion amount of impurity ions. However, when SiC is used, Vbuilt is about three times as high as that of silicon, and since it can be formed by increasing the thickness of the n ⁻ type layer or by increasing the impurity concentration, a normally-off type storage MOSFET can be manufactured. It can be said that it is easy.

For reference, FIG. 6 shows the relationship between the energy of ion implantation and the thickness of the thin film semiconductor layer 8. As shown in this figure, the thickness of the thin film semiconductor layer 8 can be changed by changing the energy of the ion implantation, and the thickness of the thin film semiconductor layer 8 can be changed in consideration of the relationship with the concentration of the thin film semiconductor layer 8. I am trying to set it. However,
Since FIG. 6 shows data obtained by directly performing ion implantation on the surface of silicon carbide on which no oxide film or the like is formed, FIG.
The ion implantation energy is selected in consideration of the film thickness of the oxide film 33 shown in (c).

[Step shown in FIG. 3C] Next, the oxide film is removed to expose the entire surface of the wafer including the groove 7. [Step shown in FIG. 4A] Then, a gate oxide film (gate insulating film) 9 is formed on the entire surface of the wafer including the side surface of the groove 7.

[Step shown in FIG. 4B] Further, the groove 7 is formed.
The inside of the gate oxide film 9 inside is filled with the gate electrode layer 10. As the constituent material of the gate electrode layer 10, p-type polysilicon or n-type polysilicon is used. [Step shown in FIG. 4C] Further, after forming the interlayer insulating film 11 made of LTO or the like on the upper surface of the gate electrode layer 10, the gate oxide film 9 and a predetermined region of the interlayer insulating film 11 are removed by etching, A contact hole for selectively exposing the surface layer portion of the n ⁺ type source region 5 and the p type epitaxial layer 3 is formed.

Thereafter, the source electrode layer 12 is formed of Ni or the like on the n ⁺ type source region 5 and the low resistance p type silicon carbide region 6 including the interlayer insulating film 11. Further, drain electrode layer 13 is formed on the back surface of n ⁺ type silicon carbide semiconductor substrate 1 to complete the trench gate type power MOSFET. Thus, the oxide film 33 (see FIG. 3C) is formed on the side surface 7 of the groove 7.
By performing ion implantation by utilizing the fact that it is thin on a, it is possible to form the thin film semiconductor layer 8 for forming the storage channel without relying on epitaxial growth.

Further, by forming the side surface 7a of the groove 7 into a tapered shape, the above-mentioned ion implantation can be performed from the direction normal to the semiconductor substrate 4, and the efficiency of ion implantation can be improved. Next, the operation (operation) of this vertical power MOSFET will be described. This MOSFET operates in a normally-off type accumulation mode, and when no voltage is applied to the gate electrode layer 10, carriers in the thin film semiconductor layer 8 are present between the p-type epitaxial layer 3 and the thin film semiconductor layer 8. Difference in electrostatic potential and thin film semiconductor layer 8
The entire area is depleted by the potential generated by the difference in work function between the gate electrode layer 10 and the gate electrode layer 10. By applying a voltage to the gate electrode layer 10, the potential difference caused by the sum of the work function difference between the thin film semiconductor layer 8 and the gate electrode layer 10 and the voltage applied from the outside is changed. This makes it possible to control the state of the channel.

That is, the work function of the gate electrode layer 10 is the first work function, the work function of the p-type epitaxial layer 3 is the second work function, and the work function of the thin film semiconductor layer 8 is the third work function. Then, by utilizing the difference between the first to third work functions, the first to third work functions and the impurity concentration of the thin film semiconductor layer 8 and the impurity concentration of the thin film semiconductor layer 8 are depleted so as to deplete the n-type carriers of the thin film semiconductor layer 8. The film thickness can be set.

In the off state, the depletion region is p
It is formed in the thin film semiconductor layer 8 by the electric field generated by the type epitaxial layer 3 and the gate electrode layer 10. When a positive bias is applied to the gate electrode layer 10 from this state, the n ⁺ -type source region 5 to the n ⁻ -type epitaxial layer 2 are formed at the interface between the gate insulating film (SiO ₂ ) 9 and the thin film semiconductor layer 8. A channel region extending in the direction is formed and switched to the ON state. At this time, electrons flow from the n ⁺ type source region 5 to the n ⁻ type epitaxial layer 2 through the thin film semiconductor layer 8.
When reaching the n ⁻ type epitaxial layer 2 (drift region), the electrons flow vertically to the n ⁺ type silicon carbide substrate 1 (n ⁺ drain).

By applying a positive voltage to the gate electrode layer 10 in this manner, a storage channel is induced in the thin film semiconductor layer 8 and carriers flow between the source electrode 10 and the drain electrode 11. (Second Embodiment) In the first embodiment, one embodiment of the present invention is applied to a storage channel type trench gate type power MOSFE.
Although the case of application to T has been described, MC-SIT (MOS Controlled S) as in the present embodiment.
static Induction Transisto
It can also be applied to r).

FIG. 7 shows the MC-SIT in this embodiment.
The schematic diagram of is shown. Since this MC-SIT has almost the same configuration as the MOSFET in the first embodiment, only different parts will be described, and similar parts will be denoted by the same reference numerals and description thereof will be omitted. As shown in FIG. 7, a gate electrode layer 41 electrically connected to the p-type epitaxial layer 3 is provided on the upper surface of the p-type epitaxial layer 3. The gate electrode layer 41 is electrically isolated from the source electrode layer 12 by the silicon oxide film 42 formed on the boundary between the p type epitaxial layer 3 and the n ⁺ type source region 5. The silicon oxide film 42 electrically separates the p-type epitaxial layer 3 from the source electrode layer 12.

In the MC-SIT thus constructed, the gate electrode layer 10 is used as the first gate and the gate electrode layer 41 is used as the third gate to control the voltage applied to these first and second gates. As a result, the width of the depletion region formed in the thin film semiconductor layer 8 is controlled, and a current flows between the source electrode layer 12 and the drain electrode layer 13.

Also in the MC-SIT configured as described above, an oxide film is formed on the entire upper surface of the semiconductor substrate 4 including the groove 7, and ion implantation is performed using this oxide film as a mask, so that a thin film semiconductor can be obtained without epitaxial growth. The layer 8 can be formed. (Third Embodiment) In the first embodiment, one embodiment of the present invention is the same as the storage channel type trench gate type power MOSFE.
Although the case of application to T has been described, the SIT (Static Induction Tr) is used as in the present embodiment.
It can also be applied to an anistor).

FIG. 8 shows a schematic diagram of the SIT in this embodiment. The SIT will be described below with reference to FIG.
It should be noted that only parts different from those of the trench gate type power MOSFET shown in FIG. 1 will be described, and similar parts will be denoted by similar reference numerals and description thereof will be omitted. The SIT is formed in the groove 7 so that the first gate electrode 50 made of polysilicon terminates at the interface between the n ⁺ type source region 5 and the sidewall channel film, and the upper surface of the p type base region 3 is formed. A second gate electrode layer 51 electrically connected to the first gate electrode layer 50 is formed therein. An equal voltage is applied to the first and second gate electrode layers 50 and 51.

An interlayer insulating film 52 made of LTO or the like is formed on the first gate electrode layer 50, and a source electrode layer 53 is further formed on the interlayer insulating film 52. The second gate electrode layer 51 is electrically separated from the source electrode layer 53 by the silicon oxide film 54 provided at the boundary between the n ⁺ type source region 5 and the p type base region 3.

The SIT thus constructed applies a voltage to the first and second gate electrode layers 50 and 51, and the work function difference between the first gate electrode layer 51 and the p-type epitaxial layer 3 is increased. By controlling the width of the depletion layer generated in the thin-film semiconductor layer 8 on the basis of the above, a current is made to flow from the source electrode layer 53 to the drain electrode layer 13. In addition,
At this time, the applied voltage to the first and second gate electrode layers 50 and 51 needs to be set so as not to exceed the Schottky voltage determined by the work function difference.

Also in the MC-SIT configured as described above, an oxide film is formed on the entire upper surface of the semiconductor substrate 4 including the groove 7, and ion implantation is performed using this oxide film as a mask to thereby form a thin film semiconductor without relying on epitaxial growth. The layer 8 can be formed. (Other Embodiments) In the above embodiment, when the thin film semiconductor layer 8 is formed, the side surface 7a of the groove 7 is tapered and the ion implantation is performed from the direction normal to the semiconductor substrate 4. The angle of the side surface 7a of the groove 7 and the angle of ion implantation are not limited to those in the above embodiment.

That is, the side surface 7a of the groove 7 may be perpendicular to the bottom surface 7b. Even in this case, the thin film semiconductor layer 8 can be formed by performing the ion implantation obliquely. Thus, the side surface 7a of the groove 7
The thin film semiconductor layer 8 can be formed by changing the angle, the ion implantation conditions, and the like.

[Brief description of drawings]

FIG. 1 is a vertical power MOS according to an embodiment of the present invention.
It is sectional drawing of FET.

FIG. 2 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG.

FIG. 3 is a diagram showing a manufacturing process of the vertical power MOSFET subsequent to FIG. 2;

FIG. 4 is a diagram showing a manufacturing process of the vertical power MOSFET subsequent to FIG. 3;

FIG. 5 is a diagram showing a relationship between an angle of a groove 7 and etching conditions.

FIG. 6 is a diagram showing a relationship between ion implantation energy conditions and ion implantation depth.

FIG. 7 is a sectional view for explaining an MC-SIT in the second embodiment.

FIG. 8 is a sectional view for explaining an SIT according to the third embodiment.

FIG. 9 is a sectional view showing a configuration of a conventional vertical power MOSFET.

[Explanation of symbols]

1 ... n ⁺ type semiconductor substrate, 2 ... n ⁻ type epitaxial layer,
3 ... p ^- type base layer, 5 ... n ⁺ type source region, 7 ... trench,
7a ... Side surface, 7b ... Bottom surface, 8 ... Thin film semiconductor layer, 9 ... Gate oxide film, 10 ... Gate electrode layer, 11 ... Interlayer insulating film, 1
2 ... Source electrode layer, 13 ... Drain electrode layer.

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-9-74191 (JP, A) JP-A 2-91976 (JP, A) JP-A 9-260653 (JP, A) JP-A 63- 98124 (JP, A) JP 58-184767 (JP, A) JP 9-172187 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 652 H01L 29/78 653

Claims (5)

(57) [Claims] 1. Switching of a current flowing between a source electrode layer (12) and a drain electrode layer (13) using a thin film semiconductor layer (8) formed on a side surface (7a) of a groove (7) as a channel region. In the method for manufacturing a silicon carbide semiconductor device, the method comprises: forming a first conductive type high resistance layer (2) having a higher resistance than the low resistance layer on the first conductive type low resistance layer (1); ,
A second conductivity type first semiconductor layer (3) is formed on the high resistance layer (2), and the first semiconductor layer (3) is formed.
A step of preparing a semiconductor substrate (4) having a side as a main surface, and a first conductive layer electrically connected to the source electrode layer (12) in a predetermined region of a surface layer portion of the first semiconductor layer (3). Forming a source region (5) of the mold; forming a groove (7) penetrating the source region (5) and the first semiconductor layer (3) from the main surface; and the groove (7). An oxide film (33) is formed on the main surface of the semiconductor substrate (4) including the oxide film, and ion implantation is performed using the oxide film (33) as a mask to form a first film on the side surface (7a) of the groove (7). A method of manufacturing a silicon carbide semiconductor device, comprising: a step of forming a conductive type thin film semiconductor layer (8); and a step of removing the oxide film (33). 2. A high resistance layer (1) of the first conductivity type having a higher resistance than the low resistance layer is formed on the low resistance layer (1) of the first conductivity type, and the high resistance layer (2) is formed. A step of preparing a semiconductor substrate (4) having a second conductivity type first semiconductor layer (3) formed thereon and having the first semiconductor layer (3) side as a main surface; Forming a source region (5) of the first conductivity type in a predetermined region of a surface layer portion of the semiconductor layer (3); and penetrating the source region (5) and the first semiconductor layer (3) from the main surface. Forming the groove (7), forming an oxide film (33) on the main surface of the semiconductor substrate (4) including the groove (7), and performing ion implantation using the oxide film (33) as a mask. And a step of forming a first conductivity type thin film semiconductor layer (8) on the side surface (7a) of the groove (7), and removing the oxide film (33). And a step of forming a gate insulating film (9) on the upper surface of the semiconductor layer (2) including the groove (7), and using the thin film semiconductor layer (8) as a channel region, at least on the channel region. Forming a gate electrode layer (10) via the gate insulating film (9), and the semiconductor substrate (4) including the gate electrode layer (10)
A step of forming an interlayer insulating film (11) thereon, and a step of forming a contact hole communicating with the base region (3) in a predetermined region of the interlayer insulating film (11) and the gate insulating film (9). And a step of forming a source electrode layer (12) on the interlayer insulating film (11) which is electrically connected to the base region (3) through the contact hole, and, among the semiconductor substrate (4), The method of manufacturing a silicon carbide semiconductor device according to claim 1, further comprising: forming a drain electrode layer (13) on a surface opposite to the main surface. 3. The silicon carbide semiconductor according to claim 1, wherein the step of forming the groove (7) is performed so that a side surface (7a) of the groove (7) has a tapered shape. Device manufacturing method. 4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the main surface is a (0001-) C plane. 5. A first gate on the thin film semiconductor layer (8).
Forming a gate electrode (50), An interlayer insulating film (52) is formed on the first gate electrode (50).
A source electrode connected to the source region (5) through
Forming (53) and contacting the first semiconductor layer (3)
And electrically connected to the first gate electrode (50)
A second gate electrode for forming
A method for manufacturing a silicon carbide semiconductor device according to claim 1.