JPH11266015A - Manufacture of silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the formation of a storage channel provided on a trench side, without depending on epitaxial growing process. SOLUTION: An oxide film 33 is formed on a main surface of an n<+> -type semiconductor substrate 4 including a trench 7 and then ion-implanted using this oxide film 33 as a mask to form a thin-film semiconductor layer 8 on a side 7a of the trench 7. When the oxide film 33 is formed on the main surface of the n<+> -type semiconductor substrate 4 including the trench 7, the oxide film 33 is formed thin on the side 7a of the trench 7 but thick in the other parts. As a result, if the main surface is ion-implanted using this oxide film 33 as the mask, a thin-film semiconductor layer 8 for forming a storage channel can be formed, without depending upon epitaxial growth process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a silicon carbide semiconductor device, and more particularly to an insulated gate field effect transistor, and more particularly to a vertical power MOSFET for high power.

[0002]

2. Description of the Related Art Conventionally, there is a storage channel type silicon carbide semiconductor device in which a thin film semiconductor layer (sidewall channel film) is formed on a side surface of a groove so that a storage channel can be formed by the thin film semiconductor layer. Japanese Patent Application Laid-Open No. 9-741 discloses an example of this storage channel type silicon carbide semiconductor device.
No. 91 discloses a trench gate type power MOSFET. This trench gate type power MOSFET will be described with reference to FIG.

A trench gate type power MOSFET has n ⁺
-Type single crystal silicon carbide (SiC) semiconductor substrate (hereinafter referred to as n ⁺
1) and n ⁻ -type epitaxial layer 2
And a semiconductor substrate 4 made of hexagonal single-crystal silicon carbide and constituted by a p-type epitaxial layer 3. The semiconductor device is formed with the upper surface (main surface) of the semiconductor substrate 4 as a substantially (0001-) carbon surface.

[0004] A predetermined area of the surface layer portion of the p-type epitaxial layer 3
In the area, n⁺Type source region 5 is formed, and n⁺Type
A trench (trench) 7 is formed at a predetermined position in the source region 5.
Have been. This groove 7 has n⁺Source region 5 and p-type epi
N penetrating through the axial layer 3 ^-Type epitaxial layer 2
And a side surface 7 substantially perpendicular to the surface of the p-type epitaxial layer 3
a and bottom surface 7b parallel to the surface of p-type epitaxial layer 3
have.

[0005] On the side surface 7a of the groove 7, a thin film made of n ^-- type silicon carbide formed on the surface of the n ⁺ -type source region 5, the p-type epitaxial layer 3, and the n ^-- type epitaxial layer 2 by the epitaxial growth method. A semiconductor layer 80 is provided. A gate insulating film (gate oxide film) 9 is formed inside the trench 7, and the gate oxide film 9 is filled with a gate electrode layer 10. An interlayer insulating film 11 is formed on the gate electrode layer 10. Are located. Further, the surface and the p-type epitaxial layer 3 on the surface of the interlayer insulating film 11 above the n ⁺ -type source region 5, including the source electrode layer 12 is formed, the source electrode layer 12 and the n ⁺ -type source region 5 Both are in contact with the p-type epitaxial layer 3. Drain electrode layer 13 is formed on the surface of n ⁺ -type silicon carbide semiconductor substrate 1 (the back surface of semiconductor substrate 4).

The trench gate type power M thus constructed
In the OSFET, the thin film semiconductor layer 80 is used as a channel formation region, and a voltage is applied to the gate electrode layer 10 to form the gate oxide film 9.
By applying an electric field, a storage channel is induced in the thin film semiconductor layer 80, and a current flows between the source electrode layer 12 and the drain electrode layer 13. By doing so, the impurity concentration of the p-type epitaxial layer 3 and the impurity concentration of the n-type thin film semiconductor layer 80 in which the channel is formed can be controlled independently, and the impurity concentration of the p-type epitaxial layer 3 can be increased. , N ⁺ type source region 5
And the p-type epitaxial layer 3 sandwiched between the n ⁻ -type epitaxial layers 2 is reduced in thickness to shorten the channel length, thereby making the trench gate type power MOSFET high withstand voltage and low on-resistance.

[0007]

In the above-mentioned conventional trench gate type power MOSFET, the thin film semiconductor layer 80 for forming the storage channel is formed by digging the trench 7 and then epitaxially growing it. For this reason, epitaxial growth for forming the thin film semiconductor layer 80 is required, and there is a problem that the manufacturing process becomes longer.

The present invention has been made in view of the above points, and has as its object to form a channel layer for forming a storage channel provided on the side surface of a trench without using epitaxial growth.

[0009]

In order to achieve the above object, the following technical means are employed. In the invention according to claims 1 to 4, the semiconductor substrate (4) including the groove (7)
An oxide film (33) is formed on the main surface of the trench, and ion implantation is performed using the oxide film (33) as a mask to form a groove (7).
Is characterized in that a thin film semiconductor layer (8) of the first conductivity type is formed on the side surface (7a).

Thus, when the oxide film (33) is formed on the main surface of the semiconductor substrate (4) including the groove (7), the oxide film (33) is thin on the side surface (7a) of the groove (7), Other portions are formed thicker. Therefore, this oxide film (3
By performing ion implantation using 3) as a mask, the thin film semiconductor layer (8) for forming a storage channel can be formed without using epitaxial growth.

According to a third aspect of the present invention, the side surface (7a) of the groove (7) is tapered. If the groove (7) is tapered, ion implantation for forming the thin film semiconductor layer (8) can be performed from the normal direction of the surface of the semiconductor substrate (4). Simplification can be achieved.

By controlling the thickness of the thin film semiconductor layer (8) in this manner, the characteristics of the semiconductor device can be made normally-off. According to the invention described in claim 4, the thickness of the oxide film on the bottom surface of the groove can be made larger than the thickness of the side surface. Thus, the thin film semiconductor layer for forming the storage channel can be reliably formed only on the side surface by ion implantation.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 1 shows a normally-off n-channel type trench gate type power MOS according to the present embodiment.
1 shows a cross-sectional view of an FET (hereinafter, referred to as a vertical power MOSFET). This device is suitable for application to a rectifier of an inverter or a vehicle alternator.

The structure of a vertical power MOSFET will be described with reference to FIG. However, the vertical power MOSFET according to the present embodiment is the same as the MOSFET shown in FIG.
Since it has a structure similar to that of T, only different parts will be described. Note that, in the vertical power MOSFET of the present embodiment, the same portions as those of the MOSFET shown in FIG. 9 are denoted by the same reference numerals.

In the MOSFET shown in FIG. 9, the thin-film semiconductor layer 80 for forming the storage channel is formed by epitaxial growth.
Is formed by ion implantation. The manufacturing process of the vertical power MOSFET shown in FIG. 1 will be described with reference to FIGS.

[Step shown in FIG. 2 (a)] First, n ^{+ of} about 400 μm whose main surface is a (0001-) carbon surface
A silicon carbide substrate 1 is prepared, an n ⁻ -type epitaxial layer 2 of about 10 μm is grown on the surface thereof, and a p-type epitaxial layer 3 of about 2.5 μm is grown on the n ⁻ -type epitaxial layer 2. Thus, semiconductor substrate 4 including n ⁺ -type silicon carbide substrate 1, n ⁻ -type epitaxial layer 2 and p-type epitaxial layer 3 is formed. In addition,
The crystal axis of n ⁺ -type silicon carbide substrate 1 is tilted by 3.5 ° to 8 ° so that n ⁻ -type epitaxial layer 2 and p-type epitaxial layer 3
Is formed, the plane orientation of the main surface of the semiconductor substrate 4 is substantially a (0001-) carbon plane.

[Step shown in FIG. 2B] Next, an n-type impurity (for example, nitrogen) is ion-implanted into a predetermined region of the surface layer of the p-type epitaxial layer 3 to form an n ⁺ -type source region 5. . [Step shown in FIG. 2C] A silicon nitride film (Si ₃ N) is formed on the p-type epitaxial layer 3 including the n ⁺ -type source region.
₄ film) 31 and then a silicon nitride film 31
An LTO film 32 is formed thereon. Then, the silicon oxide film 31 and the LTO film 32 in the region where the groove is to be formed are removed by photoetching. At this time,
In the etching, the groove 7 to be formed later is [112-0].
The mask is aligned so as to be substantially parallel to the direction. In this [112-0] direction, since the interface state density is the minimum,
The withstand voltage can be improved based on the reduction of the interface state density. Since the groove 7 is formed under such conditions, the groove 7
When viewed from above, the planar shape of the side surface 7a of the groove 7 is a hexagon having the same interior angle.

If the groove 7 is not parallel to the [112-0] direction but is substantially parallel to the [11-00] direction,
The carbon atom density can be reduced, and by selecting this direction, the interface state density due to the carbon atoms can be reduced. Then, using RIE as a dry etching method, the n ⁺ type source region 5 is formed.
And a groove 7 penetrating both the p-type epitaxial layer 3 and reaching the n ⁻ -type epitaxial layer 2 is formed. At this time, R
By controlling the component (ratio) of the IE gas and the etching time, the side surface 7a of the groove 7 forms a predetermined angle with respect to the bottom surface 7b (the surface direction of the semiconductor substrate 4).
In the present embodiment, the side surface 7a of the groove 7 is one to the bottom surface 7b.
The angle is set to 05 °, that is, the side surface 7a of the groove 7 is formed in a tapered shape.

As an example, SF ₆ + O _{2 is} used as an etching solution.
When the ratio of O ₂ is changed, the groove 7
FIG. 5 shows how the inclination of the side surface 7a changes. In addition, the angle of the side surface 7a of the groove 7 shown in FIG.
The angle formed with respect to the normal direction of the semiconductor substrate 4 is shown, and the angle formed by the side surface 7a of the groove 7 with respect to the bottom surface 7b is 90 degrees.
It corresponds to α when expressed as + α °. Based on this figure,
In the present embodiment, the side surface 7a of the groove 7 is one to the bottom surface 7b.
The O ₂ ratio is set to about 50% so as to be 05 °.

[Step shown in FIG. 3A]
An oxide film 33 is formed on the entire upper surface of the wafer including the inside of the groove 7. At this time, the oxide film 33 is formed thin on the side surface 7a of the groove 7 and thick on other portions. Oxide film 33
Although the specific film thickness varies depending on the heat treatment conditions, for example, when heat treatment is performed at 1080 ° C. for 6 hours in a wet oxidizing atmosphere, the film thickness is about 60 nm on the side surface 7a of the groove 7 and on other portions. It is about 300 nm.

[Step shown in FIG. 3B] Using the oxide film 33 as a mask, an n-type impurity is ion-implanted from the normal direction of the semiconductor substrate 4 (above the paper surface). Thus, the n-type impurity ions are implanted into the side surface of the groove 7 through the portion of the oxide film 33 on the side surface 7a of the groove 7 where the film thickness is reduced, and the thin film semiconductor layer 8 is formed.

At this time, as described above, the side surface 7a of the groove 7
Is tapered and the (0001-) C plane is used as a main surface, so that a thin oxide film can be selectively formed on the side surface 7a due to anisotropy of oxidation, and ion implantation from the normal direction of the semiconductor substrate 4 can be performed. As a result, the thin film semiconductor layer 8 can be formed, so that the direction of ion implantation can be easily set.

The conditions of the ion implantation at this time differ depending on the thickness of the oxide film 33.
It is necessary to set the energy so that n-type impurity ions do not pass through portions other than the side surface 7a of the groove 7 and the thin film semiconductor layer 8 formed on the side surface 7a of the groove 7 has a desired thickness. For example, in the present embodiment, the thickness of the thin film semiconductor layer 8 is set to be 200 to 300 nm.

Here, the thickness of the thin film semiconductor layer 8 is determined based on the following equation in order to make the vertical power MOSFET a normally-off type. Vertical power MOSFET
Is required to have a sufficient barrier height so that the depletion layer extending to the n ⁻ -type layer prevents electric conduction when no gate voltage is applied. This condition is expressed by the following equation.

[0025]

(Equation 1)

Here, Tepi is the size of the depletion layer extending to the n ⁻ -type layer. The first term on the right-hand side of the equation (2) is the extension of the depletion layer due to the built-in voltage Vbuilt of the PN junction between the thin film semiconductor layer 8 and the p-type epitaxial layer 3, that is, the depletion spreading from the p-type epitaxial layer 3 to the thin film semiconductor layer 8. The second term is the extension amount of the depletion layer due to the charge of the gate insulating film 7 and φms, that is, the extension amount of the depletion layer extending from the gate insulating film 7 to the thin film semiconductor layer 8. Therefore, if the sum of the extension amount of the depletion layer extending from the p-type epitaxial layer 3 and the extension amount of the depletion layer extending from the gate insulating film 7 is equal to or more than the thickness of the thin film semiconductor layer 8, the vertical power MOSFET can be normally off. The thin film semiconductor layer 8 is formed under ion implantation conditions satisfying this condition because it can be formed into a mold.

Such a normally-off type vertical power M
The OSFET can prevent a current from flowing even when a voltage cannot be applied to the gate electrode due to a failure or the like, so that safety can be ensured as compared with a normally-on type. Further, as shown in FIG. 1, the p-type epitaxial layer 3 is in contact with the source electrode 10 and is in a ground state. Therefore, the thin film semiconductor layer 8 can be pinched off by using the built-in voltage Vbuilt of the PN junction between the thin film semiconductor layer 8 and the p-type epitaxial layer 3. For example, the p-type epitaxial layer 3
Is not grounded and is in a floating state, the built-in voltage Vbuilt cannot be used to extend the depletion layer from the p-type epitaxial layer 3, so that the p-type epitaxial layer 3 is in contact with the source electrode 10. This can be said to be an effective structure for pinching off the thin film semiconductor layer 8. By increasing the impurity concentration of the p-type epitaxial layer 3, the built-in voltage Vbuilt can be further increased.

In this embodiment, the vertical power MOSFET is manufactured by using silicon carbide. However, when manufacturing the vertical power MOSFET by using silicon, impurity layers such as the p-type epitaxial layer 3 and the thin film semiconductor layer 8 are formed. Since it is difficult to control the amount of thermal diffusion at the time of performing, it becomes difficult to manufacture a normally-off type MOSFET similar to the above configuration. Therefore, by using SiC as in the present embodiment, a vertical power MOSFET can be manufactured with higher accuracy than when silicon is used.

Also, a normally-off type vertical power MOS
In order to make an FET, it is necessary to set the thickness of the thin film semiconductor layer 8 so as to satisfy the condition of the above formula 1. However, when silicon is used, since the Vbuilt is low, the thickness of the thin film semiconductor layer 8 is reduced. Considering that it is difficult to control the amount of diffusion of impurity ions, it can be said that manufacturing is extremely difficult. However, when SiC is used, Vbuilt is about three times as high as that of silicon and can be formed by increasing the thickness of the n ⁻ -type layer or increasing the impurity concentration. Therefore, it is possible to manufacture a normally-off type storage MOSFET. It can be said that it is easy.

FIG. 6 shows the relationship between the energy of ion implantation and the thickness of the thin film semiconductor layer 8 for reference. As shown in this figure, the thickness of the thin film semiconductor layer 8 can be changed by changing the energy of the ion implantation, and the thickness of the thin film semiconductor layer 8 is reduced in consideration of the relationship with the concentration of the thin film semiconductor layer 8. I am trying to set it. However,
FIG. 6 shows data when ions are directly implanted into the silicon carbide surface on which no oxide film or the like is formed.
The ion implantation energy is selected in consideration of the thickness of the oxide film 33 shown in FIG.

[Step shown in FIG. 3C] Next, the oxide film is removed to expose the entire surface of the wafer including the groove 7. [Step shown in FIG. 4A] Then, a gate oxide film (gate insulating film) 9 is formed on the entire surface of the wafer including the side surfaces of the groove 7.

[Step shown in FIG. 4 (b)]
The inside of the gate oxide film 9 is filled with the gate electrode layer 10. As a constituent material of the gate electrode layer 10, p-type polysilicon or n-type polysilicon is used. [Step shown in FIG. 4C] Further, after an interlayer insulating film 11 made of LTO or the like is formed on the upper surface of the gate electrode layer 10, a predetermined region of the interlayer insulating film 11 together with the gate oxide film 9 is removed by etching. A contact hole for selectively exposing the surface portion of the n ⁺ type source region 5 and the p type epitaxial layer 3 is formed.

Thereafter, a source electrode layer 12 made of Ni or the like is formed on the n ⁺ -type source region 5 including on the interlayer insulating film 11 and the low-resistance p-type silicon carbide region 6. Further, a drain electrode layer 13 is formed on the back surface of n ⁺ type silicon carbide semiconductor substrate 1 to complete a trench gate type power MOSFET. As described above, the oxide film 33 (see FIG. 3C)
By performing ion implantation by utilizing the fact that the layer is thin on a, it becomes possible to form the thin film semiconductor layer 8 for forming a storage channel without using epitaxial growth.

Further, by making the side face 7a of the groove 7 tapered, the above-described ion implantation can be performed from the normal direction of the semiconductor substrate 4, and the efficiency of ion implantation can be improved. Next, the operation (operation) of this vertical power MOSFET will be described. This MOSFET operates in a normally-off type accumulation mode. When no voltage is applied to the gate electrode layer 10, carriers in the thin film semiconductor layer 8 are generated between the p-type epitaxial layer 3 and the thin film semiconductor layer 8. Difference in electrostatic potential and thin film semiconductor layer 8
The entire region is depleted by a potential caused by a difference in work function between the gate electrode layer 10 and the gate electrode layer 10. By applying a voltage to the gate electrode layer 10, a potential difference caused by the sum of a work function difference between the thin film semiconductor layer 8 and the gate electrode layer 10 and an externally applied voltage is changed. As a result, the state of the channel can be controlled.

That is, the work function of the gate electrode layer 10 is defined as a first work function, the work function of the p-type epitaxial layer 3 is defined as a second work function, and the work function of the thin film semiconductor layer 8 is defined as a third work function. Then, utilizing the difference between the first to third work functions, the first to third work functions and the impurity concentration of the thin film semiconductor layer 8 and the impurity concentration of the thin film semiconductor layer 8 are reduced so as to deplete the n-type carriers of the thin film semiconductor layer 8. The film thickness can be set.

In the off state, the depletion region is p
It is formed in the thin film semiconductor layer 8 by an electric field created by the type epitaxial layer 3 and the gate electrode layer 10. When a positive bias is supplied to the gate electrode layer 10 from this state, the n ⁺ -type source region 5 to the n ⁻ -type epitaxial layer 2 are removed from the interface between the gate insulating film (SiO ₂ ) 9 and the thin-film semiconductor layer 8. A channel region extending in the direction is formed and is switched on. At this time, electrons flow from the n ⁺ -type source region 5 through the thin-film semiconductor layer 8 to the n ⁻ -type epitaxial layer 2 from the thin-film semiconductor layer 8.
Then, when reaching the n ⁻ type epitaxial layer 2 (drift region), the electrons flow vertically to the n ⁺ type silicon carbide substrate 1 (n ⁺ drain).

By applying a positive voltage to the gate electrode layer 10 as described above, a storage channel is induced in the thin film semiconductor layer 8, and carriers flow between the source electrode 10 and the drain electrode 11. (Second Embodiment) In the first embodiment, an embodiment of the present invention is described by using a storage channel type trench gate type power MOSFET.
T has been described above, but as in the present embodiment, MC-SIT (MOS Controlled S)
static InductionTransisto
r) can also be applied.

FIG. 7 shows the MC-SIT in this embodiment.
FIG. Since the MC-SIT has substantially the same configuration as the MOSFET in the first embodiment, only different portions will be described, and the same portions will be denoted by the same reference numerals and description thereof will be omitted. As shown in FIG. 7, on the upper surface of the p-type epitaxial layer 3, a gate electrode layer 41 electrically connected to the p-type epitaxial layer 3 is provided. This gate electrode layer 41 is electrically separated from source electrode layer 12 by a silicon oxide film 42 formed on the boundary between p-type epitaxial layer 3 and n ⁺ -type source region 5. The p-type epitaxial layer 3 is electrically separated from the source electrode layer 12 by the silicon oxide film 42.

In the MC-SIT thus configured, the gate electrode layer 10 is used as a first gate, and the gate electrode layer 41 is used as a third gate to control voltages applied to the first and second gates. Thereby, the width of the depletion region formed in the thin film semiconductor layer 8 is controlled, and a current flows between the source electrode layer 12 and the drain electrode layer 13.

Also in the MC-SIT having such a structure, an oxide film is formed on the entire upper surface of the semiconductor substrate 4 including the groove 7, and ion implantation is performed using the oxide film as a mask. Layer 8 can be formed. (Third Embodiment) In the first embodiment, an embodiment of the present invention is described by using a storage channel type trench gate type power MOSFET.
T has been described, but as in the present embodiment, the SIT (Static Induction Tr
anstor).

FIG. 8 is a schematic diagram of the SIT according to the present embodiment. Hereinafter, the SIT will be described with reference to FIG.
Only the portions different from the trench gate type power MOSFET shown in FIG. 1 will be described, and the same portions will be denoted by the same reference numerals and description thereof will be omitted. The SIT is formed such that a first gate electrode 50 made of polysilicon is terminated inside the trench 7 at the interface between the n ⁺ -type source region 5 and the sidewall channel film, and the upper surface of the p-type base region 3 is formed. A second gate electrode layer 51 electrically connected to the first gate electrode layer 50 is formed. An equal voltage is applied to the first and second gate electrode layers 50 and 51.

An interlayer insulating film 52 made of LTO or the like is formed on the first gate electrode layer 50, and a source electrode layer 53 is formed on the interlayer insulating film 52. The second gate electrode layer 51 is electrically separated from the source electrode layer 53 by a silicon oxide film 54 provided at the boundary between the n ⁺ type source region 5 and the p type base region 3.

The SIT configured as described above applies a voltage to the first and second gate electrode layers 50 and 51 and generates a work function difference between the first gate electrode layer 51 and the p-type epitaxial layer 3. By controlling the width of the depletion layer generated in the thin film semiconductor layer 8 based on the above, current flows from the source electrode layer 53 to the drain electrode layer 13. In addition,
At this time, the voltage applied to the first and second gate electrode layers 50 and 51 needs to be set so as not to exceed the Schottky voltage determined by the work function difference.

Also in the MC-SIT having such a structure, an oxide film is formed on the entire upper surface of the semiconductor substrate 4 including the groove 7, and ion implantation is performed using the oxide film as a mask. Layer 8 can be formed. (Other Embodiments) In the above embodiment, when the thin film semiconductor layer 8 is formed, the side surface 7a of the groove 7 is tapered and ion implantation is performed from the normal direction of the semiconductor substrate 4. The angle of the side surface 7a of the groove 7 and the angle of the ion implantation are not limited to the above embodiment.

That is, the side surface 7a of the groove 7 may be perpendicular to the bottom surface 7b. Also in this case, the thin film semiconductor layer 8 can be formed by performing ion implantation obliquely. Thus, the side surface 7a of the groove 7
The thin film semiconductor layer 8 can be formed even if the angle of ion implantation, ion implantation conditions, and the like are changed.

[Brief description of the drawings]

FIG. 1 is a vertical power MOS according to an embodiment of the present invention.
It is sectional drawing of FET.

FIG. 2 is a diagram showing a manufacturing process of the vertical power MOSFET shown in FIG.

FIG. 3 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 2;

FIG. 4 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 3;

FIG. 5 is a diagram showing a relationship between an angle of a groove 7 and an etching condition.

FIG. 6 is a diagram showing a relationship between an ion implantation energy condition and an ion implantation depth.

FIG. 7 is a cross-sectional view illustrating an MC-SIT according to a second embodiment.

FIG. 8 is a cross-sectional view illustrating an SIT according to a third embodiment.

FIG. 9 is a cross-sectional view showing a configuration of a conventional vertical power MOSFET.

[Explanation of symbols]

1 ... n ⁺ type semiconductor substrate, 2 ... n ^- type epitaxial layer,
3 ... p ^- type base layer, 5 ... n ⁺ type source region, 7 ... groove,
7a: side surface, 7b: bottom surface, 8: thin film semiconductor layer, 9: gate oxide film, 10: gate electrode layer, 11: interlayer insulating film, 1
2 ... source electrode layer, 13 ... drain electrode layer.

Claims (4)

[Claims] 1. Switching of a current flowing between a source electrode layer (12) and a drain electrode layer (13) using a thin film semiconductor layer (8) formed on a side surface (7a) of a groove (7) as a channel region. The method of manufacturing a silicon carbide semiconductor device according to claim 1, further comprising: forming a first conductive type high resistance layer (2) having a higher resistance than the low resistance layer on the first conductive type low resistance layer (1); ,
A second conductive type first semiconductor layer (3) is formed on the high resistance layer (2), and the first semiconductor layer (3) is formed.
Preparing a semiconductor substrate (4) having a side as a main surface; and a first conductive layer electrically connected to the source electrode layer (12) in a predetermined region of a surface portion of the first semiconductor layer (3). Forming a mold source region (5); forming a groove (7) penetrating the source region (5) and the first semiconductor layer (3) from the main surface; and forming the groove (7). An oxide film (33) is formed on the main surface of the semiconductor substrate (4), and ion implantation is performed using the oxide film (33) as a mask, and a first surface is formed on the side surface (7a) of the groove (7). A method for manufacturing a silicon carbide semiconductor device, comprising: a step of forming a conductive thin film semiconductor layer (8); and a step of removing the oxide film (33). 2. A high-resistance layer of the first conductivity type having a higher resistance than the low-resistance layer is formed on the low-resistance layer of the first conductivity type. A step of preparing a semiconductor substrate (4) having a second conductive type first semiconductor layer (3) formed thereon and having the first semiconductor layer (3) side as a main surface; Forming a first conductivity type source region (5) in a predetermined region of a surface layer portion of the semiconductor layer (3); and penetrating the source region (5) and the first semiconductor layer (3) from the main surface. Forming a groove (7), forming an oxide film (33) on the main surface of the semiconductor substrate (4) including the groove (7), and performing ion implantation using the oxide film (33) as a mask. Forming a first conductivity type thin film semiconductor layer (8) on the side surface (7a) of the groove (7); and removing the oxide film (33). Forming a gate insulating film (9) on the upper surface of the semiconductor layer (2) including the groove (7); and using the thin film semiconductor layer (8) as a channel region at least on the channel region. Forming a gate electrode layer (10) via the gate insulating film (9); and the semiconductor substrate (4) including the gate electrode layer (10).
Forming an interlayer insulating film (11) thereon; and forming a contact hole communicating with the base region (3) in a predetermined region of the interlayer insulating film (11) and the gate insulating film (9). Forming a source electrode layer (12) electrically connected to the base region (3) via the contact hole on the interlayer insulating film (11); Forming a drain electrode layer (13) on a surface opposite to the main surface. The method of manufacturing a silicon carbide semiconductor device according to claim 1, further comprising: 3. The silicon carbide semiconductor according to claim 1, wherein the step of forming the groove (7) is performed so that a side surface (7a) of the groove (7) has a tapered shape. Device manufacturing method. 4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein said main surface is a (0001-) C plane.