JPH11266017A - Silicon carbide semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize further reduction of the on-resistance of a MOSFET in a storage mode. SOLUTION: The impurity concentration in a part 5b, which is arranged in the surface part of a first conductivity-type semiconductor layer 2, of a surface channel layer 5 is set so as to become higher than that of the layer 2. The on-resistance of a MOSFET is decided by the contact resistance between a source electrode 10 and source regions 4a and 4b, the internal resistances of the source regions 4a and 4b, a storage channel resistance in a channel region formed in the layer 5, an internal resistance in the layer 5, a JFET resistance in a JFET part, an internal resistance in the layer 2, the internal resistance of a semiconductor substrate 1 and the contact resistance between the substrate 1 and a drain electrode 11, and the sum total of these resistances becomes the on-resistance of the MOSFET. Accordingly, the internal resistance in the layer 5 is reduced, whereby the on-resistance of the MOSFET is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate field effect transistor, particularly a vertical power MOSF for high power.
It is about ET.

[0002]

2. Description of the Related Art The applicant of the present invention has filed an application for a planar MOSFET in which the channel mobility is improved to reduce the on-resistance in Japanese Patent Application No. 9-259076. FIG. 12 is a cross-sectional view of the planar MOSFET, and the structure of the planar MOSFET will be described with reference to FIG.

An n ⁺ -type silicon carbide semiconductor substrate 1 has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. Main surface 1a of n ⁺ type silicon carbide semiconductor substrate 1
Above, n ⁻ having a lower dopant concentration than substrate 1
-Type silicon carbide epitaxial layer (hereinafter referred to as n ^- type silicon carbide epi layer) 2 is stacked. In this case, n ⁺ -type silicon carbide semiconductor substrate 1 and the n ^- but the upper surface of type silicon carbide epitaxial layer 2 is set to (0001) Si plane, n ⁺ -type silicon carbide semiconductor substrate 1 and the n ^- -type silicon carbide epitaxial layer 2 The upper surface may be the (112-0) a surface. That is, (000
1) A low surface state density can be obtained by using the Si surface, and (1)
When the 12-0) a plane is used, a crystal having a low surface state density and completely having no screw dislocation can be obtained.

[0004] n^-In the surface layer of silicon carbide epilayer 2
In a predetermined area, p having a predetermined depth ^-Type silicon carbide base
Regions 3a and p^-Type silicon carbide base region 3b is separated
It is formed. Also, p^--Type silicon carbide base region 3
a in a predetermined region in the surface layer portion of the base region 3a
Also shallow n⁺The type source region 4a also has p^-Type silicon carbide
A predetermined area in the surface portion of the base area 3b includes a base
N shallower than region 3b ⁺Each of the mold source regions 4b
Has been established.

Further, the surface of n ⁻ -type silicon carbide epilayer 2 and p ⁻ -type silicon carbide base regions 3a and 3b between n ⁺ -type source region 4a and n ⁺ -type source region 4b have n ⁻ -type SiC Layer 5 extends. That is, n ⁻ -type SiC layer 5 is arranged so as to connect source regions 4a, 4b and n ⁻ -type silicon carbide epilayer 2 at the surface portions of p ⁻ -type silicon carbide base regions 3a, 3b. This n ^- type SiC
The layer 5 is formed by epitaxial growth, and uses an epitaxial film having 4H, 6H, and 3C crystals. The epitaxial layer can form various crystals regardless of the underlying substrate. When the device operates, it functions as a channel forming layer on the device surface. Hereinafter, n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

The dopant concentration of the surface channel layer 5 is 1
The concentration is as low as about × 10 ¹⁵ cm ⁻³ to about 1 × 10 ¹⁷ cm ⁻³ , and is lower than the dopant concentration of n ⁻ -type silicon carbide epilayer 2 and p ⁻ -type silicon carbide base regions 3a and 3b. ing. Thereby, low on-resistance is achieved. In addition, concave portions 6a and 6b are formed in the surface portions of p ⁻ -type silicon carbide base regions 3a and 3b and n ⁺ -type source regions 4a and 4b.

A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ type source regions 4a and 4b. Further, a polysilicon gate electrode 8 is formed on the gate insulating film 7. The polysilicon gate electrode 8 is covered with an insulating film 9.
As the insulating film 9, LTO (Low Temperature) is used.
e Oxide) film is used. A source electrode 10 is formed thereon, and the source electrode 10 has n ⁺ -type source regions 4a and 4b and p ⁻ -type silicon carbide base region 3a,
3b. Further, n ⁺ type silicon carbide semiconductor substrate 1
A drain electrode layer 11 is formed on the back surface 1b of the substrate.

Note that, of the n ^- type silicon carbide epilayer 2, p
^The portion sandwiched between-type silicon carbide base regions 3a and 3b constitutes a so-called J-FET portion. Next, the operation (operation) of the power planar type MOSFET will be described. M above
OSFETs operate in a storage mode. Surface channel layer 5
, The carrier is a p ⁻ -type silicon carbide base region 3a,
3b and the difference in electrostatic potential between the surface channel layer 5 and the surface channel layer 5 and the polysilicon gate electrode 8
Depleted by the potential created by the work function difference between Therefore, by adjusting the voltage applied to the polysilicon gate electrode 8, the work function difference between the surface channel layer 5 and the polysilicon gate electrode 8 and the potential difference caused by an externally applied voltage are changed. On / off of the MOSFET is controlled by controlling the state of the channel.

More specifically, in the off state, the depletion region is formed in surface channel layer 5 by the electric field created by p ⁻ -type silicon carbide base regions 3 a and 3 b and polysilicon gate electrode 8. By supplying a positive bias to the polysilicon gate electrode 8, the n ⁺ -type source regions 4a, 4b to n at the interface between the gate insulating film (SiO ₂ ) 7 and the surface channel layer 5
^- a channel region formed extending in a type drift region 2 direction to switch to the ON state.

At this time, electrons are supplied to the n ⁺ type source region 4.
a and 4b flow through the surface channel layer 5 and flow from the surface channel layer 5 to the n ⁻ -type silicon carbide epilayer 2 including the JFET portion. Then, n ⁻ -type silicon carbide epilayer (drift region) 2
, Electrons are transferred to the n ⁺ type silicon carbide semiconductor substrate (n ⁺
Drain) 1 flows vertically. Thus, the gate electrode 8
, A storage channel is induced in the surface channel layer 5, and a current flows between the source electrode 10 and the drain electrode 11.

As described above, in the planar type MOSFET, the operation mode is set to the accumulation mode in which the channel is induced without inverting the conductivity type of the channel forming layer. The on-resistance is reduced by increasing the mobility.

[0012]

As described above, the on-resistance can be reduced by using the storage mode MOSFET. However, further reduction in on-resistance is desired. The present invention has been made in view of the above points, and has as its object to further reduce the on-resistance in a MOSFET in an accumulation mode.

[0013]

In order to achieve the above object, the following technical means are employed. In the first to fourth aspects of the present invention, a portion (5b) of the surface channel layer (5) disposed on the surface of the first conductivity type semiconductor layer (2) is the semiconductor layer (2). It is characterized in that the impurity concentration is higher than that of the first embodiment.

The on-resistance of the MOSFET includes the contact resistance between the source electrode (10) and the source region (4a, 4b), the internal resistance of the source region (4a, 4b), and the channel region formed on the surface channel layer (5). , The internal resistance in the surface channel layer (5), J
It is determined by the JFET resistance in the FET portion, the internal resistance in the semiconductor layer (2), the internal resistance of the semiconductor substrate (1), and the contact resistance between the semiconductor substrate (1) and the drain electrode (11). Becomes

Therefore, by making the impurity concentration of the portion (5b) of the surface channel layer (5) disposed on the surface of the semiconductor layer (2) higher than that of the semiconductor layer (2),
Since the resistance of the surface channel layer (5) other than the channel region can be reduced, the on-resistance of the MOSFET can be reduced. Thereby, MOSFET
In this case, the on-resistance can be further reduced.

According to the second aspect of the present invention, when the potential of the gate electrode (8) is substantially zero, the surface channel layer (5) comprises a depletion layer extending from the gate insulating film (7) and a base region (5). It is characterized by being pinched off by a depletion layer extending from 3a, 3b). That is, it is characterized by being a normally-off type. As described above, by using the normally-off type, even when a voltage cannot be applied to the gate electrode (10) due to a failure or the like, current can be prevented from flowing. Safety can be ensured in comparison.

According to the third aspect of the present invention, in the semiconductor layer (2), the J-FET portion located on the side surface of the base region (3a, 3b) has a junction depth greater than the surface channel region (5). A low resistance region (30) of the first conductivity type having a larger depth is formed, and in the invention according to claim 4, the junction depth is smaller than that of the base region (3a, 3b). It is characterized in that a low resistance region (30) of the first conductivity type which is deepened is formed.

As described above, by forming the first conductive type low resistance region (30) having a junction depth deeper than the channel region (5) and the base regions (3a, 3b) in the J-FET portion. The current path can be sufficiently prevented from being narrowed by the depletion layer extending from the base region, and the resistance in the J-FET portion can be reduced.

If the low-resistance region (30) is separated from the surface channel layer (5), the gap between the low-resistance region (30) and the surface channel layer (5) may be increased. Since the high resistance first conductivity type semiconductor layer (2) remains, the electric field in the base regions (3a, 3b) can be reduced, and the withstand voltage can be improved. According to the invention described in claim 6, the impurity concentration in the portion (5b) of the surface channel layer (5) disposed on the surface of the semiconductor layer (2) is higher than the impurity concentration in the semiconductor layer (2). The process is characterized by having a step of performing.

As described above, the portion (5b) of the surface channel layer (5) disposed on the surface of the semiconductor layer (2)
The step of making the impurity concentration in the semiconductor layer (2) higher than the impurity concentration in the semiconductor layer (2) can manufacture the silicon carbide semiconductor device according to the first aspect. For example, by ion-implanting the surface layer of the semiconductor layer (2) and the surface layer of the base regions (3a, 3b) at the same time, the semiconductor layer ( The impurity concentration in the portion (5b) disposed on the surface portion of (2) can be higher than the impurity concentration in the semiconductor layer (2).

As described above, if the surface channel layer (5) is formed by ion implantation, and ion implantation is also performed on a portion (5b) of the surface channel layer (5) other than the channel region, the surface channel Simultaneously with the formation of the layer (5), the impurity concentration in the portion (5b) of the surface channel layer (5) arranged on the surface of the semiconductor layer (2) is made higher than the impurity concentration in the semiconductor layer (2). be able to. Thereby, the manufacturing process of the silicon carbide semiconductor device can be simplified.

According to the present invention, ions are implanted from the surface of the semiconductor layer (2) where the base regions (3a, 3b) are not formed, and the junction depth is higher than the surface channel region (5). The low-resistance region of the first conductivity type (30) is formed to be deeper, and in the invention according to the ninth aspect, the first junction is deeper than the base region (3a, 3b). It is characterized in that a conductive low resistance region (30) is formed.

Thus, the silicon carbide semiconductor device according to claim 3 or 4 can be manufactured. According to a tenth aspect, in the low resistance region (30) forming step, ion implantation is performed so that the low resistance region (30) is separated from the surface channel layer (5).
The silicon carbide semiconductor device according to claim 5 can be manufactured.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. (First Embodiment) FIG. 1 shows a normally-off type n-channel planar MOSFET according to this embodiment.
FIG. 1 shows a cross-sectional view of a (vertical power MOSFET). This device is preferably applied to a rectifier of an inverter or a vehicle alternator.

The structure of the vertical power MOSFET will be described with reference to FIG. However, the vertical power MOSFET in this embodiment is the same as the MOSF shown in FIG.
Since it has almost the same structure as ET, only different parts will be described. Note that, in the vertical power MOSFET of the present embodiment, the same portions as those of the MOSFET shown in FIG. 12 are denoted by the same reference numerals.

In the MOSFET shown in FIG. 12, the surface channel layer 5 is entirely formed of an n ⁻ -type layer. However, in the vertical power MOSFET of this embodiment, the surface channel layer 5 is formed.
Of these, the portion 5a to be a channel region is formed of an n ⁻ type layer, and the portion 5b other than the portion to be a channel region is formed of an n ⁺ type layer. That is, the surface channel layer 5 has p ⁻
Regions 4a and 4b at the surface portions of base type silicon carbide base regions 3a and 3b and at the surface portion of n ⁻ -type silicon carbide epilayer 2.
And n ⁻ -type silicon carbide epi layer 2. Of these, the surface portions of p ⁻ -type silicon carbide base regions 3 a and 3 b are n ⁻ -type layers, and n ⁻ -type silicon carbide epi layer 2 is formed. Is a n ⁺ -type layer.

The on-resistance Ron of the vertical power MOSFET depends on the source electrode 10 and the n ⁺ -type source region 4a.
4b, contact resistance Rs-cont, n ⁺ type source region 4
a, 4b internal resistance (drift resistance) Rsource, storage channel resistance Rchannel in the channel region formed in surface channel layer 5, internal resistance (accumulation drift resistance) Racc-drift in surface channel layer 5, J in J-FET section -FET resistance RJFET, n ⁺ type silicon carbide epilayer 2
Is determined by the internal resistance (drift resistance) Rdrift, n ⁺ -type internal resistance Rsub of the silicon carbide semiconductor substrate 1, and n ⁺ -type contact resistance Rd-cont the silicon carbide semiconductor substrate 1 and the drain electrode 11 in. That is, it is represented by the following equation.

[0028]

## EQU1 ## Ron = Rs-cont + Rsource + Rchannel + Rac
c-drift + RJFET + Rdrift + Rsub + Rd-cont Of these, the internal resistance (accumulation
Lift resistance) Racc-drift
A portion 5 of the surface channel layer 5 to be a channel region.
5b other than a⁺Because it is formed with a mold layer,
This part 5b is n ^-Lower than when formed with a mold layer
You. For this reason, the sum of the on-resistances Ron becomes small,
The resistance Ron can be reduced.

The vertical power MOSFET according to this embodiment shown in FIG. 1 and the surface channel layer 5 shown in FIG.
FIG. 2 shows a comparison between the drain currents of the portions other than the channel region and those of the n ^- type layer.
This figure shows a change in drain current when the gate applied voltage is changed. As shown in FIG. 2, when the portion 5b other than the channel region of the surface channel layer 5 is an n ⁺ -type layer, the portion 5b other than the channel region becomes n ⁻
It can be seen that the drain current is larger than in the case of the mold layer. This is a vertical power MOSFET
This is because the on-resistance Ron is reduced. As described above, by making the portion 5b of the surface channel layer 5 other than the channel region an n ⁺ -type layer, the on-resistance Ron of the vertical power MOSFET can be further reduced.

In the base regions 3a and 3b, deep base layers 30a and 30b having a partially increased thickness are formed. These deep base layers 30a, 30b
Is formed in a portion that does not overlap with n ⁺ -type source regions 4a and 4b, and a portion of p ⁻ -type silicon carbide base regions 3a and 3b where deep base layers 30a and 30b are formed has a larger thickness. The impurity concentration is higher than that of the thin portion where the deep base layer 30a is not formed.

Such a deep base layer 30a, 30
b, n ⁻ below the deep base layers 30a, 30b.
The thickness of the n-type silicon carbide epitaxial layer 2 is reduced (n ⁺ -type silicon carbide semiconductor substrate 1 and deep base layers 30a, 30b).
Distance becomes shorter) and the electric field strength can be increased,
Avalanche breakdown (hereinafter abbreviated as breakdown) is facilitated.

At this time, the deep base layers 30a, 30
b to n⁺Formed in a part that does not overlap the mold source region
Therefore, the following can be said. Breakdown is deep
Occurs at the base layers 30a, 30b, thereby
Breakdown current between pole 10 and drain electrode 11
Flows. At this time, the breakdown current (hole current)
The flowing paths are the source regions 4a, 4b and n^-Drift area
(N^-Sandwiched between epitaxial silicon carbide layers 2)^-Mold base area
In areas 3a and 3b, p^-In the mold base regions 3a, 3b
More voltage drop, p^-Mold base regions 3a, 3b and
The PN junction between the source regions 4a and 4b is forward-biased.
And n ^--Type silicon carbide epilayer 2 and base regions 3a and 3b
Parasitic NPN transistor composed of source regions 4a and 4b
The data will operate and a large current will flow. For this reason
The element is heated up and becomes unfavorable in terms of reliability.
sell. Therefore, the deep base layers 30a, 30b⁺
Because it is formed in a part that does not overlap the mold source region,
Can be avoided.

Next, the vertical power MOSFET shown in FIG.
Will be described with reference to FIGS. [Step shown in FIG. 3A] First, an n-type 4H or 6H or 3C-SiC substrate, that is, an n ⁺ -type silicon carbide semiconductor substrate 1 is prepared. Here, n ⁺ -type silicon carbide semiconductor substrate 1 has a thickness of 400 μm and main surface 1a has a thickness of (00).
01) Si plane or (112-0) a plane. An n ^-- type silicon carbide epilayer 2 having a thickness of 5 μm is epitaxially grown on main surface 1a of substrate 1. In this example, n ⁻ -type silicon carbide epilayer 2 has the same crystal as base substrate 1,
It becomes a mold 4H or 6H or 3C-SiC layer.

[Step shown in FIG. 3 (b)] An LTO film 20 is arranged in a predetermined region on the n ⁻ -type silicon carbide epilayer 2, and B ⁺ (or aluminum) is ion-implanted using the LTO film 20 as a mask. P ^- type silicon carbide base regions 3a and 3b are formed. The ion implantation conditions at this time are as follows:
And the dose amount is 1 × 10 ¹⁶ cm ⁻² .

[Step shown in FIG. 3C] After removing the LTO film 20, N ⁺ ions are implanted from the upper surface of the substrate 1 to
Surface channel layer 5 is formed on the surface of n ^- type silicon carbide epilayer 2 and on the surface (surface layer) of p ^- type silicon carbide base regions 3a and 3b. The ion implantation conditions at this time are a temperature of 700 ° C. and a dose of 1 × 10 ¹⁶ cm ⁻² . Thereby, the surface channel layer 5 becomes the p ⁻ type base region 3
The surface portions of a and 3b are compensated to form an n ⁻ -type layer having a low n ^- type impurity concentration, and the surface portion of the n ⁻ -type silicon carbide epilayer 2 is formed as an n ⁺ -type layer having a high n-type impurity concentration. Is done.

In order to make the vertical power MOSFET a normally-off type, the thickness (film thickness) of the surface channel layer 5 is set.
Is determined based on the following equation. Vertical power MO
In order for the SFET to be of the normally-off type, it is necessary that the depletion layer extending to the n ⁻ -type layer has a sufficient barrier height so as to prevent electric conduction when no gate voltage is applied. . This condition is expressed by the following equation.

[0037]

(Equation 2)

Where Tipi is n^-Of the depletion layer spreading over the mold layer
Height, φms is the work function difference between metal and semiconductor (electron energy
Qs is the space charge in the gate insulating film (oxide film) 7.
Load and Qfc are gate oxide films (SiO_Two) And n^-With mold layer
Interface (hereinafter referred to as SiO_Two/ SiC interface)
Charge, Qi is mobile ions in the oxide film, Qss is SiO _Two
/ SiC interface surface charge, Cox is a gate insulating film (oxidized
7 shows the capacity of the film 7).

The first term on the right-hand side of the equation (2) is the extension of the depletion layer due to the built-in voltage Vbuilt of the PN junction between the surface channel layer 5 and the p ^- type silicon carbide base regions 3a, 3b, that is, p ^- type silicon carbide. The extension amount of the depletion layer extending from the base regions 3a and 3b to the surface channel layer 5,
The term is the extension of the depletion layer due to the charge of the gate insulating film 7 and φms, that is, the extension of the depletion layer extending from the gate insulating film 7 to the surface channel layer 5. Therefore, if the sum of the extension amount of the depletion layer extending from p ^- type silicon carbide base regions 3a and 3b and the extension amount of the depletion layer extending from gate insulating film 7 is set to be equal to or greater than the thickness of surface channel layer 5, Type power MO
Since the SFET can be a normally-off type, the surface channel layer 5 is formed under ion implantation conditions that satisfy this condition.

Such a normally-off type vertical power M
In OSFET, voltage is impressed on the gate electrode due to failure or the like.
So that no current flows even if the
Compared to the normally-on type
Safety can be ensured. Also, as shown in FIG.
U, p^-Type silicon carbide base regions 3a and 3b
It is in contact with the electrode 10 and is in a ground state. others
The surface channel layer 5 and p ^--Type silicon carbide base region 3
Use built-in voltage Vbuilt of PN junction with a and 3b
Thus, the surface channel layer 5 can be pinched off.
For example, p^--Type silicon carbide base regions 3a and 3b are grounded.
If it is not floating and it is floating,
Using built-in voltage Vbuilt^-Type silicon carbide base
The depletion layer can be extended from the source regions 3a and 3b.
Because there is no^-Type silicon carbide base regions 3a and 3b
The contact with the cathode electrode 10 causes the surface channel layer 5 to be pinned.
It can be said that this is an effective structure for starting off. The book
In the embodiment, when the impurity concentration is low, p^-Type silicon carbide
Although the base regions 3a and 3b are formed, the impurity concentration is reduced.
The higher the built-in voltage Vbuilt
It can be used well.

In this embodiment, the vertical power MOSFET is manufactured by using silicon carbide. However, if it is to be manufactured using silicon, the p ^- type silicon carbide base regions 3a and 3b, the surface channel layer 5 and the like are not used. It is difficult to control the diffusion amount of thermal diffusion when forming the impurity layer described above, so that it is difficult to manufacture a normally-off type MOSFET similar to the above-described configuration. Therefore, by using SiC as in the present embodiment, a vertical power MOSFET can be manufactured with higher accuracy than when silicon is used.

A normally-off type vertical power MOS
In order to form an FET, it is necessary to set the thickness of the surface channel layer 5 so as to satisfy the condition of the above formula 2, but when silicon is used, the thickness of the surface channel layer 5 is reduced because Vbuilt is low. Considering that it is difficult to control the amount of diffusion of impurity ions, it can be said that manufacturing is extremely difficult. However, when SiC is used, Vbuilt is about three times as high as that of silicon and can be formed by increasing the thickness of the n ⁻ -type layer or increasing the impurity concentration. Therefore, it is possible to manufacture a normally-off type storage MOSFET. It can be said that it is easy.

[Step shown in FIG. 4 (a)] An LTO film 21 is disposed in a predetermined region on the surface channel layer 5, and using this as a mask, N ⁺ ions are implanted to form an n ⁺ source region 4a,
4b is formed. The ion implantation condition at this time is 700
C. and the dose is 1 × 10 ¹⁵ cm ⁻² . [Step shown in FIG. 4B] Then, after removing the LTO film 21, an LTO film 22 is disposed in a predetermined region on the surface channel layer 5 by using a photoresist method, and the pTO is formed by RIE using the LTO film 22 as a mask. ^- type silicon carbide base regions 3a, 3b
The upper surface channel layer 5 is partially etched away.

[Step shown in FIG. 4 (c)]
B ⁺ ions are implanted using the film 22 as a mask to form the deep base layers 30a and 30b. Thereby, a part of the base regions 3a and 3b becomes thicker. The deep base layers 30a and 30b are formed in the n ⁺ type source region 4
a and 4b are formed in portions that do not overlap with each other, and portions of the p ⁻ -type silicon carbide base regions 3a and 3b where the deep base layers 30a and 30b are formed are thicker.
The impurity concentration is formed higher than that of the thin portion where the deep base layer 30a is not formed.

[Step shown in FIG. 5A] After the LTO film 22 is removed, a gate insulating film (gate oxide film) 7 is formed on the substrate by wet oxidation. At this time, the ambient temperature is 1080 ° C. Thereafter, a polysilicon gate electrode 8 is deposited on the gate insulating film 7 by LPCVD. The film formation temperature at this time is 600 ° C.

[Step shown in FIG. 5B] Subsequently, after removing unnecessary portions of the gate insulating film 7, an insulating film 9 made of LTO is formed to cover the gate insulating film 7. More specifically,
The film formation temperature is 425 ° C., and annealing is performed at 1000 ° C. after the film formation. [Step shown in FIG. 5C] Then, the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature. After film formation, annealing at 1000 ° C. is performed.

Thus, the vertical power M shown in FIG.
The OSFET is completed. Next, this vertical power MOSF
The operation (operation) of the ET will be described. This MOSFET operates in a normally-off type accumulation mode. When no voltage is applied to the polysilicon gate electrode, carriers in the surface channel layer 5 are formed by p ⁻ -type silicon carbide base regions 3a and 3b and the surface channel layer. 5 is depleted by the potential generated by the difference in electrostatic potential between the surface channel layer 5 and the work function between the surface channel layer 5 and the polysilicon gate electrode 8. By applying a voltage to the polysilicon gate electrode 8, a potential difference caused by a sum of a work function difference between the surface channel layer 5 and the polysilicon gate electrode 8 and an externally applied voltage is changed. As a result, the state of the channel can be controlled.

That is, the work function of polysilicon gate electrode 8 is the first work function, the work function of p ⁻ -type silicon carbide base regions 3a and 3b is the second work function, and the work function of surface channel layer 5 is Assuming the third work function, the first
Using the difference between the first to third work functions, the first to third work functions, the impurity concentration and the film thickness of the surface channel layer 5 are set so as to deplete the n-type carriers in the surface channel layer 5. be able to.

In the off state, the depletion region is p
^--Type silicon carbide base regions 3a, 3b and polysilicon regions
The electric field created by the gate electrode 8 causes the surface channel
Formed in layer 5. From this state the polysilicon gate
When a positive bias is supplied to the electrode 8, the gate insulation
Film (SiO_Two) At the interface between 7 and the surface channel layer 5
And n⁺From the mold source regions 4a, 4b to n^-Mold drift area
A channel region extending in the direction of region 2 is formed and turned on.
Is switched. At this time, the electron is n⁺Type source
From the regions 4a and 4b via the surface channel layer 5, the surface channel
Flannel layer 5 to n ^-Flows into the epitaxial silicon carbide layer 2. Soshi
And n^--Type silicon carbide epi layer 2 (drift region)
And the electron is n⁺Type silicon carbide semiconductor substrate 1 (n⁺Dray
Flows vertically to

As described above, by applying a positive voltage to the gate electrode 8, a storage channel is induced in the surface channel layer 5, and carriers flow between the source electrode 10 and the drain electrode 11. However, the voltage applied to the gate electrode 8 needs to be higher than a predetermined threshold voltage Vth.
The threshold voltage Vth will be described.

For reference, the threshold voltage Vth of the inversion type MOSFET will be described, and based on this, the threshold voltage Vth of the storage type vertical power MOSFET as in this embodiment will be described. Generally, the threshold value Vth of an inversion type MOSFET is expressed by the following equation.

[0052]

Vth = VFB + 2φB where VFB = φms− (Qs + Qfc + Qi + Qss) / Cox
Which, when replaced, is shown by the following equation.

[0053]

Vth = φms− (Qs + Qfc + Qi + Qss) / C
ox + 2φB Generally, work function difference (electron energy difference) φms between metal and semiconductor, fixed charge at interface between gate oxide film (SiO ₂ ) and n ⁻ -type layer (hereinafter referred to as SiO ₂ / SiC interface). Qfc, mobile ions Qi in the oxide film, and SiO ₂
The energy band is bent by the influence of the surface charge Qss at the / SiC interface. Therefore, the sum of the voltage that cancels the bending of the energy band and the voltage 2φB that starts to form the inversion state becomes the threshold voltage Vth, and is expressed by the above-described equations (3) and (4).

Considering the case of the storage type vertical power MOSFET according to the present embodiment based on this, the p ⁻ type base region 3 is compared with the inversion type MOSFET.
The energy band of the surface channel layer 5 is bent by the work function difference Vbuilt (built-in voltage of the PN junction) of the a, 3b and the surface channel layer 5, and the voltage 2φB for inverting is unnecessary. Therefore, the threshold voltage Vth is expressed by the following equation.

[0055]

Vth = Vbuilt + φms− (Qs + Qfc + Qi +
Qss) / Cox That is, the work function difference Vbuilt on the PN junction side of the surface channel layer 5, the work function difference φms between the metal and the semiconductor on the gate insulating film 7 side, and the amount of energy band bending (Qs + Qfc + Qi + Qss) caused by the oxide film. Since the energy band is bent due to /) / Cox, if a voltage that cancels these is applied, the energy band is flattened and a current flows.

For this reason, the storage type MO in this embodiment is
The threshold voltage Vth of the SFET is expressed by Expression 3. Therefore, in this embodiment, a voltage equal to or higher than the threshold voltage Vth shown in Expression 5 is set as the gate applied voltage. (Second Embodiment) FIG. 6 shows a second embodiment of the present invention. In the present embodiment, the on-resistance is further reduced with respect to the first embodiment, and has substantially the same configuration as that of the first embodiment. The same reference numerals are given and only different configurations will be described.

As shown in FIG. 6, in the present embodiment, n ⁻
P ^- type base regions 3a, 3a
the J-FET portion serving as sites flanking the b, p ^- type base region 3a, the low resistance region 30 of n ⁺ type junction depth is formed deeper than 3b is provided. The low resistance region 30 has a configuration in contact with the surface channel layer 5.

The vertical power MOSF thus configured
ET can be formed by selectively ion-implanting an n-type impurity into the J-FET portion before forming the surface channel layer 5 or after forming the surface channel layer 5. As described above, since the low-resistance region 30 is formed, the resistance of the J-FET portion decreases, and the vertical power MO
The on-resistance of the SFET can be further reduced.

By forming low resistance region 30 in this manner, the extension of the depletion layer from p ⁻ -type silicon carbide base regions 3a and 3b can be reduced, and the J-FET portion is formed by the depletion layer. Can be prevented from reducing the width of the current path (width in the left-right direction on the paper). For this reason, it is possible to prevent the resistance value from increasing due to the reduction of the current path.

FIG. 7 shows the vertical power M in this embodiment.
5 shows a drain current ID-drain voltage VD characteristic of an OSFET. For reference, FIG. 5 shows the drain current ID-drain voltage VD characteristic of the vertical power MOSFET according to the first embodiment. As shown in this figure,
The vertical power MOSFET according to the present embodiment in which the low resistance region 30 is formed has the same drain voltage VD as compared to the vertical power MOSFET according to the first embodiment.
It can be seen that the drain current VD flowing at this time is large.

As described above, the on-resistance of the vertical power MOSFET can be further reduced by forming the low-resistance region 30. Further, the low resistance region 30
As shown in FIGS. 8 and 9, the p ⁻ -type base regions 3a and 3b
It does not matter if it is shallower than this, and it does not have to be in contact with the surface channel layer 5.
Any structure that suppresses the extension of the depletion layer from the p ⁻ -type base regions 3a and 3b may be used. These low-resistance regions 30 can be formed by adjusting the ion implantation energy to control the implantation depth.

(Other Embodiments) In the above embodiment, n ⁻
The surface channel layer 5 is formed by directly implanting ions into the surface layer portion of the p-type silicon carbide epilayer 2 and the surface portions (surface layer portions) of the p ⁻ -type silicon carbide base regions 3a and 3b, as shown in FIG. As described above, an n ⁻ -type surface channel layer 5 is epitaxially grown thereon, and then the n-type impurity concentration in a portion other than the channel region in the surface channel layer 5 is selectively increased by photolithography and ion implantation. It may be. However, since the number of manufacturing steps increases in such a case, it is preferable to manufacture the vertical power MOSFET by the method of the above embodiment.

Further, as shown in FIG.⁺Type source
After the regions 4a and 4b have been formed, n⁺Type source area
Area 4a, 4b or p^--Type silicon carbide base regions 3a, 3b and
And n ^-Channel layer 5 on the surface of type silicon carbide epilayer 2
Is epitaxially grown,
The portion 5b other than the portion 5a to be the channel region is n⁺Mold layer
It may be formed as. However, in this case
However, the surface channel layer 5 is epitaxially grown and
Thereafter, ion implantation is further performed in the same manner as shown in FIG.
And the number of manufacturing processes increases.
It can be said that the method shown in FIG.

Further, in the second embodiment, the low resistance region 3
Although 0 is configured to be in contact with the surface channel layer 5, they may be separated from each other. In this case, since the low resistance region 30 is formed separately from the portion 5 b of the surface channel layer 5, the low resistance region 30 can be formed to have a higher concentration than the surface channel layer 5. Since the n ⁻ -type region having high resistance remains between the surface channel layer 5 and the surface channel layer 5, not only the same effect as in the second embodiment can be obtained, but also the p ⁻ -type silicon carbide base regions 3a and 3b. Can be reduced, and the withstand voltage of the vertical power MOSFET can be improved.

[Brief description of the drawings]

FIG. 1 is a vertical power MO according to a first embodiment of the present invention.
It is sectional drawing of SFET.

FIG. 2 is a graph showing gate applied voltage-drain current characteristics for explaining the on-resistance of the vertical power MOSFET in FIG.

FIG. 3 is a view showing a manufacturing process of the vertical power MOSFET shown in FIG. 1;

FIG. 4 is a view illustrating a manufacturing process of the vertical power MOSFET following FIG. 3;

FIG. 5 is a diagram showing a manufacturing step of the vertical power MOSFET following FIG. 4;

FIG. 6 shows a vertical power MO according to a second embodiment of the present invention.
It is sectional drawing of SFET.

7 is a diagram showing a drain current ID-drain voltage VD characteristic of the vertical power MOSFET shown in FIG. 6;

FIG. 8 is a diagram showing a case where a low resistance region 30 deeper than the surface channel layer 5 is formed.

FIG. 9 is a diagram showing a case where the surface channel layer 5 and the low resistance region 30 are separated from each other.

FIG. 10 is a vertical power MOSFET according to another embodiment.
It is sectional drawing for demonstrating T.

FIG. 11 is a vertical power MOSFET according to another embodiment.
It is sectional drawing for demonstrating T.

FIG. 12 is a vertical power MOSF filed by the present applicant.
It is sectional drawing which shows the structure of ET.

[Explanation of symbols]

1 ... n ⁺ -type silicon carbide semiconductor substrate, 2 ... n ^- -type silicon carbide epitaxial layer, 3a, 3b ... p ^- type silicon carbide base region, 4a, 4b ... n ⁺ -type source region, 5 ... surface channel layer (n ^- Type SiC layer), 5a... N ^- type layer portion, 5b.
n ⁺ -type layer portion, 7: gate insulating film, 8: gate electrode,
9: insulating film, 10: source electrode, 11: drain electrode layer, 30: low resistance region.

Claims (10)

[Claims] A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface and made of silicon carbide.
A first conductivity type semiconductor layer (2) formed on the main surface of the semiconductor substrate (1) and made of silicon carbide having a higher resistance than the semiconductor substrate (1); A second conductivity type base region (3a, 3b) formed in a predetermined region of a surface layer portion and having a predetermined depth;
A first conductivity type source region (4a, 4b) formed in a predetermined region of a surface portion of the base region (3a, 3b) and shallower than a depth of the base region (3a, 3b); (3a, 3b) and the surface of the semiconductor layer (2), the source regions (4a, 4b).
b) and the semiconductor layer (2).
Surface channel layer of first conductivity type made of silicon carbide (5)
A gate insulating film (7) formed on the surface of the surface channel layer (5); and a gate electrode (8) formed on the gate insulating film.
And the base region (3a, 3b) and the source region (4
a, 4b), the source electrode (1
0), and a drain electrode (11) formed on the back surface of the semiconductor substrate (1), and the semiconductor layer (2) of the surface channel layer (5).
A portion (5b) arranged on the surface portion of the silicon carbide semiconductor device has an impurity concentration higher than that of the semiconductor layer (2). 2. When the potential of the gate electrode (8) is substantially zero, the surface channel layer (5) includes a depletion layer extending from the gate insulating film (7) and the base region (3).
2. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is pinched off by a depletion layer extending from a, 3b). 3. The junction depth of the J-FET portion of the semiconductor layer (2) located on the side surface of the base region (3a, 3b) is larger than that of the surface channel region (5). The silicon carbide semiconductor device according to claim 1, wherein a low resistance region of the first conductivity type is formed. 4. A junction depth of the J-FET portion of the semiconductor layer (2) located on a side surface of the base region (3a, 3b) is larger than that of the base region (3a, 3b). 3. The silicon carbide semiconductor device according to claim 1, wherein the first conductive type low-resistance region is formed. 4. 5. The low resistance region (30) and the surface channel layer (5) are separated from each other.
3. The silicon carbide semiconductor device according to item 1. 6. A step of forming a first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate (1) on a main surface of the first conductivity type semiconductor substrate (1). Forming a second conductivity type base region (3a, 3b) having a predetermined depth in a predetermined region of a surface portion of the semiconductor layer (2); and forming the semiconductor layer (2) and the base region ( 3a, 3b)
Forming a surface channel layer (5) on the upper surface of the base region;
Forming a first conductivity type source region (4a, 4b) in contact with the surface channel layer (5) and shallower than the depth of the base region (3a, 3b). In the step of forming the surface channel layer (5), the impurity concentration in a portion (5b) of the surface channel layer (5) disposed on a surface portion of the semiconductor layer (2) is adjusted by the semiconductor. A method for manufacturing a silicon carbide semiconductor device, comprising a step of increasing the impurity concentration in a layer (2). 7. The step of increasing the impurity concentration of the surface channel layer (5) includes the steps of: (a) forming a surface layer portion of the semiconductor layer (2) and the base region (3);
7. The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein the step of a) and the step of b) simultaneously performing ion implantation on the surface layer portion. 8. A method of performing ion implantation from a surface of the semiconductor layer (2) where the base regions (3a, 3b) are not formed, wherein a junction depth is larger than that of the surface channel region (5). The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein a low resistance region of one conductivity type is formed. 9. Ion implantation is performed from a surface of the semiconductor layer (2) where the base region (3a, 3b) is not formed, and a junction depth is deeper than the base region (3a, 3b). The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein a low resistance region of the first conductivity type is formed. 10. In the step of forming the low-resistance region (30), the low-resistance region (30) includes the surface channel layer (5).
The method of manufacturing a silicon carbide semiconductor device according to claim 7, wherein the ion implantation is performed so as to be away from the silicon carbide semiconductor device.