JP2007059632A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a good operating voltage and a sufficient avalanche resistance, and also to provide its manufacturing method. <P>SOLUTION: A mask is formed at least on the bottom face of a trench 25 formed in the semiconductor substrate 20 of the semiconductor device 10. By diffusing a conductive dopant opposite from that of a dopant diffused in a base region 22 on the side face of the trench 25 via an opening 25a of the trench 25, a channel region 23 is formed having a dopant concentration lower than that in the base region 22. The dopant concentration of only the channel region can be lowered regardless of that in the base region 22, the semiconductor device 10 having a good operating voltage, and a sufficient avalanche resistance can be obtained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a trench structure and a manufacturing method thereof, and more particularly to an insulated gate field effect transistor having a trench structure and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, a semiconductor element having a trench structure has been used in order to achieve high cell integration, improved breakdown voltage, reduced on-resistance, and the like.

  For example, an insulated gate transistor having a trench structure has a gate structure in which a conductor film functioning as a gate electrode is buried in a trench (groove) formed on the upper surface of a semiconductor substrate via a gate insulating film. A semiconductor region provided on the upper surface side of the semiconductor substrate is a source region, a semiconductor region provided on the lower surface side is a drain region, and a base region formed between the source region and the drain region is provided. Of the base region, a region in contact with the gate insulating film functions as a channel when a voltage is applied to the gate electrode.

  By the way, in order to lower the operating voltage of such an insulated gate transistor, it is preferable that the impurity concentration of the region where the channel of the base region is formed be low. However, if the impurity concentration not only in the region where the channel is formed but also in the entire base region is lowered in order to lower the operating voltage, the avalanche resistance is lowered, which is not preferable.

Therefore, before forming the gate insulating film and the gate electrode, an oxide film is formed in the trench, and the impurities in the base region are diffused into the oxide film, so that the impurity concentration in the region near the gate insulating film in the base region is reduced. A technique for reducing the level has been developed (for example, Patent Document 1).
JP 2000-228520 A

  Incidentally, in the method of manufacturing a semiconductor element disclosed in Patent Document 1, an oxide film is formed on the bottom and side surfaces of the trench. Therefore, even the impurities in the drain region formed on the bottom surface of the trench are absorbed by the oxide film, the impurity concentration in the drain region is lowered, and the withstand voltage and the like are deviated from the initial design.

  In addition, in the method for manufacturing a semiconductor element disclosed in Patent Document 1, it is necessary to form a high impurity concentration region by diffusing impurities in a separate process so that a region in contact with the source electrode in the base region is in a resistive contact. Therefore, there is a problem that the manufacturing process increases. Furthermore, if there is variation in the absorption of impurities into the oxide film, the threshold voltage will vary, and the impurity diffused in the base region is diffused into the oxide film, making it difficult to control the impurity concentration in the depth direction from the trench side. There are some problems.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device having a good operating voltage and an avalanche resistance and a method for manufacturing the same.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the first aspect of the present invention includes:
One main surface of a semiconductor substrate including a first conductivity type first semiconductor region and a second conductivity type second semiconductor region formed on an upper surface of the first semiconductor region, the second semiconductor region to the main surface Forming a trench so as to extend to the first semiconductor region;
A mask forming step of forming a mask so as to cover one main surface of the semiconductor substrate and at least a bottom surface of the trench;
An impurity diffusion step of diffusing an impurity of a first conductivity type in a region where the mask on the side surface of the trench is not formed through the opening of the trench;
A mask removal step of removing the mask;
An insulating film forming step of forming an insulating film on the bottom and side surfaces of the trench;
A gate electrode forming step of forming a gate electrode so as to fill the trench through the insulating film.

  In the mask forming step, the mask may be formed so as to cover the first semiconductor region exposed through the trench.

  In the trench forming step, the opening may be formed in a tapered shape.

  In the impurity diffusion step, impurities may be diffused by an ion implantation method.

In order to achieve the above object, a semiconductor element according to the second aspect of the present invention is:
A first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper surface of the first semiconductor region; and a first conductivity type formed on a surface region of the second semiconductor region. A semiconductor substrate comprising: a third semiconductor region; and a trench formed on one main surface of the semiconductor substrate so as to extend from the third semiconductor region to the first semiconductor region;
An insulating film formed on the surface of the trench;
A gate electrode formed so as to fill the trench through the insulating film;
With
Further, the second semiconductor region includes a second semiconductor region of a second conductivity type formed in a region in contact with the insulating film and having a lower impurity concentration than the second semiconductor region,
The impurity concentration of the first semiconductor region is substantially the same in a region in contact with the insulating film and in other regions.

  The opening of the trench may be formed in a tapered shape.

  According to the present invention, a mask is formed on at least the bottom surface of the trench, and an impurity having a conductivity type opposite to the conductivity type of the base region is implanted into the trench surface through the opening of the trench. And a semiconductor device provided with avalanche tolerance and its manufacturing method can be provided.

  A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  A semiconductor device 10 according to an embodiment of the present invention is shown in FIG. The present invention will be described taking an insulated gate field effect transistor as an example of a semiconductor element. FIG. 1 is a partial cross-sectional view of the semiconductor element 10.

  As shown in FIG. 1, the semiconductor element 10 includes a semiconductor substrate 20, a gate electrode 31, a gate insulating film 32, a source electrode 33, an interlayer insulating film 34, and a drain electrode 35.

  As shown in FIG. 1, the semiconductor substrate 20 includes a drain region 21, a base region 22, a channel region 23, a source region 24, and a trench 25.

  The drain region 21 is composed of an N-type semiconductor region in which an N-type (first conductivity type) impurity such as phosphorus or antimony (arsenic) is diffused. A drain electrode 35 is formed on the lower surface of the drain region 21. Further, the impurity concentration of the drain region 21 is formed substantially the same in the region near the gate insulating film 32 and the other regions.

  The base region 22 is composed of a P-type semiconductor region in which a P-type (second conductivity type) impurity such as boron is diffused, and is formed on the drain region 21. The impurity concentration of the base region 22 is formed higher than the impurity concentration of the channel region 23 in order to obtain a good avalanche resistance of the semiconductor element 10. A source electrode 33 is formed on the base region 22, and substantially the same voltage as the source electrode 33 is applied to the base region 22.

  The channel region 23 is composed of a P-type semiconductor region in which a P-type (second conductivity type) impurity such as boron is diffused. The channel region 23 is formed between the base region 22 and the gate insulating film 32, the source region 24 is formed on the upper surface of the channel region 23, and the drain region 21 is formed on the lower surface of the channel region. Further, when a predetermined voltage is applied to the gate electrode 31, a channel is formed near the gate insulating film 32 in the channel region 23. The impurity concentration of the channel region 23 is formed to be lower than the base region 22 by a predetermined amount in order to lower the threshold voltage and lower the operating voltage of the semiconductor element 10.

  The source region 24 is composed of an N-type semiconductor region in which an N-type (first conductivity type) impurity such as phosphorus is diffused, and is formed on the upper surfaces of the base region 22 and the channel region 23. A source electrode 33 is formed so as to be in contact with the source region 24.

  The trench 25 is formed in the upper main surface of the semiconductor substrate 20 as shown in FIG. The cross-sectional shape of the trench 25 is substantially square as shown in FIG. 1 and is formed to extend from the source region 24 to the drain region 21. A gate insulating film 32 is formed on the surface of the trench 25, and a gate electrode 31 is formed so as to fill the trench 25 via the gate insulating film 32.

  The gate electrode 31 is made of polysilicon or the like imparted with conductivity by diffusing boron, phosphorus or the like, and is formed so as to fill the trench 25 through the gate insulating film 32. Further, the upper surface of the gate electrode 31 is formed to be substantially equal to the upper main surface of the semiconductor substrate 20. The upper surface of the gate electrode 31 can be formed to be located slightly below the upper main surface of the semiconductor substrate 20.

  The gate insulating film 32 is made of an insulator, such as a silicon oxide film, and is formed on the surface of the trench 25. The gate insulating film 32 is formed to a thickness that can maintain a predetermined threshold voltage. The gate insulating film 32 is formed to a thickness that does not affect the impurity concentration of the drain region 21.

  The source electrode 33 is made of a conductor, such as aluminum (Al). The source electrode 33 is formed so as to be in contact with the source region 24 through the source contact hole 34 a and cover the interlayer insulating film 34. The source electrode 33 is formed so as to cover not only the source region 24 but also the base region 22. Thus, by forming the source electrode 33 so as to cover the base region 22, substantially the same voltage as that of the source region 24 can be applied to the base region 22.

  The interlayer insulating film 34 is made of an insulator, for example, NSG (nondoped silicate glass), BPSG (boron phosphor silicate glass), etc., and is formed between the gate electrode 31 and the source electrode 33 to electrically insulate them. . A source contact hole 34 a is formed in a region corresponding to the source electrode 33 of the interlayer insulating film 34.

  The drain electrode 35 is made of, for example, a metal multilayer film made of aluminum (Al) or the like, and is formed on the lower main surface of the semiconductor substrate 20.

  In the semiconductor element 10 having the above configuration, the threshold voltage can be lowered and the operating voltage of the semiconductor element 10 can be lowered by providing the channel region 23 with a low impurity concentration in the region in contact with the gate insulating film 32. It becomes. Moreover, since the impurity concentration of the base region 22 is kept high, the semiconductor element 10 has a good avalanche resistance.

  Next, a method for manufacturing the semiconductor element 10 according to the embodiment of the present invention will be described with reference to the drawings. In addition, the method described below is an example, and if the same result is obtained, it will not be restricted to this.

  First, an N-type semiconductor substrate 51 is prepared. Next, P-type impurities are diffused on the upper main surface of the semiconductor substrate 51 by a thermal diffusion method, an ion implantation method, or the like to form a P-type semiconductor region 52 as shown in FIG.

  Next, a resist pattern is formed on the P-type semiconductor region 52 by photolithography or the like, and then, as shown in FIG. 2B by a reactive ion etching (RIE) method or the like, as shown in FIG. Trench 25 is formed to extend from region 52 to N-type semiconductor substrate 51. Thereby, the drain region 21 is formed.

  Next, a mask 71 is formed on the entire P-type semiconductor region 52 except for the opening 25 a of the trench 25. Further, a mask 72 is formed so as to cover at least the bottom surface of the trench 25 and preferably cover the drain region 25 exposed through the trench 25. Note that any of masks 71 and 72 may be used as long as impurity diffusion can be prevented satisfactorily, and a resist, an insulator, or the like can be used.

Next, as shown in FIG. 3D, N-type impurities having a conductivity type opposite to that of the P-type semiconductor region 52 such as phosphorus and arsenic are formed on the side surfaces of the trench 25 through the opening 25a of the trench 25. Ions are implanted to a predetermined depth. Thereby, a P ⁻ type semiconductor region 53 is formed.

  Next, the mask 71 formed on the P-type semiconductor region 52 and the mask 72 formed in the trench are removed.

  Next, a resist pattern (not shown) having an opening corresponding to the region where the source region 24 is formed is formed on the P-type semiconductor region 52 by photolithography or the like. Subsequently, an N-type impurity is diffused by an ion implantation method or the like through the opening to form the source region 24. As a result, the base region 22 is formed.

  Next, the gate insulating film 32 having a predetermined thickness is formed on the surface of the trench 25 by, eg, thermal oxidation.

  Next, polysilicon is deposited by, for example, a low pressure CVD (Chemical Vapor Deposition) method so as to fill the trench 25 in which the gate insulating film 32 is formed. The polysilicon fills the trench 25 and further covers the upper surface of the base region 22 and then etches back to substantially the same position as the upper main surface of the semiconductor substrate 20. Subsequently, for example, phosphorus, boron or the like is diffused in the polysilicon to impart conductivity. As a result, the gate electrode 31 is formed as shown in FIG.

  Subsequently, an interlayer insulating film 34 is formed on the gate electrode 31 by, for example, a low pressure CVD method, and a resist pattern (not shown) having an opening in a region corresponding to the source contact hole 34a is formed by photolithography or the like. The source contact hole 34a is formed by etching using the resist pattern as a mask.

Next, for example, aluminum (Al) is deposited by sputtering or the like so as to fill the source contact hole 34 a and further cover the interlayer insulating film 34, thereby forming the source electrode 33.
Further, for example, aluminum (Al) is deposited on the lower main surface of the semiconductor substrate 20 by sputtering or the like to form the drain electrode 35.
From the above steps, the semiconductor element 10 is manufactured.

  According to the method of manufacturing a semiconductor element of the present embodiment, a mask made of a resist or the like is formed so as to cover at least the bottom surface of the trench 25, and the conductivity type is opposite to the base region 22 from the oblique direction on the side surface of the trench 25. By diffusing the N-type impurity, the channel region 23 having a low impurity concentration can be easily formed. As a result, the threshold voltage can be lowered and the operating voltage of the semiconductor element 10 can be lowered. Further, since the impurity concentration of the base region 22 is higher than that of the channel region 23, the semiconductor element 10 has a good avalanche resistance.

  Further, according to the manufacturing method of the present embodiment, since the drain region 21 is covered with the mask 72, the impurity concentration does not increase when the channel region 23 is formed. Further, the impurity concentration of the N-type semiconductor region in contact with the trench does not decrease as in the prior art, and the characteristics of the semiconductor element 10 do not deviate from the initial design. Further, in the manufacturing method of the present embodiment, since the impurity concentration of only the channel region 23 is lowered, unlike the conventional technique, the step of forming the base region 22 in contact with the source electrode 33 at a high concentration becomes unnecessary. In addition, since the channel region 23 is formed by the ion implantation method, the threshold voltage does not vary due to the degree of diffusion to the oxide film, and the impurity concentration in the depth direction can be easily controlled from the side surface of the trench. Can be done.

The present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
For example, in the above-described embodiment, the insulated gate field effect transistor has been described as an example of the semiconductor element 10, but the invention is not limited thereto, and an insulated gate bipolar transistor may be used.

  In the above-described embodiment, the case where the openings of the groove and the second groove are formed in a tapered shape has been described as an example. However, the opening may not be formed in a tapered shape. However, the opening is preferably chamfered in order to improve step coverage (step coverage).

  In the above-described embodiment, the N-type is described as the first conductivity type, and the P-type is described as the second conductivity type, but this may be reversed.

It is sectional drawing which shows the structural example of the semiconductor element which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor element which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor element which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the semiconductor element which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor element 20 Semiconductor base | substrate 21 Drain region 22 Base region 23 Channel region 24 Source region 25 Trench 31 Gate electrode 32 Gate insulating film 33 Source electrode 34 Interlayer insulating film 35 Drain electrode

Claims (4)

One main surface of a semiconductor substrate including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type formed on an upper surface of the first semiconductor region, the second semiconductor region to the main surface Forming a trench so as to extend to the first semiconductor region;
A mask forming step of forming a mask so as to cover one main surface of the semiconductor substrate and at least a bottom surface of the trench;
An impurity diffusion step of diffusing an impurity of the first conductivity type in a region where the mask on the side surface of the trench is not formed through the opening of the trench;
A mask removal step of removing the mask;
An insulating film forming step of forming an insulating film on the bottom and side surfaces of the trench;
And a gate electrode forming step of forming a gate electrode so as to fill the trench through the insulating film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the mask forming step, the mask is formed so as to cover the first semiconductor region exposed through the trench.   4. The method of manufacturing a semiconductor device according to claim 1, wherein, in the impurity diffusion step, impurities are diffused by an ion implantation method. 5. A first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper surface of the first semiconductor region; and a first conductivity type formed on a surface region of the second semiconductor region. A semiconductor substrate comprising: a third semiconductor region;
A trench formed on one main surface of the semiconductor substrate so as to extend from the third semiconductor region to the first semiconductor region;
An insulating film formed on the surface of the trench;
A gate electrode formed so as to fill the trench through the insulating film,
Further, the second semiconductor region includes a second semiconductor region of a second conductivity type formed in a region in contact with the insulating film and having a lower impurity concentration than the second semiconductor region,
An impurity concentration of the first semiconductor region is substantially the same in a region in contact with the insulating film and in other regions.

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