JP2013219161A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor device manufacturing method, which reduces variation in characteristics and enables easy manufacturing of the semiconductor device.SOLUTION: A semiconductor device of a present embodiment comprises a first conductivity type source region 4 formed on a surface part of a well region 3; a trench 40 formed in a predetermined region of the source region 4 such that at least a bottom face is exposed in a drift layer 2; a first conductivity type channel layer 6 formed in the well region 3 along lateral faces of the trench 40; a gate insulation film 7 formed so as to cover the bottom face and the lateral faces of the trench 40; a gate electrode 8 formed on the gate insulation film 7 so as to fill the trench 40; and an interlayer insulation film 9 formed so as to cover the gate electrode 8, the gate insulation film 7 and a part of the source region 4. The channel layers 6 are formed only between the drift layer 2 and the source region 4. A first conductivity type impurity concentration of the channel layer 6 is totally uniform.

Description

  The present invention relates to a semiconductor device using silicon carbide (SiC) and a method for manufacturing the semiconductor device.

  In a power electronics device, as means for switching between execution and stop of power supply for driving a load such as an electric motor, for example, a silicon IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Field Effect Transistor) is used. A switching element is used. Application of MOSFETs using silicon carbide semiconductors (hereinafter also referred to as silicon carbide MOSFETs) is being studied in the high voltage region from about 1 kV to higher. These switching elements are all insulated gate semiconductor devices.

  A semiconductor device using a silicon carbide (hereinafter also referred to as SiC) semiconductor is excellent in high voltage, large current, and high temperature operation as compared with a semiconductor device using a silicon (Si) semiconductor. Accordingly, semiconductor devices using silicon carbide semiconductors are being developed as next-generation power semiconductor devices.

  Among silicon carbide MOSFETs used as power semiconductors, vertical MOSFETs are particularly important applications. There are different types of vertical MOSFETs, such as a planar type and a trench type, depending on the gate structure.

  A vertical MOSFET used as a power semiconductor has an element structure in which a large number of MOSFET unit cells (unit cells, hereinafter also referred to as MOSFET cells) are connected in parallel in order to realize a large current. In order to realize a high-power semiconductor device, it is necessary to sufficiently reduce the on-resistance. In a vertical MOSFET for power made of SiC, a structure in which a trench called a trench is formed in a SiC substrate and a gate insulating film and a gate electrode are embedded in the trench is being studied. In this MOSFET (hereinafter also referred to as a trench gate type MOSFET), by applying a voltage to the gate electrode, the p-type SiC in contact with the side wall (side surface of the trench) of the gate insulating film formed in the trench is inverted, The on-resistance is lowered by connecting a source electrode formed on the SiC surface and a drift layer made of n-type SiC formed below p-type SiC.

  However, in the above-described trench gate type MOSFET, the gate insulating film is formed by oxidizing SiC. When the gate insulating film is formed by oxidation treatment, carbon in SiC remains at the interface between SiC and the oxide film (SiO 2), which becomes a defect, lowering carrier mobility and increasing on-resistance.

  Conventional trench gate type MOSFETs and manufacturing methods thereof are disclosed in, for example, Patent Documents 1 to 4. In the technique disclosed in Patent Document 1, after forming a trench, an insulating film is provided except for the edge of the trench. Next, n-type impurities are ion-implanted from the normal direction of the substrate using the insulating film as a mask. Thereby, an n − type semiconductor layer is formed in the channel portion. With such a configuration, the resistance of the channel portion is reduced by allowing a current to flow away from the interface between the SiC and the oxide film where defects exist. The above “n−” indicates an n-type impurity having a low impurity concentration.

  In the technique disclosed in Patent Document 2 or 3, an n − type semiconductor layer is formed in the channel portion by forming an n − type epitaxial layer on the inner wall of the trench by an epitaxial growth method. By adopting such a structure, the resistance of the channel portion is reduced.

  Further, in the technology disclosed in Patent Document 4, a tapered trench is formed, and n − type impurities are ion-implanted from the normal direction of the substrate through a thin oxide film formed on the inner wall of the trench, An n − type semiconductor layer is formed in the channel portion. By adopting such a structure, the resistance of the channel portion is reduced.

Japanese Patent No. 3097608 Japanese Patent No. 3307184 Japanese Patent No. 3419163 Japanese Patent No. 3396509

  In the trench gate type MOSFET disclosed in Patent Document 1, the n − type semiconductor layer of the channel portion is formed by ion implantation from the normal direction of the substrate. The channel length needs to be 1 to 2 μm. In the trench gate type MOSFET, the channel length is equal to the depth of the p-type impurity region. That is, in the method disclosed in Patent Document 1, n − -type impurities must be implanted to a depth of 1 to 2 μm, which requires an ion implanter having an acceleration voltage exceeding 1 MV. Further, in order to make the concentration of the n − -type impurity in the depth direction uniform, it is necessary to perform impurity implantation a plurality of times, and thus it cannot be easily manufactured.

  Further, in the trench gate type MOSFET disclosed in Patent Document 2 or 3, since the epitaxial layer of the channel portion is formed by the epitaxial growth process, the variation in the thickness of the n − type semiconductor layer and the concentration of the n − type impurity is caused. There is a problem that it cannot be controlled to 10% or less, and the variation in characteristics of the fabricated MOSFET becomes large. Moreover, in order to adjust the film thickness formed by epitaxial growth with respect to the side surface and bottom surface of a trench, it is necessary to use a (000-1) carbon surface, and the board | substrate which can be used will be restrict | limited. Further, since the n − type semiconductor layer is formed up to the N − drift layer at the bottom of the trench, the N type impurity concentration in this portion (N − drift layer) increases, and the off breakdown voltage is deteriorated and the parasitic capacitance is increased. Problem arises. If the n − type semiconductor layer extends to the N − drift layer, a MOSFET having a particularly high off breakdown voltage (eg, 1.2 kV, 3.3 kV) cannot be realized.

  In the trench gate type MOSFET disclosed in Patent Document 4, the n − type semiconductor layer of the channel portion is formed by ion implantation from the normal direction of the substrate. In this method, although the variation in the concentration of the n − -type impurity is smaller than that in the above epitaxial growth step, there is a limit to providing a taper in the trench. Moreover, the board | substrate which can be used is restrict | limited similarly to patent document 2 or 3. Further, as in Patent Document 2 or 3, since the n − type semiconductor layer is formed up to the N − drift layer at the bottom of the trench, problems such as deterioration of off breakdown voltage and increase in parasitic capacitance occur.

  The present invention has been made to solve these problems, and it is an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device that can be easily manufactured with less variation in characteristics. .

  In order to solve the above problems, a semiconductor device according to the present invention includes a semiconductor substrate, a first conductivity type drift layer formed on the semiconductor substrate, and a second conductivity type formed on a surface portion of the drift layer. A well region; a first conductivity type source region formed on a surface portion of the well region; a second conductivity type well contact region formed on a surface portion of the well region and different from the source region; A trench formed in a predetermined region of the source region so that at least a bottom surface is exposed by the drift layer; a channel region of a first conductivity type formed in the well region along the side surface of the trench; A gate insulating film formed so as to cover the bottom surface and the side surface; a gate electrode formed on the gate insulating film so as to fill a trench; the gate electrode, the gate insulating film, and a part of the gate insulating film; An interlayer insulating film formed to cover the source region, an interlayer insulating film, a source electrode formed to cover the well contact region and the source region not covered with the interlayer insulating film, and a semiconductor substrate A drain electrode formed on the side opposite to the side on which the drift layer is formed, the channel layer is formed only between the drift layer and the source region, and the impurity concentration of the first conductivity type of the channel layer is It is characterized by being uniform.

  The method for manufacturing a semiconductor device according to the present invention includes (a) a step of forming a first conductivity type drift layer on a semiconductor substrate, and (b) a step of forming a second conductivity type well region on the drift layer. (C) forming a first conductivity type source region on the surface of the well region; (d) forming a mask on the source region so that the predetermined region becomes an opening; (E) forming a trench through the source region and the well region so that at least the drift layer is exposed on the bottom surface in the opening, and (f) only the source region and well region on the side surface of the trench from the opening. (G) forming a gate insulating film so as to cover the bottom and side surfaces of the trench, and (h) filling the trench on the gate insulating film. And forming a over gate electrode, a method of manufacturing a semiconductor device.

  According to the present invention, the semiconductor substrate, the first conductivity type drift layer formed on the semiconductor substrate, the second conductivity type well region formed on the surface portion of the drift layer, and the surface portion of the well region are formed. The first conductivity type source region, the second conductivity type well contact region formed in a region different from the source region on the surface of the well region, and a predetermined region of the source region have at least a bottom surface A trench formed so as to be exposed by the drift layer; a channel region of a first conductivity type which is a well region and is formed along a side surface of the trench; and a gate formed so as to cover a bottom surface and a side surface of the trench An insulating film, a gate electrode formed on the gate insulating film so as to fill the trench, and an interlayer insulating film formed so as to cover the gate electrode, the gate insulating film, and a part of the source region; A source electrode formed so as to cover the film, the interlayer insulating film, the well contact region and the source region that are not covered by the interlayer insulating film, and a side of the semiconductor substrate opposite to the side on which the drift layer is formed Since the drain layer is formed, the channel layer is formed only between the drift layer and the source region, and the impurity concentration of the first conductivity type of the channel layer is uniform throughout, The variation in characteristics can be reduced and the device can be easily manufactured.

It is sectional drawing which shows an example of a structure of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 1 of this invention. It is a top view which shows an example of a structure of the semiconductor device by Embodiment 1 of this invention. It is AA sectional drawing of FIG. 14 by Embodiment 1 of this invention. It is sectional drawing which shows an example of a structure of the semiconductor device by Embodiment 1 of this invention. It is sectional drawing which shows an example of a structure of the semiconductor device by the modification 1 of Embodiment 1 of this invention. It is sectional drawing which shows an example of a structure of the semiconductor device by the modification 2 of Embodiment 1 of this invention. It is sectional drawing which shows an example of the shape of the trench of the semiconductor device by the modification 3 of Embodiment 1 of this invention. It is sectional drawing which shows an example of the shape of the trench of the semiconductor device by the modification 4 of Embodiment 1 of this invention. It is a top view which shows an example of a structure of the semiconductor device by the modification 5 of Embodiment 1 of this invention. It is a figure which shows an example of a structure of the semiconductor device by the modification 8 of Embodiment 1 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows an example of the manufacturing method of the semiconductor device by Embodiment 2 of this invention. It is a top view which shows a hexagonal crystal. It is a figure which shows arrangement | positioning of the atom in a hexagonal crystal.

  Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment 1>
FIG. 1 is a sectional view showing an example of the configuration of a trench gate type MOSFET which is a semiconductor device according to the first embodiment of the present invention. In the first embodiment, a semiconductor device using silicon carbide (silicon carbide semiconductor device) will be described.

  First, the configuration of the trench gate type MOSFET that is the semiconductor device according to the first embodiment will be described.

  As shown in FIG. 1, the trench gate type MOSFET according to the first embodiment includes a silicon carbide semiconductor substrate 1, an n-type (first conductivity type) drift layer 2, and a p-type (second conductivity type) well. Region 3, n-type source region 4, p-type well contact portion 5, n-type channel layer 6, gate insulating film 7, gate electrode 8, interlayer insulating film 9, source electrode 10, The drain electrode 20 is provided.

  Silicon carbide semiconductor substrate 1 (semiconductor substrate) is an n-type low-resistance silicon carbide semiconductor substrate, and is realized, for example, by a silicon carbide semiconductor substrate having a polytype of 4H.

  N type drift layer 2 made of silicon carbide is formed on silicon carbide semiconductor substrate 1 in a stacked manner.

  The well region 3 is formed on the surface portion of the drift layer 2. The well region 3 contains a p-type impurity such as aluminum (Al).

  The source region 4 is formed in a part of the surface portion of the well region 3 so as to be shallower than the thickness of the well region 3. The source region 4 contains an n-type impurity such as nitrogen (N).

  The well contact portion 5 (well contact region) is formed in a region different from the source region 4 on the surface portion of the well region 3 so as to be in contact with the source region 4.

  A trench 40 is formed in a predetermined region of the source region 4 so as to penetrate the well region 3 and the source region 4 in the thickness direction. In the first embodiment, trench 40 is formed so as to penetrate source region 4 and well region 3 and reach the inside of drift layer 2. That is, the trench 40 is formed so that at least the bottom surface is exposed by the drift layer 2.

  The gate insulating film 7 is formed (so as to cover) the inner wall including the side surface and the bottom surface of the trench 40. In the first embodiment, the gate insulating film 7 is made of silicon oxide.

  The gate electrode 8 is formed on the gate insulating film 7 so as to fill the trench 40. In other words, the gate electrode 8 is provided in contact with the gate insulating film 7 on the radially inner side of the trench 40. In the first embodiment, gate electrode 8 is made of polycrystalline silicon doped with n-type impurities.

  The interlayer insulating film 9 is formed so as to cover the gate electrode 8. More specifically, the interlayer insulating film 9 is formed so as to cover a part of the gate electrode 8, the gate insulating film 7, and the source region 4 on the gate electrode 8 side. The interlayer insulating film 9 is formed so that the remaining portion except the part of the source region 4 on the gate electrode 8 side and the well contact portion 5 are exposed and opened, and this portion (opening portion) The interlayer insulating film 9 is not formed.

  The source electrode 10 is formed on the source region 4 and the well contact portion 5 where the interlayer insulating film 9 is not formed. That is, the source electrode 10 is formed so as to cover the interlayer insulating film 9 and the well contact portion 5 and the source region 4 that are not covered by the interlayer insulating film 9. Source electrode 10 is electrically connected to source region 4 and well contact portion 5 exposed at the opening of interlayer insulating film 9. In order to reduce the contact resistance with the source electrode 10, n-type impurities are introduced into the source region 4 at a high concentration, and p-type impurities are introduced into the well contact portion 5 at a high concentration.

  Drain electrode 20 is formed on the surface of silicon carbide semiconductor substrate 1 opposite to the side on which drift layer 2 is formed.

  In the trench gate type MOSFET described above, in the well region 3 constituting the side surface of the trench 40, a region facing the gate electrode 8 through the gate insulating film 7 and in which an inversion layer is formed at the time of the on operation is referred to as a channel portion. Further, the distance between the drift layer 2 and the source region 4 in the portion including the channel portion in the portion sandwiched between the drift layer 2 and the source region 4 in the well region 3 is referred to as a channel length.

  In the first embodiment, the channel layer 6 is formed along the side surface of the trench 40 in the channel portion. More specifically, the channel layer 6 is formed only in the well region 3. The channel layer 6 is formed with the same thickness in the thickness direction of the trench 40. Here, the thickness of the channel layer 6 indicates the length in the direction perpendicular to the depth direction of the trench 40 (the left-right direction in FIG. 1). The channel layer 6 is formed by implanting an n-type impurity such as nitrogen (N) into the p-type well region 3 by oblique ion implantation (described later). The n-type impurity concentration of the channel layer 6 is constant in the thickness direction of the trench 40.

  Next, the operation of the trench gate type MOSFET according to the first embodiment will be briefly described.

  When a positive voltage equal to or higher than the threshold voltage (Vth) is applied to the gate electrode 8, an inversion channel is formed in the channel portion, and carriers are formed between the n-type source region 4 and the n-type drift layer 2. A path through which electrons flow is formed. Electrons flowing from source region 4 to drift layer 2 reach drain electrode 20 via drift layer 2 and silicon carbide substrate 1 in accordance with an electric field formed by a positive voltage applied to drain electrode 20. That is, a current flows from the drain electrode 20 to the source electrode 10 by applying a positive voltage to the gate electrode 8. This state is called an on state.

  The on-resistance of the trench gate type MOSFET can be reduced by lowering the resistance of the channel portion in the on state, but the resistance of the channel portion decreases as the channel length decreases and the mobility of electrons in the channel portion increases. Can be lowered. Here, since the channel layer 6 in contact with the gate insulating film 7 in the channel portion is n-type, it has a so-called buried channel structure. In the buried channel structure, carriers (electrons here) flow inside the channel layer 6 through a portion closer to the well region 3 than the gate insulating film 7. In a normal surface channel MOSFET, carriers flow through the interface between the gate insulating film and the channel semiconductor layer. However, since the buried channel structure is adopted in the first embodiment, the carriers are defects due to carbon in SiC. Since there is no flow in the vicinity of the gate insulating film 7 having a large amount, the mobility can be improved.

  Unlike the ON state, when a voltage lower than the threshold voltage is applied to the gate electrode 8, no inversion channel is formed in the channel portion, so that no current flows from the drain electrode 20 to the source electrode 10. This state is called an off state. Since the threshold voltage is a positive voltage, no current flows when 0 V is applied to the gate electrode 8. Therefore, the trench gate type MOSFET of the first embodiment is a so-called normally-off type transistor.

  In the off state, a depletion layer extends from the pn junction between the drift layer 2 and the well region 3 by a positive voltage applied to the drain electrode 20. When the depletion layer extending from the pn junction toward the well region 3 reaches the source region 4, punch-through breakdown occurs. The voltage when this punch-through breakdown occurs is the off breakdown voltage.

  In the first embodiment, the channel layer 6 is formed only in the well region 3. That is, the channel layer 6 does not extend to the drift layer 2. If the channel layer 6 extends to the drift layer 2, the n-type impurity concentration in that portion becomes high. Since electric field concentration occurs in a region where the impurity concentration is high, punch-through breakdown occurs at a lower electric field. In addition, when the impurity concentration is high, the depletion layer is prevented from growing, so that the parasitic capacitance increases. On the other hand, in the first embodiment, since the n-type channel layer 6 does not extend to the drift layer 2, the electric field at which punch-through breakdown occurs increases, that is, the off breakdown voltage increases. In addition, since the parasitic capacitance is small, high-speed switching operation is possible.

  In the first embodiment, the n-type impurity of the channel layer 6 is introduced by ion implantation. Since the impurity concentration by ion implantation is uniform, variation in MOSFET characteristics can be reduced.

  Next, a method for manufacturing a trench gate type MOSFET which is a semiconductor device according to the first embodiment will be described in order with reference to FIGS. 2 to 13 are cross-sectional views showing each manufacturing process of the trench gate type MOSFET.

First, as shown in FIG. 2, n-type drift layer 2 is epitaxially grown on silicon carbide semiconductor substrate 1 by a chemical vapor deposition (CVD) method. For silicon carbide semiconductor substrate 1, an n-type low-resistance silicon carbide semiconductor substrate having a 4H polytype is used. The concentration of the n-type impurity in the drift layer 2 is selected within the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ . The thickness (film thickness) of the drift layer 2 is selected within the range of 5 to 50 μm.

Next, a p-type impurity, for example, aluminum (Al) is ion-implanted into the surface portion of the drift layer 2 by an ion implantation method to form a p-type well region 3. At this time, the depth of ion implantation of the p-type impurity is set to a depth not exceeding the thickness dimension of the drift layer 2, specifically about 0.5 to 3 μm. The ion acceleration voltage is selected within a range of 100 to 500 kV. Further, the concentration of the ion-implanted p-type impurity, that is, the p-type impurity concentration in the well region 3 is selected within the range of 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ , and the n-type impurity concentration of the drift layer 2 is selected. Higher concentration. Of the drift layer 2, a region that becomes p-type in a region where p-type impurities are ion-implanted becomes the well region 3. The well region 3 may be formed by one ion implantation, or may be formed by performing ion implantation a plurality of times while changing the acceleration voltage. The well region 3 may be formed by epitaxial growth. Also in this case, the p-type impurity concentration and thickness dimension of the well region 3 are the same as those formed by ion implantation.

Next, as shown in FIG. 3, an n-type source region 4 is formed by ion-implanting an n-type impurity, for example, nitrogen (N), into the surface of the drift layer 2 through an implantation mask (not shown). Specifically, an n-type source region 4 is formed by ion-implanting an n-type impurity into a portion of the drift layer 2 that becomes the well region 3, that is, a part of the surface portion of the well region 3. The ion acceleration voltage is selected within the range of 50 to 200 kV. The depth of ion implantation of the n-type impurity is shallower than the thickness of the well region 3. Further, the concentration of the ion-implanted n-type impurity, that is, the n-type impurity concentration of the source region 4 is selected within the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the p-type impurity concentration of the well region 3 is set. Exceed. As described above, the n-type region among the regions into which the n-type impurity is implanted in the well region 3 of the drift layer 2 becomes the source region 4.

Next, a p-type well contact portion 5 is formed by ion-implanting a p-type impurity such as Al into the surface portion of the drift layer 2 via an implantation mask (not shown). Specifically, a p-type well contact portion 5 is formed by ion-implanting p-type impurities into a portion of the drift layer 2 that becomes the well region 3, that is, a part of the surface portion of the well region 3. . The ion acceleration voltage is selected within the range of 100 to 200 kV. Further, the depth of ion implantation of the p-type impurity is shallower than the thickness dimension of the well region 3. The concentration of the ion-implanted p-type impurity, that is, the p-type impurity concentration of the well contact portion 5 is selected within the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the p-type impurity concentration of the well region 3 is selected. Shall be exceeded.

  Next, as shown in FIG. 4, a silicon oxide layer 30 is deposited on the surface on which the source region 4 and well contact portion 5 shown in FIG. Thereafter, the silicon oxide layer 30 is patterned by photolithography and reactive ion etching (RIE) (not shown). As a result, the silicon oxide layer 30 is opened so that a predetermined portion for forming the trench 40 in the source region 4 is exposed. At this time, the etched silicon oxide layer 30 becomes an etching mask and an implantation mask used in a process described later.

  Next, using the silicon oxide layer 30 as a mask, silicon carbide is etched by RIE to form a trench 40 that penetrates the source region 4 and the well region 3. The depth of the trench 40 is set to about 0.5 to 3 μm so as to be not less than the depth of the well region 3. Specifically, the trench 40 is formed so as to penetrate the source region 4 and the well region 3 and reach the inside of the drift layer 2.

  Next, as shown in FIG. 5, an n-type impurity, for example, N is ion-implanted using the silicon oxide layer 30 as an implantation mask, thereby forming a channel layer 6. Specifically, the channel layer 6 is formed by implanting N ions obliquely from the opening of the silicon oxide layer 30 (opening of the trench 40) into the well region 3 on the exposed side wall of the trench 40. In the first embodiment, an n-type impurity is implanted only in the well region 3 to form the channel layer 6.

  The oblique ion implantation of the n-type impurity is performed as follows. As shown in FIG. 5, the sum of the opening width C of the trench 40 and the thicknesses of the silicon oxide layer 30, the source region 4, and the well region 3 (that is, the drift layer 2 and the well region 3 from the surface of the silicon oxide layer 30). And the ion implantation angle θ (angle with respect to the side surface of the trench 40) is calculated and determined by the following equation (1) to determine the silicon carbide semiconductor substrate 1 as the ion implantation angle. Tilt to θ.

θ = arctan (C / D) (1)
In FIG. 5, the ion beams 50 and 51 are shown to be inclined, but actually, the silicon carbide semiconductor substrate 1 is inclined to the ion implantation angle θ. The concentration of the ion-implanted n-type impurity, that is, the n-type impurity concentration of the channel layer 6 is approximately the same as or less than the p-type impurity concentration of the well region 3, and specifically, the MOSFET is normally off (Vth is positive). It is selected within the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ . The ion acceleration voltage is selected within a range of 10 to 50 kV. Here, since the ion implantation angle of the n-type impurity is θ, the n-type impurity is not implanted deeper than the well region 3 using the silicon oxide layer 30 as a mask. Thus, the channel layer 6 is formed only in the well region 3. As a matter of course, the n-type impurity is also implanted into the source region 4. However, since the implantation amount (concentration) is as low as 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ , the source region 4 is affected. Absent.

  The opening width C of the trench 40 and the sum D of the thicknesses of the silicon oxide layer 30, the source region 4, and the well region 3 are formed with variations. Also, there is a variation spreading in a direction perpendicular to the implantation direction, which is also called ion implantation spread. The implantation spread becomes larger as the impurity concentration is larger and the implantation energy is larger. Accordingly, the ion implantation angle θ is preferably determined in consideration of these variations. Specifically, this corresponds to an increase in variation in the opening width C of the trench 40, a decrease in variation in the sum D of the thicknesses of the silicon oxide layer 30, the source region 4, and the well region 3, and an increase in implantation spread. It is preferable to increase the ion implantation angle θ by the angle to be angled, that is, to shallowly implant the trench 40 in the depth direction.

  By performing the above ion implantation, the channel layer 6 is formed with a thickness of 30 to 80 nm (length in a direction perpendicular to the depth direction of the trench 40), depending on the angle of the oblique ion implantation. The Further, the impurity concentration in the depth direction of the channel layer 6 becomes uniform.

  Next, the oblique ion implantation will be described in more detail.

  Usually, the MOSFET well region 3, source region 4, well contact portion 5, and channel layer 6 surrounded by the trench 40 are square or rectangular in shape (hereinafter also referred to as the planar shape of the MOSFET cell). It has become. FIG. 14 shows a plan view in the case where the planar shape of the MOSFET cell is a square. In FIG. 14, silicon carbide semiconductor substrate 1, interlayer insulating film 9, source electrode 10, and drain electrode 20 are not shown in order to clearly display the lower structure. FIG. 15 is a cross-sectional view taken along the line AA shown in FIG.

  The MOSFET cell 80 is indicated by a dotted line in FIG. As shown in FIGS. 14 and 15, the channel layer 6 exists on the four sides of the square (MOSFET cell) in FIG. Therefore, the oblique ion implantation for forming the channel layer 6 must be performed for each of the four sides of the square. Specifically, as shown by a solid line arrow in FIG. 14, after ion implantation is performed with the ion beam 50 on the right side of the square (the right side on the paper in FIG. 14), the silicon carbide semiconductor substrate 1 is rotated by 90 °. Then, ion implantation by the ion beam 52 is performed on the lower side. Thereafter, similarly, the silicon carbide semiconductor substrate 1 is rotated by 90 ° to perform ion implantation with the ion beam 51 on the left side and ion implantation with the ion beam 53 on the upper side. By performing the ion implantation four times, the channel layer 6 is formed on all four sides of the square. 5 shows only the ion beam 50 for the right side and the ion beam 51 for the left side in FIG. Further, when the channel layer 6 is formed by ion implantation, the gate insulating film 7 and the gate electrode 8 shown in FIG. 14 do not exist.

When the planar shape of the MOSFET cell is rectangular, as is apparent from FIG. 14, n-type impurities are not implanted into the drift layer 2 on the side wall of the trench 40 by oblique ion implantation. An n-type impurity is implanted. The n-type impurity implanted into the bottom of the trench 40 is not preferable because it increases the n-type impurity concentration of the drift layer 2. Therefore, after the oblique ion implantation of the n-type impurity performed when forming the channel layer 6, the same amount of p-type impurity is subjected to vertical ion implantation (ion implantation from a direction perpendicular to the silicon carbide semiconductor substrate 1), thereby The increased n-type impurities on the bottom surface of the trench 40 are offset. Further, in a MOSFET having a high off breakdown voltage (for example, 1.2 kV or 3.3 kV), a p-type bottom well 31 is often separately provided on the bottom surface of the trench 40 as shown in FIG. Since the p-type impurity concentration of the bottom well 31 is as high as 1 × 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ , when the bottom well 31 is provided, the vertical ions of the additional p-type impurities as described above are used. No injection is necessary. 16 forms p-type impurities in the vertical direction (perpendicular to silicon carbide semiconductor substrate 1, that is, perpendicular to the bottom surface of trench 40) after formation of trench 40 shown in FIG. Are formed by ion implantation. Alternatively, the bottom well 31 may be formed by performing vertical ion implantation after oblique ion implantation of the channel layer 6. A method of not implanting n-type impurities into the bottom surface of the trench 40 will be described later (see Modification 6 described later).

  Returning to the description of each manufacturing process of the trench gate type MOSFET, as shown in FIG. 6 after FIG. 5, after removing the silicon oxide layer 30 used as a mask, the heat treatment apparatus is used to remove argon (Ar) gas or the like. Annealing is performed at 1300 to 1900 ° C. for 30 seconds to 1 hour in an active gas atmosphere. By this annealing, ion-implanted n-type impurity (channel layer 6) and p-type impurity (source region 4), for example, N and Al are activated.

  Next, as shown in FIG. 7, the surface portions of the source region 4, well contact portion 5, channel layer 6, and drift layer 2 are thermally oxidized to form a gate insulating film 7 having a desired thickness in the trench. 40 is formed inside. The gate insulating film 7 is also formed on the surfaces of the source region 4 and the well contact portion 5. In the first embodiment, the temperature of thermal oxidation is selected within the range of 1000 to 1300 ° C., and the thickness of the gate insulating film 7 is selected within the range of 30 to 100 nm. The gate insulating film 7 is not limited to thermal oxidation. For example, a silicon oxide film may be deposited by a CVD method, or a laminated film may be formed by thermal oxidation and a CVD method. Further, after the formation of the silicon oxide film, the surface of the silicon oxide film may be nitrided in an atmosphere such as a temperature of 1000 to 1300 ° C. and NO gas or N 2 gas.

Next, as shown in FIG. 8, a gate electrode film (gate electrode 8), for example, a polycrystalline silicon film having conductivity, is formed by CVD so as to be in contact with the gate insulating film 7 inside the trench 40. The gate electrode 8 is preferably deposited with a film thickness that completely fills the trench 40 from the viewpoint of reducing the resistance of the gate electrode 8, but even if it is not completely buried, there is no problem in the operation of the MOSFET. The gate electrode 8 (polycrystalline silicon film) contains 1 × 10 ^{20 to} 5 × 10 ²⁰ cm ⁻³ of phosphorus (P), and the conductivity of the gate electrode 8 is ensured by this large amount of phosphorus. ing. The gate electrode 8 is not limited to a polycrystalline silicon film, but a refractory metal film, a compound film of refractory metal and silicon (so-called metal silicide film), or a laminated film of a polycrystalline silicon film and a metal silicide film. It may be.

  Next, the gate electrode 8 other than the inside of the trench 40 is removed by patterning the gate electrode 8 by photolithography and RIE, and the gate electrode 8 is formed in the trench 40. Although not shown, the portion where the gate electrode 8 is connected to the external electrode is left as a gate electrode pad without etching the gate electrode 8 by photolithography.

  Next, as shown in FIG. 10, an interlayer insulating film 9 is formed so as to cover the surface portions of the gate insulating film 7 and the gate electrode 8. The interlayer insulating film 9 is formed with a silicon oxide layer having a thickness of 0.5 to 2.0 μm by a CVD method.

  Next, as shown in FIG. 11, the interlayer insulating film 9 is opened by etching so that the portion near the well contact portion 5 and the well contact portion 5 of the source region 4 are exposed by photolithography and RIE. In FIG. 11, the illustration of the gate insulating film 7 existing below the interlayer insulating film 9 is omitted.

Next, as shown in FIG. 12, source electrode 10 electrically connected is formed on the portion where source region 4 and well contact portion 5 are exposed, and further, as shown in FIG. 13, a silicon carbide semiconductor substrate is formed. 1 is formed by laminating the drain electrode 20 on the back surface of the silicon carbide semiconductor substrate 1 (on the side opposite to the side where the drift layer 2 is formed). Here, the source electrode 10 is made of Al or an alloy containing Al, and the drain electrode 20 is made of a laminated film such as nickel (Ni) or a silicide thereof (NiSi ₂ ) or gold (Au). Note that NiSi ₂ may be separately provided at the contact portion between the source electrode 10 and the source region 4 and well contact portion 5 to further reduce the contact resistance. Although not shown, when the source electrode 10 is patterned, an electrode such as Al is also provided on the gate electrode pad. Through the above manufacturing process, the vertical MOSFET shown in FIG. 1 is completed.

  From the above, according to the first embodiment, as shown in FIG. 5, the n-type impurity is ion-implanted by performing oblique ion implantation on the well region 3 on the side wall (side surface) of the trench 40. Thus, the channel layer 6 is formed. Further, since the channel layer 6 is n-type, carriers flow in the well region 3 side rather than the gate insulating film 7 side in the channel layer 6. Therefore, the carrier does not flow in the vicinity of the gate insulating film 7 where there are many defects due to carbon in SiC, so that the mobility can be improved. That is, the resistance of the channel portion can be reduced. Further, since the channel layer 6 is formed only in the well region 3 and does not extend to the drift layer 2, it is possible to suppress the deterioration of the off breakdown voltage and the generation of parasitic capacitance. Further, since the impurity concentration by ion implantation is uniform, variation in MOSFET characteristics can be reduced. Further, since the patterning by photolithography is unnecessary in the oblique ion implantation process, the channel layer 6 can be formed at a low cost. In the first embodiment, the channel layer 6 is formed using oblique ion implantation, so that an epitaxial growth step for forming the channel layer 6 is not necessary. Further, the semiconductor substrate to be used is not limited. Therefore, in the first embodiment, an excellent MOSFET can be easily manufactured as described above.

  In the first embodiment, the channel layer 6 is formed by the oblique ion implantation method using the silicon oxide layer 30 as a mask, but the silicon oxide layer 30 may be omitted. When there is no silicon oxide layer 30, n-type impurities are ion-implanted into the source region 4 and the surface of the well contact portion 5, but the concentration of the n-type impurity for forming the channel layer 6 is different from that of the source region 4. Since the n-type impurity concentration and the p-type impurity concentration of the well contact portion 5 are lower, the resistance of the source region 4 and the contact resistance between the well contact portion 5 and the source electrode 10 are not affected. If there is no silicon oxide layer 30, D in the above formula (1) needs to be the sum of the thicknesses of the source region 4 and the well region 3. The same applies to D in Formulas 2 and 5 in Modifications 1 and 2 to be described later.

  In the first embodiment, oblique ion implantation for forming the channel layer 6 is performed immediately after the formation of the trench 40. However, a thin insulating film, for example, a silicon oxide film having a thickness of 10 to 30 nm is formed inside the trench 40. A film may be formed, and oblique ion implantation may be performed through the thin insulating film. The thin insulating film may be formed by an oxidation method or a CVD method. When oblique ion implantation is performed through a thin insulating film, the thickness of the channel layer 6 and the n-type impurity concentration can be reduced. The thickness of the thin insulating film, the acceleration voltage of the oblique ion implantation, and the implantation amount (n-type impurity concentration) may be appropriately selected according to the performance specifications such as the threshold voltage (Vth) and on-resistance of the MOSFET. The thin insulating film is desirably removed after oblique ion implantation.

  Hereinafter, modifications 1 to 8 of the first embodiment will be described in order.

<Modification 1 (U-shaped trench)>
In the first embodiment, the trench 40 has a flat bottom surface, and the bottom surface and the side surface intersect perpendicularly. In this way, when the bottom surface and the side surface of the trench 40 intersect perpendicularly, if the gate insulating film 7 is formed by oxidation (oxidation treatment), a large stress is generated at the intersection between the bottom surface and the side surface, and The gate insulating film 7 becomes thin, and there is a problem that reliability is deteriorated. Normally, this problem is solved by raising the oxidation temperature. However, as shown in FIG. 17, a U-shaped trench 41 may be formed. In the U-shaped trench 41, since the side surface and the bottom surface do not intersect perpendicularly, the stress at the intersection is relaxed, and the film thickness of the gate insulating film 7 at the intersection is uniform.

  Further, as described in Patent Documents 2 and 3, when the channel layer is grown by epitaxial growth, there is a problem that the film thickness of the bottom surface of the trench becomes non-uniform. On the other hand, in the first embodiment, since the channel layer 6 is formed by the oblique ion implantation method, the channel layer 6 can be formed regardless of the shape of the bottom surface of the trench 40.

<Modification 2 (p-type gate)>
In the first embodiment, polycrystalline silicon doped with n-type impurities is used for the gate electrode 8, but the material of the gate electrode 8 is not limited to this.

FIG. 18 is a cross-sectional view of a MOSFET using polycrystalline silicon doped with p-type impurities as the gate electrode 8a. As shown in FIG. 18, the gate electrode 8a is polycrystalline silicon in which boron (B), which is a p-type impurity, is selectively introduced within a range of 2 × 10 ^{19 to} 3 × 10 ²⁰ cm ⁻³ .

  Next, a method for forming a polycrystalline silicon film doped with p-type impurities will be described.

  First, polycrystalline silicon containing no impurities is deposited by a CVD method.

  Next, B or BF2 ions are implanted at an acceleration voltage of 10 to 100 kV. For example, the depth (projection range) with the highest concentration when implanted at 100 kV is 0.3 μm for B and 0.07 μm for BF2, and reaches the polycrystalline silicon film at the bottom of the trench 40. Will not reach. Therefore, annealing at 800 to 1000 ° C. is performed. For example, the diffusion distance of B at a temperature of 900 ° C. and an annealing time of 30 minutes is about 1 μm. Therefore, the annealing temperature or time may be appropriately determined so that B diffuses to the bottom of the trench 40.

  Since the gate electrode 8a using the polycrystalline silicon film introduced with B formed as described above is p-type, the Fermi level is located on the valence band side, and the work function of the gate electrode 8a is n-type. It becomes larger than the work function of the electrode 8. Therefore, the work function difference between the gate electrode 8a and the channel layer 6 increases, and the threshold voltage Vth of the MOSFET increases. In the second modification, the threshold voltage Vth is 0.5 to 1.0 V higher than the Vth of the n-type gate electrode 8.

  From the above, in the second modification, p-type polycrystalline silicon is used for the gate electrode 8a, so that the threshold voltage Vth can be increased in addition to the effect of the first embodiment. In general, the threshold voltage Vth of a MOSFET decreases as the element temperature increases. On the other hand, in the second modification, normally-off characteristics are exhibited even at higher temperatures, and stable operation is possible.

<Modification 3 (forward taper trench)>
In Embodiment 1 described above, the sidewall (side surface) of trench 40 is formed to be perpendicular to the surface of silicon carbide semiconductor substrate 1, but the angle of the sidewall of the trench is not limited to be perpendicular.

  FIG. 19 shows a cross-sectional view when the angle of the sidewall of the trench is an acute angle (90 ° or less) with respect to the surface of silicon carbide semiconductor substrate 1. As shown in FIG. 19, the trench 42 has a forward tapered shape. That is, the shape of the trench 42 is a forward taper in which the distance between the opposing side surfaces of the trench 42 gradually decreases from the source region 4 toward the drift layer 2. In FIG. 19, only the silicon oxide layer 30, the source region 4, the well region 3, the trench 42, and the ion beam 50 are illustrated for simplicity.

In FIG. 19, oblique ion implantation of n-type impurities is performed as follows. Based on opening width E of trench 42, sum D of thicknesses of silicon oxide layer 30, source region 4, and well region 3, and angle φ formed by the sidewall of trench 42 and the surface of silicon carbide semiconductor substrate 1. Then, the ion implantation angle θ ₁ is calculated and determined by the following equation (2), and the silicon carbide semiconductor substrate 1 is tilted to the ion implantation angle θ ₁ .

θ ₁ = arctan ((ED / tanφ) / D) (2)
As described above, the channel layer 6 can be formed only in the well region 3 by ion-implanting n-type impurities at the ion implantation angle θ ₁ .

  From the above, according to the third modification, in addition to the same effects as those of the first embodiment, there is an effect that the gate electrode can be easily formed because the trench 42 has a forward taper. Specifically, the gate electrode can be deposited and formed not by CVD but also by sputtering.

  In addition, since the shape of the trench 42 is a forward taper, the depth is limited. The maximum taper depth X of the forward taper is obtained by the following equation (3).

X = Etanφ / 2 (3)
When the trench depth is X determined by the above equation (3), the bottom surface of the trench does not exist, and the trench shape is V-shaped. The trench shape in this state is shown by a dotted line in FIG. In the forward-tapered trench 42, the depth D to the bottom surface of the well region 3 (the interface between the well region 3 and the drift layer 2 (not shown)) must be set to be shallower than the maximum trench depth X. The condition is the following formula (4).

θ ₁ > 90−φ (4)
From the above, E, D, and φ must be selected so that θ ₁ satisfies the above equation (4).

  Hereinafter, specific examples (two) of the derivation method of the above formula (4) will be described.

  First, the first derivation method will be described.

As shown in FIG. 19, angle between the ion beam 50 and the semiconductor substrate surface is given by 90-θ _1. If this angle is not smaller than the taper angle φ of the trench, ions are implanted into the entire inner wall of the trench. Therefore, it is necessary to satisfy the condition of 90−θ ₁ <φ, that is, θ ₁ > 90−φ (the above formula (4)). In this way, the above equation (4) is derived.

  Next, the second derivation method will be described.

  Based on the equations (2) and (3) and the condition X> D, the following is derived.

From Equation (3), Etanφ / 2> D, that is,
E / 2> D / tanφ (5)
It becomes.

  If -1 is applied to both sides of the above equation (5), the inequality sign is reversed so that -E / 2 <-D / tanφ, and if E is added to both sides, EE / 2 <ED / tanφ is obtained. Further, when divided by D, E / 2D <(ED / tanφ) / D. Since tan is a monotonically increasing function, arctan is also a monotonically increasing function, so arctan (E / 2D) <arctan ((ED / tanφ) / D).

Also, from equation (2)
arctan (E / 2D) <θ ₁ (6)
And

From Equation (5), E / 2D> 1 / tanφ and 1 / tanφ = tan (90−φ), so that E / 2D> tan (90−φ). This results in the equation (6), arctan (tan ( 90-φ)) <arctan (E / 2D) < a theta _1. Therefore, 90−φ <arctan (E / 2D) <θ _{1 is established} , and the above equation (4) is derived.

<Example 4 (reverse taper trench)>
FIG. 20 shows a cross-sectional view when the angle of the sidewall (side surface) of the trench is an obtuse angle (90 ° or more) with respect to the surface of silicon carbide semiconductor substrate 1. As shown in FIG. 20, the trench 43 has a reverse taper shape. That is, the shape of the trench 43 is a reverse taper in which the distance between the opposing side surfaces of the trench 43 gradually increases from the source region 4 toward the drift layer 2. In FIG. 20, only the silicon oxide layer 30, the source region 4 and the well region 3, the trench 43, and the ion beam 50 are illustrated for simplicity.

In FIG. 20, oblique ion implantation of n-type impurities is performed as follows. Based on the opening width F of the trench 43, the sum D of the thicknesses of the silicon oxide layer 30, the source region 4 and the well region 3, and the angle ψ formed by the sidewall of the trench 43 and the surface of the silicon carbide substrate 1, Ion implantation angle θ ₂ is calculated and determined by the following equation (7), and silicon carbide semiconductor substrate 1 is tilted to ion implantation angle θ ₂ .

θ ₂ = arctan ((F + Dtan (ψ−90)) / D) (7)
As described above, the channel layer 6 can be formed only in the well region 3 by ion-implanting n-type impurities at the implantation angle θ ₂ .

  From the above, according to the fourth modification, in addition to the same effect as in the first embodiment, the trench 43 has an inverse taper, so that the area of the source region 4 and the well contact portion 5 is reduced. There is an effect that a large sum can be formed. Specifically, since the sum of the areas of the source region 4 and the well contact portion 5 in the MOSFET cell having the same area can be made larger than that in the first embodiment and the third modification, the source electrode 10 and The contact area is increased and the contact resistance is reduced.

<Modification 5 (trench planar shape)>
In the first embodiment, the planar shape of the MOSFET cell surrounded by the trench 40 has been described as a square or rectangular shape (see FIG. 14), but the planar shape of the MOSFET cell is not limited to a rectangular shape or a square shape.

  FIG. 21 shows a plan view of the MOSFET when the planar shape of the MOSFET cell surrounded by the trench 40 (gate electrode 8) is a hexagon. As shown in FIG. 21, one MOSFET cell 81 is indicated by a dotted line in FIG. In FIG. 21, silicon carbide semiconductor substrate 1, interlayer insulating film 9, source electrode 10, and drain electrode 20 are not shown in order to clearly show the lower structure. Further, the cross-sectional view along the line BB shown in FIG. 21 corresponds to FIG.

  As shown in FIG. 21, the channel layer 6 exists on each of the six sides of the hexagon. Therefore, the oblique ion implantation performed to form the channel layer 6 must be performed on each of the six sides of the hexagon. Specifically, as shown by a solid arrow in FIG. 21, after ion implantation is performed with an ion beam 54 on the upper side of the hexagon (the upper side of the drawing in FIG. 21), the silicon carbide semiconductor substrate 1 is moved to 60 °. The ion beam 55 is ion-implanted with respect to the upper right side of the hexagon. Thereafter, similarly, each of the silicon carbide semiconductor substrates 1 is rotated by 60 ° to perform ion implantation with the ion beam 56 for the lower right side, ion implantation with the ion beam 57 for the lower side, and ions with the ion beam 58 for the lower left side. Implantation and ion implantation with the ion beam 59 are performed on the upper left side. The channel layer 6 is formed on all six sides of the hexagon by these six ion implantations. Note that the gate insulating film 7 and the gate electrode 8 shown in FIG. 21 do not exist at the time of ion implantation performed to form the channel layer 6.

  As described above, the planar shape of the MOSFET cell is not limited, and a MOSFET cell having an arbitrary shape can be formed, not limited to a rectangle (square) or a hexagon. If oblique ion implantation is performed on each side forming the MOSFET cell, the channel layer 6 is formed.

  From the above, according to the fifth modification, in addition to the same effects as in the first embodiment, the channel layer 6 can be made to coincide with an arbitrary crystal plane. Specifically, for example, 4H polytype silicon carbide has a hexagonal crystal structure and a 6-fold symmetric crystal. Therefore, if the planar shape of the MOSFET cell is a regular hexagon, the channel layer is formed on all six sides. 6 is, for example, a (11-20) plane with less interface states (more precisely, a (1, 1, 2 bar, 0) plane, which is a physically equivalent plane, ie, (-12-10). ), (-2110), (2-1-10), (-1-120), (1-210)), and the mobility of the MOSFET can be further improved. Further, the channel layer 6 is formed on a crystal plane having a low surface density of crystal defects, for example, a (1-100) plane (or a plane equivalent thereto, that is, (10-10), (01-10), (-1100), ( −1010) and (0-110)), the yield can be improved.

<Modification 6 (Avoiding Trench Bottom Injection)>
In the first embodiment, the planar shape of the trench 40 is a square (the same applies to a rectangle), and an n-type impurity is implanted into the bottom surface of the trench 40. However, if the ion implantation direction with respect to the planar shape of the MOSFET cell is selected (see FIG. 14), it is possible to prevent the n-type impurity from being implanted into the bottom surface of the trench 40.

  As shown in FIG. 14, if n-type impurity ions are implanted from the direction of dotted arrows 50 a, 51 a, 52 a, and 53 a in the figure, the n-type impurity is not implanted into the bottom surface of the trench 40. At this time, the ion implantation angle θ when the side wall of the trench 40 is vertical can be obtained by substituting SQRT (2) C in place of C in the above equation (1). Here, SQRT (2) indicates the square root of 2. Similarly, when the sidewall of the trench 40 is forward tapered (the shape of the trench 40 is forward tapered), SQRT (2) E may be substituted for E in the above equation (2). Further, when the sidewall of the trench 40 is reversely tapered (the shape of the trench 40 is reversely tapered), SQRT (2) F may be substituted for F in the above equation (7).

  Generally, the ion implantation direction with respect to the plane of the MOSFET cell when performing oblique ion implantation is a direction perpendicular to the longitudinal direction of the trench 40, that is, the width direction of the trench 40 (direction in which the side surface of the trench 40 extends). If the direction is not parallel to the n-type impurity, no n-type impurity is implanted into the bottom surface of the trench 40. This is because the size of the normal MOSFET cells 80 and 81 is about 10 μm, whereas the width of the trench 40 is as narrow as 1 to 1.5 μm. When ion implantation is performed on the hexagonal MOSFET cell of FIG. 21 from the directions of arrows 55 to 59, n-type impurities are not implanted into the bottom of the trench.

  From the above, according to the sixth modification, in addition to the same effect as in the first embodiment, the n-type impurity is not implanted into the bottom surface of the trench 40. Therefore, it is not necessary to introduce a p-type impurity for compensation into the bottom surface of the trench 40, and the number of processes can be reduced. When the p-type bottom well 31 is separately provided on the bottom surface of the trench 40 (see FIG. 16), there is no need to increase the concentration of the p-type impurity for compensation, and the p-type bottom well 31 is formed. The required ion implantation time is shortened. The same effects as those of the fourth modification can be obtained in the third and fourth modifications.

<Modification 7 (channeling avoidance)>
As described above, the shape of the trench and its taper angle can be freely selected. That is, an arbitrary crystal plane can be selected as the crystal plane of the sidewall of the trench, and the above formulas (1), (2), (5) are selected based on the opening width of the trench and the depth to the bottom surface of the well region. ) To determine the ion implantation angle θ, θ ₁ , or θ ₂ . When the ion implantation angle with respect to the crystal face of the sidewall of the trench reaches a specific value, a phenomenon occurs in which the implanted n-type impurity ions cause channeling and are implanted deeper than the set value. Hereinafter, channeling of a vertical trench will be described as an example.

In FIG. 5, the (1-100) plane (or an equivalent plane) is selected as the sidewall of the trench 40, the opening width C of the trench 40 is 1.0 μm, the silicon oxide layer 30, the source region 4, and the well region. When the sum D of the thicknesses of 3 is 1.4 μm, the ion implantation angle is about 35.54 ° (more precisely, 35.26 ° when D is 1.41 μm). Wake up. Thus, when channeling occurs depending on the selected crystal plane and ion implantation angle, channeling can be performed by changing the value of the opening width C and the sum of the thicknesses of the source region 4 and the well region 3 (values related to D). It goes without saying that the ion implantation angle that does not occur can be determined, but it is more preferable to change the thickness of the silicon oxide layer 30. This is because the opening width C and the thicknesses of the source region 4 and well region 3 are related to the performance of the MOSFET and cannot be freely changed. On the other hand, since the film thickness of the silicon oxide layer 30 is related only to the opening of the trench 40 and the oblique ion implantation process, it is more flexible to change the film thickness of the silicon oxide layer 30. In the above example, when the thickness of the silicon oxide layer 30 is changed so that the sum D of the thicknesses of the silicon oxide layer 30, the source region 4, and the well region 3 becomes 1.25 μm or 1.60 μm, θ becomes 38.66 ° or 32.01 °, and channeling can be avoided. Generally, when the sum D of the thicknesses of the silicon oxide layer 30, the source region 4, and the well region 3 is changed by 10%, the ion implantation angle θ (or θ ₁ , θ ₂ ) changes by about 3 °, and channeling is avoided. Enough angle to do. That is, channeling can be avoided if the ion implantation angle is different by 3 ° or more from the angle at which channeling occurs with respect to the side surface of the trench.

  The ion implantation angle (35.26 °) that causes channeling will be described below with reference to FIGS.

  FIG. 27 is a plan view of a hexagonal crystal as viewed from above. In FIG. 27, only Si atoms are shown, and C atoms are not shown. Si atoms are shown in large size for easy understanding of the arrangement. The atoms in the first layer are indicated by white circles, and the atoms in the second layer are indicated by hatched circles. The third layer atom is not shown because it is located immediately above the first layer atom.

  As shown in FIG. 27, broken line arrows a1, a2, and a3 indicate unit cell vectors. The solid line arrow is a line connecting the center of the first layer atom 1 and the center of the second layer atom 2. A line perpendicular to the direction in which the direction of the solid arrow is projected onto the plane (included in the plane) is a thick broken line. The crystal plane including the broken line and perpendicular to the plane is the (10-10) plane. Channeling occurs when ions are implanted from this plane in the direction opposite the solid arrow.

  FIG. 28 is a diagram showing a vertical arrangement of atom 1 in the first layer and atom 2 in the second layer in FIG. The solid arrow shown in FIG. 28 corresponds to the solid arrow shown in FIG. Further, the broken line in FIG. 28 corresponds to the thick broken line in FIG. A plane that includes a broken line and is perpendicular to the plane of the drawing (broken line in FIG. 28) indicates a (10-10) plane.

In FIG. 28, an angle θ ₃ (an angle causing channeling) formed by a line (solid arrow) connecting the center of atom 1 of the first layer and the center of atom 2 of the second layer is θ ₃ = 54.74. ° (= arccos (1 / SQRT (3)), where Y = a / SQRT (3), and the interatomic distance is a, and the coordinates of the center of atom 2 are (a / 2, SQRT (3) a / 6), the center of atom 1 = the origin, x on the right side of the page and y on the top of the page). Therefore, since the ion implantation angle is 90−θ ₃ , the ion implantation angle = 35.26 °.

From the above, according to the present modified example 7, in addition to the same effect as in the first embodiment, channeling in ion implantation of n-type impurities can be easily avoided. The same applies to Modifications 3 to 6 described above.

<Modification 8 (Trench Formation Mask Shape)>
In the first embodiment, the silicon oxide layer 30 is used for etching the trenches 40 to 43 and as a mask for oblique ion implantation. The silicon oxide layer 30 was formed so that its cross-sectional shape had the same taper angle as that of the trenches 40 to 43. In the case of oblique ion implantation, when viewed from the direction of the ion beam, the film thickness of the edge portion of the silicon oxide layer 30 is thin, and the edge portion cannot sufficiently block the implantation of ions into the sidewall of the trench 40. That is, even if the ion implantation angle θ (or θ ₁ , θ ₂ ) is determined in consideration of the edge portion of the silicon oxide layer 30, the channel layer 6 (channel layer 6) in the region of about 50 nm below the well region 3. In this case, in the region of about 50 nm from the interface between the drift layer 2 and the well region 3 to the well region 3 side, the amount of ion implantation is reduced.

  FIG. 22 is a cross-sectional view of the silicon carbide semiconductor device during ion implantation, and corresponds to FIG. As shown in FIG. 22, the silicon oxide layer 32 from which the edge portion has been removed is formed. That is, the thickness of the silicon oxide layer 32 is smaller on the opening side than on the non-opening side. Thus, by removing the thin portion of the edge portion of the silicon oxide layer 32, the channel layer 6 can be formed at a uniform concentration up to the lower side of the well region 3.

The silicon oxide film 32 from which the edge portion has been removed is formed by changing the mixing ratio of the etching gas during etching by RIE. Specifically, in the etching gases trifluoromethane (CHF ₃ ) and O ₂ , the edge portion of the silicon oxide film 32 is removed by increasing the flow rate of O ₂ . The etching gas is not limited to CHF ₃ and O ₂ , and may be carbon tetrafluoride (CF ₄ ) and O ₂ . The angle of the ion implantation 50 is determined in consideration of the shape of the silicon oxide film 32 from which the edge portion has been removed.

    From the above, according to the present modification 8, since the edge portion of the silicon oxide layer 32 is removed, the channel layer 6 can be formed with a more uniform concentration in addition to the same effect as in the first embodiment, and the MOSFET The variation in characteristics can be further suppressed.

<Embodiment 2>
In Embodiment 1, the channel layer is formed only in the well region by the oblique ion implantation method, but the method of forming the channel layer only in the well region is not limited to the oblique ion implantation method.

  23 to 26 are cross-sectional views by process showing a method of manufacturing a trench gate type MOSFET which is a semiconductor device according to the second embodiment of the present invention. The MOSFET according to the second embodiment is a silicon carbide semiconductor device, like the MOSFET according to the first embodiment. Note that, in the MOSFET according to the second embodiment, the same components as those of the MOSFET according to the first embodiment are denoted by the same reference numerals, and common description is omitted.

  About the manufacturing method of MOSFET by this Embodiment 2, it manufactures by the process (FIGS. 2-4) same as the manufacturing method of MOSFET by Embodiment 1 until the stage which the formation of the trench 40 is complete | finished.

  Next, as shown in FIG. 23, a resist 70 is formed on the entire surface. The resist 70 is formed thick so as to completely fill the trench 40 and to have a flat surface.

Next, as shown in FIG. 24, the resist 70 is etched so that it remains only at the bottom of the trench 40. The resist 71 is obtained by anisotropically etching the resist 70 by the RIE method using O ₂ as an etching gas. The thickness of the resist 71 is formed so that the outermost surface of the resist 71 coincides with the lowermost surface of the well region 3. That is, the resist 71 is formed on the bottom surface of the trench 40 so that the top surface is flush with the boundary surface between the drift layer 2 and the well region 3.

Next, as shown in FIG. 25, plasma treatment is performed with a gas containing nitrogen. Plasma treatment is performed at a temperature of 100 to 200 ° C., a pressure of 50 to 400 Pa, an RF (Radio Frequency) frequency of 13.56 MHz, an RF power of ^{2 to 20} W / cm ² , an N 2 gas flow rate of 500 to 1000 sccm, and a treatment time of 10 to 60 minutes. Select with. By this plasma treatment, nitrogen atoms are introduced into the side walls of the trench 40 to form the channel layer 61. At this time, since the resist 71 is formed at the bottom of the trench 40, nitrogen is not introduced into the drift layer 2.

  Next, as shown in FIG. 26, after the plasma processing, the resist 71 is removed.

  Thereafter, a MOSFET is formed by the same process (FIGS. 6 to 13) as in the first embodiment.

From the above, the channel layer 61 is formed by plasma treatment. In plasma treatment, nitrogen is not introduced as deeply as ion implantation. In the second embodiment, for example, when the plasma treatment is performed under the conditions of a temperature of 100 ° C., a pressure of 200 Pa, an RF power of 10 W / cm ² , an N 2 gas flow rate of 500 sccm, and a treatment time of 30 minutes, the thickness of the obtained channel layer 61 is obtained. A channel layer having a uniform n-type impurity concentration of 10 nm and an n-type impurity concentration of 2 × 10 ¹⁶ cm ⁻³ was obtained. Although the thickness of the channel layer 61 is thinner than the thickness by the ion implantation method, the mobility of the MOSFET is improved and the on-resistance is reduced. The gas to be introduced is not limited to N 2 gas. The same effect can be obtained if the gas contains nitrogen and does not erode the resist 71, such as ammonia (NH3) gas.

  From the above, according to the second embodiment, since the channel layer 6 is formed only in the well region 3 by plasma processing, the on-resistance is reduced, the off-breakdown voltage is high, and the parasitic capacitance is small, so that high speed is achieved. MOSFETs capable of switching operations can be formed by a simpler process than ion implantation. In addition, since the n-type impurity concentration of the channel layer 6 is uniform, variation in MOSFET characteristics can be reduced.

  In the embodiment of the present invention, the case where the semiconductor element is a vertical MOSFET is disclosed. For example, the silicon carbide (SiC) semiconductor substrate 1 shown in FIG. 1, FIG. 17, FIG. Even if a semiconductor element having an IGBT cell region with a conductivity type of the second conductivity type (p-type) is configured, the same effect as described above can be obtained. Therefore, the scope of the present invention is a semiconductor element as a switching element having a MOS structure such as MOSFET or IGBT.

  In the above description, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. The unit of the angle shown in the embodiment of the present invention is degree (°).

  In the embodiment of the present invention, silicon carbide is used as a semiconductor, but the semiconductor is not limited to silicon carbide. Other than silicon carbide, for example, gallium nitride (GaN) can be used. When gallium nitride is used, silicon (Si) may be introduced into the channel portion as an n-type impurity.

  Further, within the scope of the invention, the present invention can be freely combined with each other, or can be appropriately modified or omitted.

  The present invention is suitable for application to a power converter such as an inverter.

  1 Silicon carbide semiconductor substrate, 2 drift layer, 3 well region, 4 source region, 5 well contact portion, 6 channel layer, 7 gate insulating film, 8, 8a gate electrode, 9 interlayer insulating film, 10 source electrode, 20 drain electrode , 30 silicon oxide layer, 31 bottom well, 32 silicon oxide layer, 40-43 trench, 50-59 ion beam, 50a-53a ion beam, 61 channel layer, 70, 71 resist, 80, 81 MOSFET cell.

Claims (16)

A semiconductor substrate;
A first conductivity type drift layer formed on the semiconductor substrate;
A second conductivity type well region formed on the surface of the drift layer;
A first conductivity type source region formed on the surface of the well region;
A well contact region of a second conductivity type formed in a surface portion of the well region and a region different from the source region;
A trench formed in a predetermined region of the source region so that at least a bottom surface is exposed by the drift layer;
A channel layer of a first conductivity type formed along the side surface of the trench in the well region;
A gate insulating film formed to cover the bottom and side surfaces of the trench;
A gate electrode formed on the gate insulating film so as to fill the trench;
An interlayer insulating film formed to cover the gate electrode, the gate insulating film, and a part of the source region;
A source electrode formed to cover the interlayer insulating film and the well contact region and the source region that are not covered by the interlayer insulating film;
A drain electrode formed on the opposite side of the semiconductor substrate from which the drift layer is formed;
With
The semiconductor device according to claim 1, wherein the channel layer is formed only between the drift layer and the source region, and the impurity concentration of the first conductivity type of the channel layer is uniform overall.   The semiconductor device according to claim 1, wherein the channel layer is formed by ion implantation into the well layer from an oblique direction with respect to a side surface of the trench.   The semiconductor device according to claim 1, wherein the shape of the trench is U-shaped.   4. The semiconductor device according to claim 1, wherein the gate electrode includes second conductivity type polycrystalline silicon. 5.   5. The channel layer according to claim 1, wherein a surface along a side surface of the trench is a (11-20) plane or a crystal plane equivalent to the (11-20) plane. A semiconductor device according to 1.   5. The channel layer according to claim 1, wherein a plane along a side surface of the trench is a (1-100) plane or a crystal plane equivalent to the (1-100) plane. 6. A semiconductor device according to 1.   The shape of the trench is a forward taper in which a distance between opposing side surfaces of the trench gradually decreases from the source region toward the drift layer. A semiconductor device according to claim 1.   The shape of the trench is a reverse taper in which a distance between opposing side surfaces of the trench is gradually increased from the source region toward the drift layer. A semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon carbide semiconductor substrate. (A) forming a first conductivity type drift layer on a semiconductor substrate;
(B) forming a second conductivity type well region on the drift layer;
(C) forming a first conductivity type source region on the surface of the well region;
(D) forming a mask on the source region so that a predetermined region becomes an opening;
(E) forming a trench through the source region and the well region so that at least the drift layer is exposed at a bottom surface in the opening;
(F) introducing a first conductivity type impurity from the opening into only the source region and the well region on the side surface of the trench;
(G) forming a gate insulating film so as to cover the bottom surface and the side surface of the trench;
(H) forming a gate electrode on the gate insulating film so as to fill the trench;
A method for manufacturing a semiconductor device. In the step (f),
The impurity is ion-implanted at an angle with respect to a side surface of the trench determined based on an opening width of the trench and a length from a surface of the mask to a boundary surface between the drift layer and the well region. The method of manufacturing a semiconductor device according to claim 10, wherein In the step (f),
The impurity according to claim 11, wherein the impurity is ion-implanted from a direction in which a side surface of the trench extends and a direction in which the direction of the ion implantation is projected on the semiconductor substrate. A method for manufacturing a semiconductor device. In the step (f),
13. The method of manufacturing a semiconductor device according to claim 11, wherein an angle of the ion implantation differs by 3 ° or more from an angle at which channeling occurs with respect to a side surface of the trench. In the step (d),
14. The method of manufacturing a semiconductor device according to claim 10, wherein the film thickness of the mask is smaller on the opening side than on the non-opening side. The step (f)
(I) forming a resist on the bottom surface of the trench so that an upper surface is flush with a boundary surface between the drift layer and the well region;
(J) performing a plasma treatment using a gas containing nitrogen as an impurity on the side surface from the opening of the trench;
15. The method of manufacturing a semiconductor device according to claim 10, further comprising:   The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor substrate is a silicon carbide semiconductor substrate.

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