JP6651801B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

  Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device for controlling a high voltage or a large current. There are a plurality of types of power semiconductor devices, such as a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor: an insulated gate bipolar transistor), and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: an insulated gate field effect transistor). Have been.

  For example, a bipolar transistor or an IGBT has a higher current density than a MOSFET and can increase the current, but cannot perform high-speed switching. Specifically, the use of a bipolar transistor at a switching frequency of about several kHz is the limit, and the use of an IGBT at a switching frequency of about several tens kHz is the limit. On the other hand, the power MOSFET has a lower current density than the bipolar transistor and the IGBT, and it is difficult to increase the current, but a high-speed switching operation up to about several MHz is possible.

  In the market, there is a strong demand for a power semiconductor device having both a large current and a high speed, and IGBTs and power MOSFETs have been focused on improvement. At present, development is progressing almost to the material limit. For this reason, a semiconductor material that can replace silicon from the viewpoint of a power semiconductor device is being studied. (SiC) has attracted attention (for example, see Non-Patent Document 1 below).

  Silicon carbide is a very chemically stable semiconductor material, has a wide band gap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. In addition, silicon carbide is expected to be a semiconductor material capable of sufficiently reducing on-resistance because the maximum electric field strength is at least one order of magnitude higher than that of silicon. Such features of silicon carbide similarly apply to other semiconductors such as gallium nitride (GaN) having a wider band gap than silicon (hereinafter, referred to as a wide band gap semiconductor). Therefore, by using a wide band gap semiconductor, it is possible to increase the breakdown voltage of a semiconductor device (for example, see Non-Patent Document 2 below).

  In such a high breakdown voltage semiconductor device, a high voltage is applied not only to an active region in which an element structure is formed and a current flows in an on state, but also to an edge termination region surrounding the active region and maintaining a breakdown voltage, The electric field concentrates on the edge termination region. The breakdown voltage of a high breakdown voltage semiconductor device is determined by the impurity concentration, the thickness, and the electric field strength of the semiconductor, and the breakdown strength determined by the inherent characteristics of the semiconductor is equal from the active region to the edge termination region. For this reason, an electric load exceeding the breakdown strength may be applied to the edge termination region due to the electric field concentration in the edge termination region, and the edge termination region may be damaged. That is, the breakdown voltage of the high breakdown voltage semiconductor device is limited by the breakdown strength in the edge termination region.

  Devices that improve the breakdown voltage of the high-voltage semiconductor device as a whole by relaxing or dispersing the electric field in the edge termination region include a junction termination extension (JTE) structure and a field limiting ring (FLR) structure. A device in which a withstand voltage structure such as described above is arranged in an edge termination region is known (for example, see Patent Documents 1 and 2 below). Further, in Patent Document 1 below, a floating metal electrode in contact with the FLR is arranged as a field plate (FP: Field Plate) to discharge electric charges generated in an edge termination region, thereby improving reliability.

A withstand voltage structure of a conventional high withstand voltage semiconductor device will be described using a MOSFET having a JTE structure as an example. FIG. 5 is a sectional view showing the structure of a conventional semiconductor device. The conventional semiconductor device shown in FIG. 5 includes a semiconductor substrate 140 made of silicon carbide (hereinafter, referred to as a silicon carbide substrate (semiconductor chip)) 140, an active region 110, an edge termination region 120 surrounding the active region 110, Is provided. Silicon carbide base 140 is formed on an n ⁺ -type support substrate (hereinafter, referred to as an n ⁺ -type silicon carbide substrate) 101 made of silicon carbide, on an n ^- type semiconductor layer (hereinafter, n ⁻ ) made of silicon carbide. And a p-type semiconductor layer 104 made of silicon carbide (hereinafter referred to as a p-type silicon carbide layer) 104.

In active region 110, a MOS gate (insulating gate made of metal-oxide film-semiconductor) structure is provided on the front surface (surface on the side of p-type silicon carbide layer 104) of silicon carbide substrate 140. The p-type silicon carbide layer 104 is removed over the entire area of the edge termination region 120, and a step 121 in which the edge termination region 120 is lower than the active region 110 (concave toward the drain side) is formed on the front surface of the silicon carbide substrate 140. The n ⁻ -type silicon carbide layer 102 is formed on the bottom surface 121 a of the step 121 and is exposed. The edge termination region 120 includes a plurality of p ⁻ -type low-concentration regions (two in this case, p ⁻ -type and p ⁻ -type from the inside) in which the impurity concentration is lowered as being located on the outside (chip end side). JTE structures 130 are provided adjacent to each other.

The p ⁻ -type low-concentration region (hereinafter, referred to as a first JTE region) 131 and the p ⁻ -type low-concentration region (hereinafter, referred to as a second JTE region) 132 are formed of the step 121 of the n ⁻ -type silicon carbide layer 102, respectively. It is selectively provided at a portion exposed on the bottom surface 121a. The first JTE region 131 is in contact with the outermost p-type base region 103 on the bottom surface 121a of the step 121. Drain electrode 115 is provided in contact with the back surface of silicon carbide substrate 140 (the back surface of n ⁺ -type silicon carbide substrate 101). Reference numerals 105 to 109 and 111 to 114 denote an n ⁺ -type source region, a p ⁺ -type contact region, an n-type JFET region, a gate insulating film, a gate electrode, a field oxide film, an interlayer insulating film, a source electrode, and a passivation film, respectively. .

In the MOSFET having the configuration shown in FIG. 5, when a voltage lower than the threshold voltage is applied to the gate electrode 109 while a positive voltage is applied to the drain electrode 115 with respect to the source electrode 113, the p-type base region Since the pn junction between 104 a and n-type JFET region 107 is in a reverse-biased state, the reverse breakdown voltage of the active region is ensured and no current flows. The p-type base region 104a is a portion of the p-type silicon carbide layer 104 other than the n ⁺ -type source region 105 and the p ⁺ -type contact region 106.

On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 109, an n-type inversion layer (channel) is formed on the surface layer of the p-type base region 104a just below the gate electrode 109 (drain side). You. Thereby, a current flows through the path of n ⁺ type silicon carbide substrate 101, n ⁻ type silicon carbide layer 102, n type JFET region 107, surface inversion layer of p type base region 104a, and n ⁺ type source region 105. Thus, by controlling the gate voltage, a well-known switching operation of the MOSFET can be performed.

In the MOSFET having the configuration shown in FIG. 5, when a voltage is applied, a depletion layer extends outward from a pn junction between p-type base region 103 and the n ⁻ -type drift layer, and the first and second JTEs. It extends to both areas 131 and 132. The n ⁻ -type drift layer is a portion of the n ⁻ -type silicon carbide layer 102 other than the p-type base region 103 and the first and second JTE regions 131 and 132. The breakdown voltage in the edge termination region is ensured by the pn junction between the first and second JTE regions 131 and 132 and the n ⁻ -type drift layer.

Further, as another high withstand voltage semiconductor device, a groove reaching the n ⁻ -type drift region penetrating in the depth direction an outer end (edge end region side) of the p-type base region extending from the active region to the edge end region. There has been proposed a device having a breakdown voltage structure in which the inside of the device is embedded with an insulating film (for example, see Patent Document 3 (FIG. 13)). In Patent Document 3 below, an n-type channel stopper is provided at the boundary between the n ⁻ -type drift region and the insulating film at the bottom surface of the groove provided in the edge termination region, and the p-type base is provided along the inner wall of the groove. The region and the n-type channel stopper are connected.

JP 2010-50147 A JP 2006-165225 A US Patent Application Publication No. 2014/167143

K. Shenai (K. Shenai), two others, Optium Semiconductors for High-Power Electronics, I Triple E Transactions on Electronics Devices (IEE). September, Vol. 36, No. 9, p. 1811-1823 B. Jayant Baliga, Silicon Carbide Power Devices, (USA), World Scientific Publishing Company, World Scientific Publishing Co., March 30, 200 . 61

However, in the withstand voltage structures disclosed in Patent Documents 1 and 2, the width of the edge termination region 120 (the length from the boundary between the active region 110 and the edge termination region 120 to the chip end) is as long as 100 μm or more. There is a problem that the size becomes large. Further, in the withstand voltage structure disclosed in Patent Document 3, an n-type channel stopper is provided at the boundary of the n ⁻ -type drift region with the insulating film at the bottom of the groove and cut at that location. Therefore, there is a problem that the pressure-resistant structure must be determined only by the side surfaces of the groove.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a highly reliable breakdown voltage structure without increasing the chip size and a method of manufacturing the semiconductor device, in order to solve the above-described problems caused by the conventional technology.

In order to solve the problems described above and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. An active region through which a main current flows and a termination region surrounding the active region are provided on a semiconductor substrate of a first conductivity type made of a semiconductor having a band gap wider than that of silicon. The termination region includes a plurality of second conductivity type semiconductor regions provided in concentric circles surrounding the periphery of the active region and having a lower impurity concentration as being located outside, and a front surface of the semiconductor substrate. And an insulating film buried inside the groove. The outermost second conductivity type semiconductor region of the plurality of second conductivity type semiconductor regions is provided along the inner wall of the groove and covers the insulating film. A step is formed on the front surface of the semiconductor substrate so that the terminal region is lower than the active region. The trench and the second conductivity type semiconductor region are provided on a surface formed in the terminal region by the step.

  Further, in the semiconductor device according to the present invention, in the above-mentioned invention, a first semiconductor region of a second conductivity type is selectively provided on the front surface side of the semiconductor substrate in the active region. The first semiconductor region extends to a surface formed in the terminal region by the step, and contacts the innermost second conductivity type semiconductor region of the plurality of second conductivity type semiconductor regions. And

Further, a semiconductor device according to the present invention has the following features in the above-described invention. A fourth semiconductor region of the second conductivity type is provided to cover the first semiconductor region. A second semiconductor region of the first conductivity type is selectively provided inside the fourth semiconductor region . A gate insulating film is provided in contact with a region of the fourth semiconductor region between the second semiconductor region and the semiconductor substrate. A gate electrode is provided on the opposite side of the fourth semiconductor region with the gate insulating film interposed therebetween. The first electrode is in contact with the fourth semiconductor region and the second semiconductor region. The second electrode is in contact with the back surface of the semiconductor substrate.

  Further, a semiconductor device according to the present invention has the following features in the above-described invention. A trench penetrating the second semiconductor region and the first semiconductor region and reaching the semiconductor substrate is provided. A trench gate structure in which the gate electrode is provided inside the trench via the gate insulating film is provided. A third semiconductor region of the second conductivity type covering the bottom surface of the trench is provided.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the semiconductor having a wider band gap than silicon is silicon carbide.

  Further, in order to solve the above-described problems and achieve the object of the present invention, the method of manufacturing a semiconductor device according to the present invention is provided on a semiconductor substrate of a first conductivity type made of a semiconductor having a wider band gap than silicon. A method for manufacturing a semiconductor device including an active region and a termination region surrounding the periphery of the active region has the following features. First, a first step of forming a groove provided on the front surface of the semiconductor substrate in the termination region is performed. Next, a second step of forming a plurality of second conductive semiconductor regions provided concentrically surrounding the periphery of the active region and having a lower impurity concentration as being disposed on the outer side is performed. Next, a third step of burying an insulating film in the trench is performed. In the second step, first, a first forming step of forming the outermost second conductivity type semiconductor region of the plurality of second conductivity type semiconductor regions along the inner wall of the groove is performed. Next, an insulating film mask is formed on the front surface of the semiconductor substrate, with an opening in a portion corresponding to a formation region of another second conductivity type semiconductor region among the plurality of second conductivity type semiconductor regions. A second forming step is performed. Next, using the insulating film mask as a mask, a third forming step of forming the another second conductivity type semiconductor region by ion implantation is performed. In the third step, after the third forming step, a portion of the insulating film mask other than a portion embedded inside the groove is removed, and the insulating film mask remaining inside the groove is replaced with the insulating film. And

  Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, after the first forming step, one or more element structures constituting an element structure are formed on a surface layer of a front surface of the semiconductor substrate in the active region. The method further includes a fourth step of selectively forming the diffusion region. In the fourth step, a fourth forming step of forming another insulating film mask having an opening corresponding to a region where the diffusion region is formed on the front surface of the semiconductor substrate; As a mask, a fifth forming step of forming the diffusion region by ion implantation as a set is repeated as many times as the number of the diffusion regions. In the third step, every time the fourth step is performed, a portion of the other insulating film mask other than a portion embedded inside the groove is removed, and the other insulating film remaining inside the groove is removed. The mask is the insulating film, and the inside of the groove is completely filled with the insulating film.

  According to the above-described invention, when a voltage is applied, the depletion layer extending from the active region side extends to the plurality of second conductivity type semiconductor regions, so that concentration of an electric field in the active region can be suppressed. According to the invention described above, the outermost second conductivity type semiconductor region is provided along the inner wall of the groove, and the insulating film is buried inside the groove, so that when the voltage is applied, An electric field can be shared between the conductive semiconductor region and the insulating film inside the trench. Thus, a high withstand voltage can be maintained with a withstand voltage structure of about several μm constituted by the JTE structure and the insulating film inside the trench. In addition, since the electric field is shared between the second conductivity type semiconductor region and the insulating film inside the trench, the electric field in the second conductivity type semiconductor region is reduced, and the breakdown voltage distribution in the termination region can be stabilized.

  ADVANTAGE OF THE INVENTION According to the semiconductor device and the manufacturing method of a semiconductor device concerning this invention, there exists an effect that the reliable withstand voltage structure which ensured the stable withstand voltage distribution can be realized, without enlarging a chip size.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device according to the first embodiment; FIG. 5 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment; FIG. 13 is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment; FIG. 4 is a characteristic diagram illustrating a breakdown voltage characteristic of the semiconductor device according to the example. FIG. 11 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

  Preferred embodiments of a semiconductor device and a method of manufacturing the semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, a layer or a region with an n or p prefix means that electrons or holes are majority carriers, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region to which they are not added. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and overlapping description will be omitted. In the present specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after, and a negative index is indicated by adding "-" before the index.

(Embodiment 1)
A semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the first embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described using a planar gate MOSFET as an example. FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment. As shown in FIG. 1, the silicon carbide semiconductor device according to the first embodiment includes a semiconductor substrate (hereinafter, referred to as a silicon carbide substrate (semiconductor substrate (semiconductor chip))) 40 made of silicon carbide, an active region 10, And an edge termination region 20 surrounding the periphery of the active region 10. The active region 10 is a region where a current flows when in the ON state. The edge termination region 20 is a region that relaxes the electric field on the substrate front surface side of the drift region and maintains the breakdown voltage.

Silicon carbide base 40 includes n ⁻ type semiconductor layer (n ⁻ type silicon carbide layer) 2 made of silicon carbide on n ⁺ type support substrate (n ⁺ type silicon carbide substrate) 1 made of silicon carbide. And a p-type semiconductor layer (p-type silicon carbide layer) 4 made of silicon carbide. N ⁺ type silicon carbide substrate 1 functions as a drain region. In active region 10, a p-type base region (first semiconductor region) is formed in a surface layer of n ⁻ -type silicon carbide layer 2 on the side opposite to n ⁺ -type silicon carbide substrate 1 (front side of the base). 3) is provided selectively. The outermost (chip end side) p-type base region 3 extends from the active region 10 side to a bottom surface 21 a of a step 21 described later, and a part thereof is exposed to the bottom surface 21 a of the step 21. The bottom surface 21 a of the step 21 is a front surface of the silicon carbide substrate 40 newly formed in the edge termination region 20 by forming the step 21. Exposure to the bottom surface 21a of the step 21 means that it is arranged so as to be in contact with a field oxide film 11 described later. A portion of n ⁻ -type silicon carbide layer 2 other than p-type base region 3 and first and second JTE regions 31 and 32 described later is a drift region.

P-type silicon carbide layer 4 is provided on surface of n ⁻ -type silicon carbide layer 2 opposite to n ⁺ -type silicon carbide substrate 1 so as to cover p-type base region 3. The impurity concentration of p-type silicon carbide layer 4 may be lower than the impurity concentration of p-type base region 3. Within p-type silicon carbide layer 4, n ⁺ -type source region (second semiconductor region) 5 and p ⁺ -type contact region 6 are selectively provided at a portion facing p-type base region 3 in the depth direction. Is provided. Further, inside p-type silicon carbide layer 4, n-type semiconductor region 7 penetrating p-type silicon carbide layer 4 in the depth direction and reaching n ⁻ -type silicon carbide layer 2 is provided. n-type semiconductor region 7 is disposed apart from the n ⁺ -type source region 5 with respect to the n ⁺ -type source region 5 to the opposite side of the p ⁺ -type contact region 6.

A portion 4a of the p-type silicon carbide layer 4 other than the n ⁺ -type source region 5, the p ⁺ -type contact region 6 and the n-type semiconductor region 7 (hereinafter, referred to as a second p-type base region (first semiconductor region)) The p-type base region (hereinafter, referred to as a first p-type base region) 3 functions as a base region. An n-type semiconductor region (hereinafter, referred to as an n-type JFET region) 7 is a JFET (junction FET) region sandwiched between adjacent base regions, and functions as a drift region together with the n ⁻ -type silicon carbide layer 2. By making the impurity concentration of n-type JFET region 7 interposed between adjacent base regions higher than the impurity concentration of n ⁻ -type silicon carbide layer 2, the JFET resistance is reduced.

Of the 2p-type base region 4a, on a surface of a portion held with n ⁺ -type source region 5 and the n-type JFET region 7, a gate insulating film 8 over the n-type JFET region 7 of n ⁺ -type source region 5 A gate electrode 9 is provided through the gate electrode 9. The first and second p-type base regions 3 and 4a, the n ⁺ -type source region 5, the p ⁺ -type contact region 6, the gate insulating film 8, and the gate electrode 9 are formed on the front surface of the silicon carbide substrate 40 (p-type silicon carbide). On the layer 4 side), a MOS gate structure is formed. The source electrode (first electrode) 13 is in contact with the n ⁺ type source region 5 and the p ⁺ type contact region 6 and is electrically insulated from the gate electrode 9 by the interlayer insulating film 12.

The p-type silicon carbide layer 4 is removed over the entire area of the edge termination region 20, and a step 21 in which the edge termination region 20 is lower than the active region 10 (concave toward the drain side) is formed on the front surface of the silicon carbide substrate 40. Is formed. That is, n ⁻ type silicon carbide layer 2 is exposed on bottom surface 21 a of step 21. The side wall 21 b of the step 21 is located, for example, at the boundary between the active region 10 and the edge termination region 20. The side wall 21b of the step 21 is located between the bottom surface 21a of the step 21 and the front surface of the substrate closer to the active region 10 than the step 21 and has an oblique angle θ with respect to the bottom surface 21a of the step 21. This is a front surface of the silicon carbide substrate 40 having a degree. The side wall 21 b of the step 21 may be located slightly closer to the edge termination region 20 than the boundary between the active region 10 and the edge termination region 20. P-type silicon carbide layer 4 is exposed on side wall 21b of the step. When the depth of step 21 is deeper than the thickness of p-type silicon carbide layer 4, p-type silicon carbide layer 4 and first p-type base region 3 are exposed on side wall 21 b of step 21.

A boundary 21c between the bottom surface 21a and the side wall 21b of the step 21 (hereinafter, referred to as a bottom corner portion of the step 21) is closer to the drain than the boundary between the p-type silicon carbide layer 4 and the outermost first p-type base region 3. In addition, it is located at a depth position that does not penetrate the outermost first p-type base region 3. That is, the bottom corner 21 c of the step 21 is covered at least on the drain side by the outermost first p-type base region 3. Grooves 22 are selectively provided in a portion of n ⁻ -type silicon carbide layer 2 exposed on bottom surface 21 a of step 21 at a depth that does not reach n ⁺ -type silicon carbide substrate 1 in the depth direction. The groove 22 is arranged apart from the bottom corner 21 c of the step 21. The steps 21 and the grooves 22 are arranged in a substantially annular planar layout surrounding the periphery of the active region 10.

In the edge termination region 20, a plurality of p ⁻ -type low-concentration regions (second conductivity type semiconductor regions: two in this case, p from the inside (the active region 10 side), ^- type, p ^- JTE structure 30 is provided with a mold and to reference numeral 31, 32) arranged adjacently. JTE structure 30 is arranged in a substantially annular planar layout surrounding the periphery of active region 10. The p ⁻ -type low-concentration region (hereinafter, referred to as a first JTE region) 31 is disposed between the bottom corner 21 c of the step 21 and the groove 22, separated from the bottom corner 21 c of the step 21 and the groove 22, and It is exposed on the bottom surface 21a of the step 21. The first JTE region 31 is in contact with the outermost first p-type base region 3 on the bottom surface 21 a of the step 21.

The p ⁻ -type low concentration region (hereinafter, referred to as a second JTE region) 32 is provided along the inner wall (side wall and bottom surface) of the groove 22 and is exposed on the entire inner wall of the groove 22. The second JTE region 32 is in contact with the first JTE region 31 at a portion provided along the inner side wall of the groove 22. Second JTE region 32 has a predetermined thickness t2 so as not to be in contact with n ⁺ -type silicon carbide substrate 1 at a portion provided along the bottom surface of groove 22. The thickness t2 of the second JTE region 32 may be smaller than the thickness t1 of the first JTE region 31 (t2 <t1). The first and second JTE regions 31, 32 are arranged in a concentric planar layout. An insulating film 33 is embedded in the groove 22. That is, the insulating film 33 is covered with the second JTE region 32.

  The first and second JTE regions 31 and 32 and the insulating film 33 form a withstand voltage structure in the edge termination region 20. The breakdown voltage of the edge termination region 20 is set by variously changing the depth d of the groove 22 and the impurity concentration of the second JTE region 32. Specifically, the breakdown voltage of the edge termination region 20 increases as the depth d of the groove 22 increases. For example, when the depth d of the groove 22 is about 1 μm, the withstand voltage of the edge termination region 20 is about 1200 V. The withstand voltage of the edge termination region 20 increases as the impurity concentration of the second JTE region 32 decreases. As the depth d of the groove 22 increases, the withstand voltage of the edge termination region 20 can be increased by the impurity concentration of the second JTE region 32.

For example, when the depth d of the groove 22 is about 1 μm, as described above, the withstand voltage of the edge termination region 20 is about 1200 V, and the withstand voltage difference of the edge termination region 20 due to the impurity concentration of the second JTE region 32 hardly occurs. . On the other hand, for example, when the depth d of the groove 22 is about 6 μm, when the impurity concentration of the second JTE region 32 is 1.50 × 10 ¹⁶ / cm ³ , the withstand voltage of the edge termination region 20 is about 1600 V or more. On the other hand, when the impurity concentration of the second JTE region 32 is set to 6.00 × 10 ¹⁶ / cm ³ , the breakdown voltage of the edge termination region 20 exceeds 2200 V. The width w (width between the inner and outer side walls) of the groove 22 may be, for example, about 5 μm.

On the front surface of silicon carbide substrate 40 in edge termination region 20, interlayer insulating film 12 extends from active region 10 and covers first and second JTE regions 31 and 32 and insulating film 33. Field oxide film 11 may be provided between front surface of silicon carbide substrate 40 and interlayer insulating film 12 in edge termination region 20. In addition, a protective film 14 made of, for example, polyimide such as a passivation film is provided on the interlayer insulating film 12 in the edge termination region 20. The protective film 14 has a function of preventing discharge. The protection film 14 may extend on the end of the source electrode 13. Drain electrode 15 is provided on the back surface of silicon carbide substrate 40 (the back surface of n ⁺ type silicon carbide substrate 1).

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described by taking, as an example, a case of manufacturing a MOSFET of a withstand voltage class of 1200 V, for example. First, a silicon carbide single crystal n ⁺ -type silicon carbide substrate (semiconductor wafer) 1 doped with an n-type impurity (dopant) such as nitrogen (N) so as to have an impurity concentration of 2.0 × 10 ¹⁹ / cm ³ , for example. Prepare The front surface of n ⁺ type silicon carbide substrate 1 may be, for example, a (000-1) surface having an off angle of about 4 degrees in the <11-20> direction. Next, n ⁻ -type silicon carbide layer 2 doped with an n-type impurity such as nitrogen so as to have an impurity concentration of, for example, 1.0 × 10 ¹⁶ / cm ³ is formed on the front surface of n ⁺ -type silicon carbide substrate 1. Is epitaxially grown to a thickness of, for example, 10 μm.

Next, first p-type base region 3 is selectively formed in the surface layer of n ⁻ -type silicon carbide layer 2 by photolithography and ion implantation. In this ion implantation, a p-type impurity (dopant) such as aluminum (Al) may be implanted such that the impurity concentration of the first p-type base region 3 is, for example, 1.0 × 10 ¹⁸ / cm ³ . For example, the first p-type base region 3 may be arranged in a stripe-shaped planar layout, and its width (stripe width) and depth may be set to 13 μm and 0.5 μm, respectively. Next, a p-type silicon carbide layer 4 in which a surface of n ⁻ -type silicon carbide layer 2 is doped with a p-type impurity such as aluminum so as to have an impurity concentration of, for example, 2.0 × 10 ¹⁶ / cm ³ is, for example, 0.1 μm. Epitaxial growth with a thickness of 5 μm.

Through the steps so far, silicon carbide substrate 40 having n ⁻ -type silicon carbide layer 2 and p-type silicon carbide layer 4 sequentially laminated on the front surface of n ⁺ -type silicon carbide substrate 1 is manufactured. Next, the n-type JFET region 7 is selectively formed by inverting a part of the conductivity type of the p-type silicon carbide layer 4 by photolithography and ion implantation. In this ion implantation, an n-type impurity such as nitrogen may be implanted so that the impurity concentration of the n-type JFET region 7 becomes, for example, 5.0 × 10 ¹⁶ / cm ³ . The width and depth of n-type JFET region 7 may be, for example, 2.0 μm and 0.6 μm, respectively. The n-type JFET region 7 may be formed after forming a second JTE region 32 described later.

Next, a step 21 is formed at a depth of, for example, 0.7 μm on the front surface of silicon carbide substrate 40 by photolithography and etching, and p-type silicon carbide layer 4 is removed over the entire edge termination region 20. The n ^- type silicon carbide layer 2 is exposed. Next, groove 22 is selectively formed in the portion of n ⁻ -type silicon carbide layer 2 exposed on bottom surface 21 a of step 21 by photolithography and etching. Next, the second JTE region 32 is formed along the inner wall of the groove 22 by photolithography and ion implantation. Ion implantation for forming second JTE region 32 includes, for example, ion implantation from a direction oblique to the front surface of silicon carbide substrate 40 and ion implantation from a direction orthogonal to the front surface of silicon carbide substrate 40. May be combined.

Next, a process of forming an ion implantation mask by photolithography and etching, ion implantation using the ion implantation mask, and removing the ion implantation mask as one set is repeatedly performed under different ion implantation conditions. Thus, the first JTE region 31, the n ⁺ -type source region 5, and the p ⁺ -type contact region 6 are formed. The order in which the first JTE region 31, the n ⁺ -type source region 5 and the p ⁺ -type contact region 6 are formed can be variously changed. As an ion implantation mask used for ion implantation for forming the first JTE region 31, the n ⁺ type source region 5 and the p ⁺ type contact region 6, for example, an insulating film (insulating film mask) is used. The thickness of the insulating film serving as the ion implantation mask may be, for example, about 1.5 μm. Then, when removing the ion implantation mask, a portion embedded in the groove 22 of the ion implantation mask is left without being removed. The ion implantation mask remaining inside the groove 22 becomes the insulating film 33. It is preferable to set the thickness of each ion implantation mask so that the total thickness of the ion implantation mask for each ion implantation is such that the inside of the groove 22 can be completely filled with the insulating film 33.

Next, heat treatment (annealing) for activating the first p-type base region 3, the n ⁺ -type source region 5, the p ⁺ -type contact region 6, the n-type JFET region 7, and the first and second JTE regions 31, 32 is performed, for example. This is performed at a temperature of about 1620 ° C. for about 2 minutes. Next, for example, the front surface of silicon carbide substrate 40 is thermally oxidized by heat treatment at a temperature of about 1000 ° C. in a mixed gas atmosphere of oxygen (O ₂ ) gas and hydrogen (H ₂ ) gas, for example, about 100 nm. The gate insulating film 8 is formed to have a thickness of 10 nm. Thereby, the entire front surface of silicon carbide substrate 40 is covered with gate insulating film 8.

Next, a polysilicon (poly-Si) layer doped with, for example, phosphorus (P) is formed on the gate insulating film 8. Next, the polysilicon layer is patterned and selectively removed to leave a portion of the second p-type base region 4a on the surface between the n ⁺ -type source region 5 and the n-type JFET region 7. . The polysilicon layer remaining on the gate insulating film 8 becomes the gate electrode 9. The polysilicon layer serving as the gate electrode 9 may be left over the surface of the portion of the second p-type base region 4a between the n ⁺ -type source region 5 and the n-type JFET region 7 and over the n-type JFET region 7. Good.

Next, an interlayer insulating film 12 made of, for example, phosphor glass (PSG) having a thickness of, for example, 1.0 μm is formed on the entire front surface of the silicon carbide substrate 40 so as to cover the gate electrode 9. (Form. Next, the interlayer insulating film 12 and the gate insulating film 8 are patterned by photolithography and etching to form a contact hole, exposing the n ⁺ type source region 5 and the p ⁺ type contact region 6. After formation of gate electrode 9 and before formation of interlayer insulating film 12, field oxide film 11 may be formed on the front surface of silicon carbide substrate 40 in edge termination region 20.

  Next, the interlayer insulating film 12 is flattened by heat treatment (reflow). Next, source electrode 13 is formed on the front surface of silicon carbide substrate 40 by, for example, a sputtering method so as to be embedded in the contact hole. Next, the source electrode 13 is patterned by photolithography and etching. The thickness of the source electrode 13 may be, for example, 5 μm. The material of the source electrode 13 may be, for example, aluminum (Al-Si) containing silicon (Si) at a rate of 1%.

Next, a nickel (Ni) film, for example, is formed as drain electrode 15 on the back surface of silicon carbide substrate 40 (the back surface of n ⁺ -type silicon carbide substrate 1). Then, an ohmic junction between drain electrode 15 and silicon carbide substrate 40 is formed by heat treatment at a temperature of, for example, 970 ° C. Next, on the surface of the nickel film, for example, a titanium (Ti) film, a nickel film, and a gold (Au) film are sequentially formed as the drain electrode 15. Next, protective film 14 is formed on the front surface of silicon carbide substrate 40. Thereafter, silicon carbide substrate 40 is cut (diced) into chips and singulated, whereby the MOSFET shown in FIG. 1 is completed.

As described above, according to the first embodiment, by arranging the JTE structure in the edge termination region, when a voltage is applied, the pn between the p-type base region and the n ⁻ -type drift layer is reduced. A depletion layer extending from the junction spreads over a plurality of JTE regions constituting the JTE structure. Therefore, the depletion layer can be expanded in the edge termination region earlier than when the JTE structure is not disposed in the edge termination region, and the concentration of the electric field in the active region can be suppressed. According to the first embodiment, the second JTE region is provided along the inner wall of the groove and the insulating film is embedded in the groove, so that when a voltage is applied, the second JTE region is formed in the insulating film inside the groove. A potential is transmitted from the region, and an electric field can be shared between the first and second JTE regions and the insulating film inside the trench. Thus, a high withstand voltage can be maintained with a withstand voltage structure of about several μm constituted by the JTE structure and the insulating film inside the trench. That is, a high withstand voltage can be realized, and an increase in chip size can be prevented. In addition, since the electric field is shared between the first and second JTE regions and the insulating film inside the trench, the electric field in the first and second JTE regions is reduced, and the breakdown voltage distribution in the edge termination region can be stabilized. Therefore, it is possible to obtain a highly reliable withstand voltage structure that secures a stable withstand voltage distribution without increasing the chip size. According to the first embodiment, the breakdown voltage structure including the JTE structure and the insulating film in the trench is arranged in the edge termination region, and when a voltage is applied, the outermost unit cell ( By causing an avalanche current (a current that rapidly increases due to the avalanche) to flow through the MOSFET in the functional unit of the element, avalanche can be reliably generated in the active region. As a result, the electric field in the edge termination region is reduced, and a stable breakdown voltage distribution can be maintained. Further, according to the first embodiment, since the n-type region such as the n-type channel stopper region is not provided along the inner wall of the groove as in Patent Document 3, for example, the withstand voltage is obtained by using the side and bottom surfaces of the groove. The structure can be configured.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 2 is a cross-sectional view illustrating the structure of the semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is obtained by applying the semiconductor device according to the first embodiment to a trench gate type MOSFET.

Specifically, as shown in FIG. 2, in the second embodiment, silicon carbide substrate 40 is formed by stacking n ⁻ -type silicon carbide layer 2 on the front surface of n ⁺ -type silicon carbide substrate 1. . A p-type base region 41 is provided on a surface layer of n ⁻ -type silicon carbide layer 2 opposite to n ⁺ -type silicon carbide substrate 1. A portion of n ⁻ -type silicon carbide layer 2 other than p-type base region 41 and first and second JET regions 31 and 32 is a drift region. The p-type base region 41 extends from the active region 10 side to the bottom surface 21 a of the step 21, and a part thereof is exposed on the bottom surface 21 a of the step 21. The p-type base region 41 is in contact with the first JET region 31 on the bottom surface 21a of the step 21. The impurity concentration of the p-type base region 41 may be, for example, the same as the impurity concentration of the first p-type base region of the first embodiment.

Inside the p-type base region 41, an n ⁺ -type source region 42 and a p ⁺ -type contact region 43 are selectively provided. Trench 44 penetrating n ⁺ -type source region 42 and p-type base region 41 and reaching n ⁻ -type silicon carbide layer 2 is provided. A gate insulating film 45 is provided inside the trench 44 along the inner wall of the trench 44, and a gate electrode 46 is provided inside the gate insulating film 45. The p-type base region 41, the n ⁺ -type source region 42, the p ⁺ -type contact region 43, the trench 44, the gate insulating film 45, and the gate electrode 46 form a trench gate type MOS gate structure. The depth of the step 21 is smaller than the thickness of the p-type base region 41, for example. The withstand voltage structure of the edge termination region 20 is the same as the withstand voltage structure of the first embodiment.

In the method for manufacturing a semiconductor device according to the second embodiment, a trench gate type MOS gate structure may be formed in the method for manufacturing a semiconductor device according to the first embodiment. At this time, the p-type base region 41 may be formed before the step 21 is formed, or may be formed after the step 21 is formed. The first JTE region 31, the n ⁺ -type source region 42, and the p ⁺ -type contact region 43 may be formed after the formation of the second JTE region 32, and the order of formation may be variously changed. Trench 44, gate insulating film 45, and gate electrode 46 are formed by a general method after forming n ⁻ -type silicon carbide layer 2 and before forming interlayer insulating film 12, for example.

  As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained.

(Embodiment 3)
Next, the structure of the semiconductor device according to the third embodiment will be described. FIG. 3 is a cross-sectional view illustrating the structure of the semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment is different from the semiconductor device according to the second embodiment in that a p-type region (third semiconductor region) 47 is provided so as to cover the bottom surface of the trench 44 forming the MOS gate structure. It is. Specifically, p-type region 47 is selectively provided inside n ⁻ -type silicon carbide layer 2 so as to cover the bottom surface of trench 44 and apart from p-type base region 41. The p-type region 47 may be provided from the bottom surface to the bottom corner of the trench 44 so as to cover the boundary between the bottom surface and the side wall of the trench 44 (the bottom corner of the trench).

  The method for manufacturing a semiconductor device according to the third embodiment may include a step of forming a p-type region 47 added to the method for manufacturing a semiconductor device according to the second embodiment. Specifically, for example, after the formation of the trench 44 and before the formation of the gate insulating film 45, p is applied from a direction perpendicular to the front surface of the silicon carbide substrate 40 by using an etching mask for forming the trench 44. The p-type region 47 may be formed by ion-implanting a type impurity.

  As described above, according to the third embodiment, the same effects as those of the first and second embodiments can be obtained. Further, according to the third embodiment, when the present invention is applied to a trench gate type MOS gate structure, it is possible to prevent an electric field from being concentrated on the bottom surface or the bottom corner of the trench constituting the MOS gate structure. it can. This can prevent the breakdown voltage of the active region from being reduced.

(Example)
Next, the width w and the depth d of the groove 22 were verified. FIG. 4 is a characteristic diagram illustrating withstand voltage characteristics of the semiconductor device according to the example. 4, the horizontal axis indicates the depth d of the groove 22, and the vertical axis indicates the withstand voltage of the edge termination region 20. 4 shows the impurity concentration (second JTE concentration) of the second JTE region 32. According to the structure of the semiconductor device according to the first embodiment described above, a plurality of MOSFETs having different depths d of the grooves 22 and different impurity concentrations in the second JTE region 32 were manufactured (hereinafter, referred to as examples). In the embodiment, the JTE structure 30 is a double zone JTE structure including the first and second JTE densities 31 and 32. The width w of the groove 22 was 5 μm. The depth d of the groove 22 is variously changed in the range of 1 μm to 6 μm. The impurity concentration of the second JTE region 32 is variously changed in the range of 1.50 × 10 ¹⁶ / cm ^{3 to} 6.00 × 10 ¹⁶ / cm ³ . FIG. 4 shows the results of measuring the breakdown voltage of the edge termination region 20 in these samples.

  From the results shown in FIG. 4, it was confirmed that the breakdown voltage of the edge termination region 20 can be increased as the depth d of the groove 22 is increased. It was also confirmed that the lower the impurity concentration of the second JTE region 32, the higher the breakdown voltage of the edge termination region 20 could be. It was confirmed that as the depth d of the groove 22 was increased, the breakdown voltage of the edge termination region 20 due to the impurity concentration of the second JTE region 32 was increased.

  In the above, the present invention is not limited to the above-described embodiments, but can be variously modified without departing from the spirit of the present invention. For example, in each of the above-described embodiments, a MOSFET is described as an example. However, the present invention is not limited to the above-described embodiment, and can be applied to semiconductor devices having various element structures such as a bipolar transistor and an IGBT. The dimensions of each part, the impurity concentration, and the like are variously set according to required specifications and the like. Further, in each of the above-described embodiments, the case where two JTE regions are arranged adjacent to each other is described as an example of the configuration of the JTE structure. JTE regions may be arranged adjacent to each other. In this case, the outermost JTE region may be provided along the inner wall of the groove. As the number of JTE regions increases, the chip size increases, but the electric field concentration in each JET structure is alleviated. For this reason, it is preferable that the number of JTE regions is set as small as possible to achieve a desired breakdown voltage of the edge termination region.

  Further, the present invention has the same effect in a semiconductor device using another wide band gap semiconductor such as gallium nitride (GaN) or a semiconductor device using silicon. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is similarly applicable to a case where the first conductivity type is p-type and the second conductivity type is n-type. Holds.

  As described above, the semiconductor device and the method of manufacturing the semiconductor device according to the present invention are useful for a semiconductor device used as a switching device, and are particularly suitable for a vertical MOSFET using a wide band gap semiconductor.

Reference Signs List 1 n ⁺ -type silicon carbide substrate 2 n ^-- type silicon carbide layer 3, 4a, 41 p-type base region 4 p-type silicon carbide layer 5, 42 n ⁺ -type source region 6, 43 p ⁺ -type contact region 7 n-type JFET region 8, 45 Gate insulating film 9, 46 Gate electrode 10 Active region 11 Field oxide film 12 Interlayer insulating film 13 Source electrode 14 Protective film 15 Drain electrode 20 Edge termination region 21 Step 21a Step bottom 21b Side wall 21c Step bottom corner Part 22 groove 30 JTE structure 31 first JTE region (p ^- type low concentration region)
32 2nd JTE region (p ^- type low concentration region)
Reference Signs List 33 insulating film 40 silicon carbide base 44 trench 47 p-type region d groove depth t1 thickness of first JTE region t2 thickness of second JTE region w groove width

Claims (7)

An active region through which a main current flows, provided on a semiconductor substrate of a first conductivity type made of a semiconductor having a band gap wider than silicon;
A termination region surrounding the periphery of the active region;
With
The termination region is
A plurality of second-conductivity-type semiconductor regions provided concentrically around the periphery of the active region, and provided with a lower impurity concentration as being disposed outside;
A groove provided on the front surface of the semiconductor substrate,
An insulating film embedded in the groove,
The outermost of the second conductivity type semiconductor region of the plurality of the second conductivity type semiconductor region is provided along the inner wall of the groove, not covered with the insulating film,
A step having the terminal region lower than the active region is formed on the front surface of the semiconductor substrate,
The semiconductor device, wherein the groove and the second conductivity type semiconductor region are provided on a surface formed in the terminal region by the step . In the active region, a first semiconductor region of a second conductivity type is selectively provided on a front surface side of the semiconductor substrate,
The first semiconductor region extends to a surface formed in the terminal region by the step, and contacts the innermost second conductivity type semiconductor region of the plurality of second conductivity type semiconductor regions. 2. The semiconductor device according to claim 1, wherein: A fourth semiconductor region of a second conductivity type provided so as to cover the first semiconductor region;
A second semiconductor region of a first conductivity type selectively provided inside the fourth semiconductor region;
A gate insulating film provided in contact with a region of the fourth semiconductor region between the second semiconductor region and the semiconductor substrate ;
A gate electrode provided on the opposite side of the fourth semiconductor region across the gate insulating film;
A first electrode in contact with the fourth semiconductor region and the second semiconductor region;
A second electrode in contact with the back surface of the semiconductor substrate;
The semiconductor device according to claim 2, further comprising: A trench reaching the semiconductor substrate through the second semiconductor region and the first semiconductor region;
A trench gate structure in which the gate electrode is provided inside the trench via the gate insulating film,
A third semiconductor region of a second conductivity type covering a bottom surface of the trench;
The semiconductor device according to claim 3, further comprising: The semiconductor device according to claim 1, wherein the semiconductor having a wider band gap than silicon is silicon carbide. A method of manufacturing a semiconductor device, comprising: an active region provided on a semiconductor substrate of a first conductivity type made of a semiconductor having a wider band gap than silicon; and a termination region surrounding a periphery of the active region.
A first step of forming a groove on the front surface of the semiconductor substrate in the termination region;
A second step of forming a plurality of second conductivity type semiconductor regions provided in a concentric manner surrounding the periphery of the active region and having a lower impurity concentration as being disposed outside;
A third step of burying an insulating film inside the groove;
Including
In the second step,
A first forming step of forming the outermost second conductivity type semiconductor region of the plurality of second conductivity type semiconductor regions along an inner wall of the groove ;
After the first forming step, an insulating portion having an opening in a front surface of the semiconductor substrate, a portion corresponding to another forming region of the second conductive type semiconductor region among the plurality of second conductive type semiconductor regions. A second forming step of forming a film mask;
A third forming step of forming the other second conductivity type semiconductor region by ion implantation using the insulating film mask as a mask,
In the third step, after the third forming step, a portion of the insulating film mask other than a portion embedded in the groove is removed, and the insulating film mask remaining in the groove is replaced with the insulating film. A method of manufacturing a semiconductor device. After the first forming step, the method further includes a fourth step of selectively forming one or more diffusion regions constituting an element structure in a surface layer on the front surface of the semiconductor substrate in the active region,
In the fourth step,
A fourth forming step of forming another insulating film mask having an opening at a portion corresponding to the formation region of the diffusion region on the front surface of the semiconductor substrate;
Using the other insulating film mask as a mask, a fifth forming step of forming the diffusion region by ion implantation is repeated as many as the number of the diffusion regions.
In the third step, every time the fourth step is performed, a portion of the other insulating film mask other than a portion embedded inside the groove is removed, and the other insulating film remaining inside the groove is removed. 7. The method according to claim 6, wherein a mask is used as the insulating film, and the inside of the groove is completely filled with the insulating film.

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