JP2017073525A - Nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device capable of achieving lower on-resistance.SOLUTION: A nitride semiconductor device comprises an ntype region 20 having a low resistance value on a lateral face of a gate structure part 6. This causes a carrier not only in a bottom layer formed by a GaN layer 2 and an AlGaN layer 3 but also a carrier in an upper layer to be carried from a lower part of the gate structure part 6 to the opposite side through the ntype region 20. Accordingly, an electron current can be carried in a 2DEG layer of each group to achieve reduction in on-resistance.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a nitride semiconductor device using a nitride semiconductor such as gallium nitride (hereinafter referred to as GaN).

  Conventionally, Patent Document 1 discloses a technique for realizing normally-off and low on-resistance in a nitride semiconductor device having a plurality of channels. Specifically, a natural super junction structure (hereinafter referred to as an NSJ structure) is formed by repeatedly forming a heterojunction of an AlGaN layer and a GaN layer on the GaN layer. A first gate structure portion that reaches the lowermost AlGaN layer in the NSJ structure and a second gate structure portion that reaches the uppermost AlGaN layer, which is an upper layer, are provided. Further, a source region and a drain region constituted by n-type regions are arranged on both sides of the first gate structure portion and the second gate structure portion.

  In the nitride semiconductor device configured as described above, the gate structure portion has a MOS structure. And, since the electrostatic potential of the first gate electrode and the gate insulating film provided in the first gate structure part is lower than the conduction band of the heterojunction of the GaN layer and the AlGaN layer, there is no carrier at the heterointerface, Normally-off operation is performed. In addition, by providing a plurality of heterojunctions, the amount of two-dimensional electron gas (hereinafter referred to as 2DEG) generated can be increased, and the on-resistance can be reduced. A desired off breakdown voltage can be obtained by the polarization effect regardless of the number of stacked heterojunctions.

JP 2013-98284 A

  However, in the nitride semiconductor device disclosed in Patent Document 1, the first gate structure portion of the MOS structure is used in order to perform a normally-off operation. However, since a barrier against electrons is generated in the MOS region, the upper two layers are formed. No electron current flows through the 2DEG layer.

  In addition, the nitride semiconductor device disclosed in Patent Document 1 includes a second gate structure portion that reaches only the uppermost AlGaN layer in addition to the first gate structure portion having the MOS structure. Even when a positive bias is applied to the second gate structure and a current is passed through the upper two layers, a current resistance component due to the tunnel barrier is generated, and thus the on-resistance cannot be sufficiently lowered.

  An object of the present invention is to provide a nitride semiconductor device capable of further reducing the on-resistance.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a substrate (1) made of semi-insulating or semiconductor and a first nitride semiconductor layer (2) constituting an electron transit layer on the substrate. ) And a second nitride semiconductor layer (3) that has a larger forbidden band width than the first nitride semiconductor layer and constitutes an electron supply portion on the first nitride semiconductor layer and the first nitride semiconductor layer. A heterojunction structure including a third nitride semiconductor layer (4) having a forbidden band width smaller than that of the second nitride semiconductor layer includes a plurality of pairs of second nitride semiconductor layers and third nitride semiconductor layers. The stacked two-dimensional electron gas stack and the source region formed so as to reach the first nitride semiconductor layer from the surface of the two-dimensional electron gas stack, being arranged apart from each other in one direction in the plane direction of the substrate (9) and drain region (10) and saw The gate is interposed between the region and the drain region and formed in the recess (5) formed so as to reach the first nitride semiconductor layer from the surface of the two-dimensional electron gas stack through the gate insulating film (6a). A lower channel layer having a gate structure portion (6) configured by providing the electrode (6b), and formed on the semiconductor layer side at the bottom of the gate structure portion when a gate voltage is applied to the gate region; A horizontal switching device is provided that allows current to flow between a source region and a drain region via a plurality of two-dimensional electron gas layers formed in each set. In such a configuration, the carrier of the two-dimensional electron gas layer formed in each of the plurality of sets is guided to the side surface on the source region and drain region side of the concave portion in the gate structure portion, and the lower channel layer A side channel layer (20, 40) is provided to flow to the opposite side of the gate structure via the.

  Thus, the side channel layer is provided on the side surface of the gate structure. For this reason, not only the lowermost layer formed by the first nitride semiconductor layer and the second nitride semiconductor layer but also the carrier of the upper two-dimensional electron gas layer below the gate structure portion through the side channel layer. It flows on the opposite side of the channel layer. As a result, current can flow through each set of two-dimensional electron gas layers, and the on-resistance can be reduced.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a diagram showing a cross-sectional configuration of a nitride semiconductor device according to a first embodiment of the present invention. It is the figure which showed the result of having investigated the change of the drain current Id with respect to gate voltage Vg by changing the thickness of the n ^<+> type ^| mold area | region 20 by simulation. FIG. 3 is a cross-sectional view showing a manufacturing process of the nitride semiconductor device shown in FIG. 1. FIG. 10 is a cross-sectional view showing a nitride semiconductor device manufacturing process described in a modification of the first embodiment. FIG. 10 is a cross-sectional view showing a nitride semiconductor device manufacturing process described in a modification of the first embodiment. FIG. 10 is a cross-sectional view showing a nitride semiconductor device manufacturing process described in a modification of the first embodiment. It is a figure which shows the cross-sectional structure of the nitride semiconductor device concerning 2nd Embodiment of this invention. It is a figure which shows the cross-sectional structure of the nitride semiconductor device concerning 3rd Embodiment of this invention. It is a figure which shows the cross-sectional structure of the nitride semiconductor device concerning 4th Embodiment of this invention. It is a figure which shows the cross-sectional structure of the nitride semiconductor device concerning 5th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, a nitride semiconductor device having a GaN device using a compound semiconductor containing GaN as a main component as a nitride semiconductor will be described.

  As shown in FIG. 1, the nitride semiconductor device according to the present embodiment includes a lateral switching element as a GaN device. In FIG. 1, only one cell of the switching element is shown, but actually, for example, the switching element is configured by forming a plurality of symmetrically laid out layouts with the left end of FIG. 1 as the center line. . This switching element is configured as follows with the left-right direction in FIG. 1 as the x direction, the depth direction as the y direction, and the up and down direction as the z direction.

  The horizontal switching element is formed using a compound semiconductor substrate in which various GaN-based semiconductor layers are formed on a substrate 1. Specifically, the GaN layer 2 is formed on the surface of the substrate 1 that is parallel to the xy plane. On top of this, two or more pairs of AlGaN layers 3 and GaN layers 4 are stacked in order in the z direction, and only the AlGaN layer 3 is formed on the outermost surface. As described above, a compound semiconductor substrate is formed by forming a repetitive structure of a pair layer composed of the GaN layer 2 and the AlGaN layer 3 and the GaN layer 4 on the substrate 1. Hereinafter, the reference numeral indicating the AlGaN layer 3 is indicated as 3a, 3b, 3c in order from the substrate 1 side, and the reference numeral indicating the GaN layer 4 is indicated as 4a, 4b in order from the substrate 1 side.

  The substrate 1 is made of a semiconductor material such as Si (111). Here, the substrate 1 is composed of Si (111), but the substrate 1 may be composed of a semi-insulating substrate such as SiC, a sapphire substrate, or AlN. A buffer layer may be formed on the substrate 1 as necessary. The buffer layer is formed as necessary in order to improve the crystallinity of the GaN layer 2. For example, the buffer layer is composed of an AlGaN-GaN superlattice layer or the like. The crystallinity here means defects or dislocations in the GaN layer 2 and affects the electrical and optical characteristics. If the GaN layer 2 can be formed on the substrate 1 with good crystallinity, the buffer layer need not be formed.

The GaN layers 2, 4a, and 4b constitute an electron transit layer, the GaN layer 2 corresponds to the first nitride semiconductor layer, and the GaN layers 4a and 4b correspond to the third nitride semiconductor layer. . More specifically, the AlGaN layers 3a to 3c are made of Al _x Ga _1-x N (0 <x ≦ 1). The AlGaN layers 3a to 3c are larger in the forbidden band than the first and third nitride semiconductor layers and constitute an electron supply unit, and correspond to the second nitride semiconductor layer. A heterojunction structure including the GaN layer 2, the AlGaN layers 3a to 3c, and the GaN layers 4a and 4b is a 2DEG stack that is a stack in which the 2DEG layers are formed. 2DEG is the GaN layer 2 side of the GaN / AlGaN interface between the GaN layer 2 and the AlGaN 3a, the GaN layer 4a side of the GaN / AlGaN interface between the GaN layer 4a and the AlGaN layer 3b, and the GaN / It is induced on the GaN layer 4b side of the AlGaN interface. That is, 2DEG carriers are induced on the GaN side at the GaN / AlGaN interface by the piezoelectric effect and the polarization effect. Here, the pair layers of the AlGaN layer 3 and the GaN layer 4 are two pairs of the AlGaN layer 3a and the GaN layer 4a and two pairs of the AlGaN layer 3b and the GaN layer 4b, but may be three or more pairs. As the number of sets increases, the number of 2DEG layers formed by induction of 2DEG carriers can be increased.

  The GaN layer 2, the AlGaN layer 3, and the GaN layer 4 are formed by heteroepitaxial growth, for example. Regarding the thickness of each of these layers, one or more pairs of 2DEG layers and two-dimensional hole gas (hereinafter referred to as 2DHG) layers and the same number of positive and negative polarization charges (that is, + polarization and −polarization) are generated and depletion occurs. The thickness is such that the neutral condition is almost satisfied as a whole.

  That is, among these layers, positive polarization charges are generated at the boundary positions of the GaN layer 2 and the AlGaN layer 3a, the GaN layer 4a and the AlGaN layer 3b, and the GaN layer 4b and the AlGaN layer 3c. Further, negative polarization charges are generated at the boundary positions between the AlGaN layer 3a and the GaN layer 4a and between the AlGaN layer 3b and the GaN layer 4b. In the case of this embodiment, when the thickness of the AlGaN layers 3a to 3c is set to a certain value or more, a 2DEG layer is formed in the GaN layer 2 in the vicinity of the boundary position between the GaN layer 2 and the AlGaN layer 3a. In addition, 2DHG is formed in the GaN layer 4a in the vicinity of the boundary position between the AlGaN layer 3a and the GaN layer 4a paired therewith. Similarly, a 2DEG layer is formed on the GaN layer 4a in the vicinity of the boundary position between the GaN layer 4a and the AlGaN layer 3b. Further, 2DHG is formed in the GaN layer 4b in the vicinity of the boundary position between the AlGaN layer 3b and the GaN layer 4b paired therewith.

Specifically, the film thickness of the AlGaN layers 3a to 3c, that is, the dimension in the z direction is set to 10 nm or more and 200 nm or less, preferably 40 nm or more and 100 nm or less. If the film thickness of the AlGaN layers 3a to 3c is less than 10 nm, the 2DEG surface density is smaller than 8 × 10 ¹² cm ⁻² , which increases the on-resistance of the element. On the other hand, when the film thickness of the AlGaN layers 3a to 3c exceeds 200 nm, dislocations and defect density associated with strain relaxation increase, resulting in large variations in device characteristics, causing an extreme decrease in manufacturing yield. Typically, the defect density is 1 × 10 ¹¹ cm ⁻² or more. In addition, it is preferable that the film thickness of the AlGaN layers 3a to 3c be 40 nm or more and 100 nm or less because the essential problems of the above materials do not occur and the 2DEG layer has a high concentration and has a low defect density. Also, the thickness of the GaN layers 4a and 4b formed on the AlGaN layers 3a and 3b needs to be designed in the same film thickness range as described above for the same reason. In particular, in the range of 40 nm to 100 nm, the 2DHG layer is formed in the same order as the 2DEG layer at the GaN / AlGaN interface paired with the interface where the 2DEG layer and the 2DEG layer are formed. It is more preferable because high breakdown voltage can be easily achieved.

The film thickness ratio AlGaN / GaN between the AlGaN layers 3a to 3c and the GaN layers 4a and 4b is 1/5 ≦ AlGaN / GaN ≦ 5, and preferably AlGaN / GaN ≦ 2. When the film thickness ratio AlGaN / GaN exceeds 5, the AlGaN layer 3 is lattice-relaxed, and the 2DEG layer and the 2DHG layer are not effectively generated, resulting in high resistance. Further, when the film thickness ratio AlGaN / GaN is ½ or more and 2 or less, an AlGaN / GaN laminated structure is formed without taking over the lattice constant of the lowermost GaN and remarkably relaxing the strain, and the dislocation and defect density are 1 × 10 ¹¹ cm ⁻² is preferable because it can be kept low.

  About the specific resistance value of a compound semiconductor substrate, what is necessary is just to adjust arbitrarily with the impurity concentration of each layer which comprises a compound semiconductor substrate according to the characteristic of the target device.

  A concave portion 5 having a depth that does not reach the substrate 1 is formed from the surface of the compound semiconductor substrate reaching the layer closest to the substrate 1 in the two-dimensional electron gas stack, that is, the lowermost GaN layer 2. Yes. In the case of this embodiment, the recessed part 5 is extended in the shape of a line in the y direction.

The side surface of the recess 5, that is, the surface that intersects the AlGaN layers 3 a to 3 c and the GaN layers 4 a and 4 b forming the 2DEG stack and faces n ⁺ -GaN layers 9 and 10, which will be described later, has a side channel. An n ⁺ type region 20 corresponding to the layer is formed. The n ⁺ type region 20 is configured by doping an n type impurity such as Si with a high concentration. Specifically, the n ⁺ type region 20 has an n type impurity concentration of 5 × 10 ¹⁸ cm ⁻³ or more. The impurity concentration is preferably as high as possible, and is preferably set to 1 × 10 ²⁰ cm ⁻³ or more. By setting the n-type impurity concentration of the n ⁺ -type region 20 to 5 × 10 ¹⁸ cm ⁻³ or more, the n ⁺ -type region 20 can be separated from each pair layer positioned above the lowermost pair layer through the n ⁺ -type region 20. The current is connected to the lower channel layer formed on the semiconductor layer side at the bottom of the gate structure 6 described later. Thereby, it can flow between source-drain. Since the ease of current flow from each pair layer varies depending on the resistance value of the n ⁺ -type region 20, the resistance value of the n ⁺ -type region 20 may be adjusted to be sufficiently lowered.

  In addition, the gate structure 6 is configured by forming the gate insulating film 6 a and the gate electrode 6 b in each recess 5. For this reason, the gate structure portion 6 also extends in a line shape in the y direction, like the recess portion 5. The length of the gate structure portion 6, that is, the gate length which is the length in the left-right direction on the paper surface is set to 0.5 μm, for example.

Further, on both sides of the gate structure 6, recesses 7 and 8 having a depth reaching the lowermost GaN layer 2 from the surface of the compound semiconductor substrate are formed. In each of the recesses 7 and 8, n ⁺ -GaN layers 9 and 10 formed of n-type semiconductor layers constituting a source region and a drain region are provided. The n ⁺ -GaN layers 9 and 10 are both formed at positions away from the gate structure 6 and extend in the y direction parallel to the gate structure 6.

Note that the device breakdown voltage is determined by the gate-drain distance Lgd, but dimension design may be performed in accordance with a desired device breakdown voltage. Further, on the gate structures 6 and n ⁺ -GaN layer 9 is illustrated without the gate electrode and the source electrode and the drain electrode are formed, and the gate electrode 6b respective electrodes of the gate structures 6 n ⁺ -Ohmic contact with the GaN layers 9, 10.

  As described above, the nitride semiconductor device including the lateral switching element according to the present embodiment is configured. The horizontal switching element configured as described above operates as follows.

First, a case where no gate voltage is applied to the gate electrode 6b will be described. In this state, the electrostatic potential of the gate electrode 6b and the gate insulating film 6a, the Fermi energy E _F is GaN layer 2 and the AlGaN layer 3 or the AlGaN layer 3 and lower than the conduction band E _C heterozygote consisting of GaN layer 4 It has become. For this reason, there are no carriers at the heterointerface. Therefore, the switching element is in an off state, and a normally-off operation can be realized.

Next, a case where a positive bias is applied as a gate voltage to the gate electrode 6b will be described. In this state, the Fermi energy E _F is higher than the conduction band E _C heterozygote consisting of the GaN layer 2 and the AlGaN layer 3 or the AlGaN layer 3 and the GaN layer 4. For this reason, a high concentration electron storage layer is generated at the heterointerface, that is, the surface of the GaN2 layer at the bottom of the gate structure 6. This electron storage layer constitutes a lower channel layer through which a current flows at the bottom of the gate structure 6, in other words, a MOS channel layer. Therefore, the electron carriers between the source and the drain are connected by the 2DEG stack-side channel layer 20 -the lower channel layer, and the switching element is turned on.

Here, the switching element according to the present embodiment includes the n ⁺ -type region 20 having a low resistance value on the side surface of the gate structure portion 6. For this reason, not only the lowermost layer formed by the GaN layer 2 and the AlGaN layer 3, but also the upper layer carriers flow through the n ⁺ -type region 20 to the opposite side from the lower channel layer at the bottom of the gate structure 6. Become. As a result, an electron current can flow through each pair of 2DEG layers, and a reduction in on-resistance can be achieved. In this way, a nitride semiconductor device capable of further reducing the on-resistance can be obtained.

Although the thickness of the n ⁺ -type region 20 is set to 5 nm or more, the carriers in the upper layer can easily flow to the opposite side through the lower side of the gate structure 6 through the side surface of the gate structure 6. It is to do. That is, as the thickness of the n ⁺ -type region 20 is thinner, the resistance value of the n ⁺ -type region 20 is higher. Therefore, a certain amount of thickness is secured in order to reduce the resistance value.

Specifically, when the n ⁺ -type region 20 is 1 × 10 ²⁰ cm ⁻³ and the drain voltage Vd is 0.1 V, the change of the drain current Id with respect to the gate voltage Vg is changed by changing the thickness of the n ⁺ -type region 20. It was investigated by simulation. FIG. 2 shows the result. Note that the distance between the gate and the source-drain is 0.5 μm and 4 μm, respectively. As shown in this figure, when the thickness of the n ⁺ -type region 20 is 5 nm or more, the drain current Id has a desired characteristic even when the thickness is changed from 5 nm to 200 nm. On the other hand, when the thickness of the n ⁺ -type region 20 is 3 nm, the drain current Id is drastically reduced as compared with the case where the thickness is 5 nm or more. This is because although the current due to the carriers formed in the lowermost layer flows when the thickness of the n ⁺ -type region 20 is thin, the 2DEG electrons formed in the upper layer than that do not flow below the gate structure portion 6, and as a current component This is because it does not contribute.

In this way, by setting the thickness of the n ⁺ -type region 20 to 5 nm or more, carriers in the upper layer can flow through the side of the gate structure 6 to the opposite side through the lower side of the gate structure 6. Therefore, it is possible to further reduce the on-resistance.

  Next, a method for manufacturing the horizontal switching element according to the present embodiment will be described with reference to FIG.

[Step shown in FIG. 3 (a)]
A compound semiconductor substrate having a structure in which a GaN layer 2, an AlGaN layer 3a, a GaN layer 4a, an AlGaN layer 3b, a GaN layer 4b, and an AlGaN layer 3c are sequentially stacked on the surface of a substrate 1 made of Si (111). prepare. For example, after forming a buffer layer on the surface of the substrate 1 as necessary, a plurality of pair layers composed of the GaN layer 2, the AlGaN layers 3a to 3c and the GaN layers 4a and 4b are formed by MOCVD (Metal Organic Chemical Vapor Deposition). : Metalorganic vapor phase epitaxy) method. Of course, each layer may be formed by a manufacturing method other than the MOCVD method, for example, an ultra-high purity and high accuracy MBE (Molecular Beam Epitaxy) method.

[Step shown in FIG. 3B]
After forming a mask 11 composed of a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN) on the surface of the GaN layer 4, the mask 11 is patterned to open a region where the gate structure portion 6 is to be formed. . For example, after forming a resist (not shown) on the surface of the mask 11 and patterning the resist through a photolithography process, the mask 11 is patterned using this resist. Thereafter, by performing a dry etching process using the mask 11, the AlGaN layers 3a to 3c and the GaN layers 4a and 4b are etched to form the recesses 5 reaching the GaN layer 2 located at the lowermost layer.

[Step shown in FIG. 3 (c)]
Further, Si, which is an n-type impurity, is implanted obliquely with the mask 11 covering the surface of the AlGaN layer 3c. Thereby, Si is implanted into the side surface and the bottom surface of the recess 5 to form the n ⁺ -type region 20.

[Step shown in FIG. 3 (d)]
Thereafter, using the mask 11 or removing the mask 11, a portion of the n ⁺ -type region 20 formed at the bottom of the recess 5 is removed using a mask in which the recess 5 is formed again. . Thereby, the n ⁺ -type region 20 can be left only on the side surface of the recess 5.

Thereafter, as in the conventional case, the gate insulating film 6a is formed by thermal oxidation or CVD, the gate electrode 6b is embedded, the recesses 7 and 8 are formed, and the n and the source and drain regions are formed. ^A process of forming ⁺ -GaN layers 9 and 10 is performed. Further, after forming an interlayer insulating film so as to cover the uppermost AlGaN layer 4, gate structure 6 and n ⁺ -GaN layers 9, 10, an interlayer insulating film is formed by patterning the interlayer insulating film to form a contact hole Perform the process. Further, an electrode formation process is performed in which a gate electrode, a source electrode, and a drain electrode are formed through the contact hole. Thus, the nitride semiconductor device provided with the switching element according to the present embodiment is completed.

(Modification of the first embodiment)
In the first embodiment described above, the formation process of the trench gate structure can be changed.

  For example, as shown in FIG. 4, after the step of oblique ion implantation of Si as an n-type impurity in FIG. 3C, a mask 30 is arranged so as to cover the outside of the recess 5 and the inner wall surface. Etching in a state covered with 30 deepens the bottom of the recess 5. In the case where the recess 5 is formed by such a process, the bottom surface of the recess 5 has a two-stage structure. Even if such a structure is used, the same effects as those of the first embodiment can be obtained.

Further, instead of the ion implantation step shown in FIG. 3C, the step shown in FIG. 5 may be performed. Specifically, a hard mask 31 having an opening corresponding to the recess 5 is disposed. For example, a silicon nitride film or the like can be used as the hard mask 31. Then, epitaxial growth is performed in a state where portions other than the recess 5 are covered with the hard mask 31. Thereby, the n-type impurity layer is selectively epitaxially grown only in the recess 5 to form the n ⁺ -type region 20. With such a manufacturing method, a nitride semiconductor device having the same structure as that of the first embodiment can be manufactured. In the case of such a manufacturing method, the n ⁺ -type region 20 can also be configured by an n-type silicon layer instead of the n-type GaN layer.

Furthermore, the process of forming the n ⁺ -type region 20 can be combined with the process of forming the n ⁺ -GaN layers 9 and 10.

For example, in the process shown in FIG. 3B, in place of the recess 5, the recess 21 having a width larger than that of the recess 5 is formed, and in addition, the recesses 7 and 8 are simultaneously formed. For example, if the part corresponding to the recessed part 21 and the recessed parts 7 and 8 is opened in the mask 11, the recessed part 21 and the recessed parts 7 and 8 will be formed simultaneously by an etching. Then, as shown in FIG. 6A, a hard mask 32 having openings corresponding to the recesses 21 and the recesses 7 and 8 is disposed. For example, as the hard mask 32, a silicon nitride film or the like can be used. The mask 11 can be used as it is as the hard mask 32 by selecting the material of the mask 11 when forming the recesses 5, 7, 8. Then, epitaxial growth is performed in a state where the portions other than the concave portion 21 and the concave portions 7 and 8 are covered with the hard mask 32. As a result, the n-type impurity layer is selectively epitaxially grown only in the recess 21 and the recesses 7 and 8, and the n ⁺ -type region 20 and the n ⁺ -GaN layers 9 and 10 are formed. Thereafter, as shown in FIG. 6B, a step similar to that shown in FIG. At this time, the depth of the recess 5 is adjusted so that the bottom surface of the recess 5 penetrates the n ⁺ -type region 20. With such a manufacturing method, a nitride semiconductor device having the same structure as that of the first embodiment can be manufactured.

Even in the case of such a manufacturing method, the n ⁺ -type region 20 constituting the side surface channel layer can be constituted not by the n-type GaN layer but by an n-type silicon layer. In this case, the source region and the drain region can also be constituted by n-type silicon layers instead of the n ⁺ -GaN layers 9 and 10. Even when the side channel layer is formed of an n-type silicon layer, the n-type impurity concentration is set to 5 × 10 ¹⁸ cm ⁻³ or more, preferably 1 × 10 ²⁰ cm ⁻³ or more, and the thickness is set to 5 nm or more. The same effect as in the case where the n-type GaN layer is used is obtained.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the side structure of the gate structure 6 is changed from that of the first embodiment. In other respects, the present embodiment is the same as the first embodiment, and therefore only different parts from the first embodiment will be described.

As shown in FIG. 7, in this embodiment, a nitride semiconductor device is configured by including a side metal film 40 formed of metal instead of the n ⁺ -type region 20 as a side channel layer. Thus, even if the side metal film 40 is provided instead of the n ⁺ -type region 20, not only the lowermost layer formed by the GaN layer 2 and the AlGaN layer 3, but also the carriers above the side metal film 40 flows to the opposite side of the lower channel layer formed at the bottom of the gate structure 6. Therefore, the same effect as that of the first embodiment can be obtained also by the nitride semiconductor device of the present embodiment.

  The side metal film 40 can be manufactured by performing selective deposition using the hard mask 31 as shown in FIG. 5 shown in the modification of the first embodiment, and the other processes are the first. This is the same as the embodiment.

(Third embodiment)
A third embodiment of the present invention will be described. This embodiment also changes the side structure of the gate structure part 6 with respect to 1st Embodiment. In other respects, the present embodiment is the same as the first embodiment, and therefore only different parts from the first embodiment will be described.

As shown in FIG. 8, in this embodiment, before the gate insulating film 6a is formed on the surface of the n ⁺ -type region 20, the side insulating film 50 is formed, and the gate insulating film 6a is formed thereon. I am doing so. That is, the side insulating film 50 is provided between the n ⁺ -type region 20 and the gate insulating film 6a. The side insulating film 50 may be composed of a film of the same material as the gate insulating film 6a, but may be composed of a film of a different material, for example, a silicon oxide film or an aluminum nitride film (AlN). Is done. In that case, if the film having a dielectric constant larger than that of the constituent material of the gate insulating film 6a, for example, the gate insulating film 6a is formed of a silicon oxide film, the side surface insulating film 50 is preferably formed of a silicon nitride film.

  Thus, by providing the side surface insulating film 50, the electric field applied to the gate insulating film 6a on the side surface of the gate structure 6 can be weakened. Therefore, the gate insulating film 6a can be prevented from being broken on the side surface of the gate structure portion 6, and the breakdown voltage of the nitride semiconductor device can be improved. In particular, if a film having a large dielectric constant is used, the gate insulating film 6a can be prevented from being broken, and the breakdown voltage of the nitride semiconductor device can be further improved.

  The nitride semiconductor device having such a structure is substantially the same as the manufacturing method described in the first embodiment. For example, after the process shown in FIG. 3C is completed, the side insulating film 50 is selectively formed in the recess 5 using the mask 11, and then the mask 11 is removed using the mask 11. After that, the side insulating film 50 and the Si implantation layer formed on the bottom of the recess 5 are removed using a mask in which the formation position of the recess 5 is opened again. Thereafter, the nitride semiconductor device of this embodiment can be manufactured by performing the same manufacturing process as that of the first embodiment.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, the configuration of the outermost surface of the compound semiconductor substrate is changed with respect to the first to third embodiments. About this others, since this embodiment is the same as that of the 1st-3rd embodiment, only a different portion from the 1st-3rd embodiment is explained. In addition, although the case where the structure of this embodiment is applied with respect to the structure of 1st Embodiment is demonstrated here, it is applicable similarly also to 2nd, 3rd Embodiment.

  As shown in FIG. 9, in this embodiment, the outermost surface of a structure in which a plurality of pairs of AlGaN layers 3 and GaN layers 4 are stacked is formed as a GaN layer 4c. As described above, when the outermost surface of the compound semiconductor substrate is the GaN layer 4c, this functions as a cap layer, and current collapse can be improved. Note that current collapse refers to a phenomenon in which the drain current is greatly reduced due to the effect of increasing the electrical resistance accompanying the switching operation of the switching element, and the drain current takes a long time to recover.

  Thus, the current collapse can be improved by setting the outermost surface of the compound semiconductor substrate to the GaN layer 4c.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. In the present embodiment, the internal configuration of the compound semiconductor substrate is changed with respect to the first to fourth embodiments. About this others, since this embodiment is the same as that of the 1st-4th embodiment, only a different portion from the 1st-4th embodiment is explained. In addition, although the case where the structure of this embodiment is applied with respect to the structure of 1st Embodiment is demonstrated here, it is applicable similarly to 2nd-4th embodiment.

  As shown in FIG. 10, in this embodiment, the thickness of the GaN layer 2 is set as thin as 200 nm or less, and a p-type GaN layer 2 a is provided below the GaN layer 2 or inside the GaN layer 2. In FIG. 10, the p-type GaN layer 2 a is disposed below the GaN layer 2, but it may be formed at an intermediate position in the thickness direction of the GaN layer 2.

  When the p-type GaN layer 2a is not provided, a fixed charge of reverse polarity that compensates for a positive fixed charge that induces 2DEG at the GaN / AlGaN interface by the lowermost GaN layer 2 and the AlGaN layer 3, that is, a negative fixed charge is generated on the substrate. There is no back side of 1. Therefore, unlike each pair of upper layers, charge balance is not achieved, and the depletion layer width extension of the 2DEG layer formed in the lowermost GaN layer 2 is reduced. As described above, since the depletion layer width of the lowermost 2DEG layer is small, current concentrates on the lowermost 2DEG layer at the time of switching transient of the switching element, and heat may be generated to cause damage to the switching element. is there.

  On the other hand, when the structure is provided with the p-type GaN layer 2a as in the present embodiment, negative fixed charges are generated by the p-type GaN layer 2a. Therefore, the positive fixed charge that induces 2DEG at the GaN / AlGaN interface by the lowermost GaN layer 2 and the AlGaN layer 3 can be compensated by the negative fixed charge, and a charge balance can be achieved. Therefore, when a gate voltage is applied, the depletion layer width extension of the lowest 2DEG layer is the same as the depletion layer width extension of the 2DEG layer located on the upper layer side. Furthermore, each layer can be depleted even when the gate voltage is low. In this way, the depletion layer width is also extended for the lowermost 2DEG layer, whereby current can be prevented from concentrating on the lowermost 2DEG layer during the switching transition of the switching element. Therefore, generation of heat in the nitride semiconductor device can be suppressed, damage to the switching element can be prevented, and a nitride semiconductor device that can operate with high reliability at a low gate voltage can be obtained.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

For example, the configuration dimensions and manufacturing method of the nitride semiconductor device described in the above embodiments are merely examples. For example, in each embodiment, the n ⁺ -GaN layers 9 and 10 may be formed by Si ion implantation. When the n ⁺ -GaN layers 9 and 10 are thus formed by ion implantation, the contact resistance can be reduced because the 2DEG layer and the n ⁺ -GaN layers 9 and 10 overlap each other. In addition, since the n ⁺ -GaN layers 9 and 10 are formed by simple ion implantation as compared with selective epi, the manufacturing process can be simplified.

In each of the above embodiments, the source region and the drain region are configured by the n ⁺ -GaN layers 9 and 10, but a structure in which these are replaced by Schottky electrodes may be employed. In the case of such a structure, it is only necessary to embed the Schottky electrode instead of the selective epi, so that the manufacturing process can be simplified as compared with the embedding epi.

  In each of the above embodiments, a structure in which the side surface of the recess 5 is perpendicular to the surface of the compound semiconductor substrate is illustrated, but it is not necessarily perpendicular. For example, the side surface of the recess 5 may be inclined with respect to the surface of the compound semiconductor substrate so that the opening entrance of the recess 5 is larger than the bottom. With such a structure, it is easy to perform ion implantation into the side surface of the recess 5, and the effect of facilitating the thickening of the laminate on the side surface of the recess 5 can be obtained.

  Furthermore, in each of the above-described embodiments, the first and third nitride semiconductor layers and the second nitride semiconductor layer constituting the two-dimensional electron gas stack are formed as GaN layers 2, 4a to 4c and AlGaN layers 3a to 3c, respectively. The case where it comprises is explained as an example. However, these are merely examples, and a two-dimensional electron gas stack is constituted by the first and third nitride semiconductor layers and the second nitride semiconductor layer having a larger forbidden band. Other materials may be used as long as they are present.

DESCRIPTION OF SYMBOLS 1 Substrate 2, 4 GaN layer 2a p-type GaN layer 3 AlGaN layer 5, 7, 8 Recess 6 Gate structure 6a Gate insulating film 6b Gate electrode 9, 10 n ⁺ -GaN layer 20 n ⁺ type region

Claims (10)

A nitride semiconductor device comprising:
A semi-insulating or semiconductor substrate (1);
A first nitride semiconductor layer (2) constituting an electron transit layer is formed on the substrate, and the forbidden band is higher on the first nitride semiconductor layer than the first nitride semiconductor layer. The second nitride semiconductor layer (3, 3a to 3c) having a large width and constituting the electron supply portion and the third nitride semiconductor layer (4, 4a) having a forbidden band width smaller than that of the second nitride semiconductor layer -4c), a two-dimensional electron gas stack in which a plurality of sets of the second nitride semiconductor layer and the third nitride semiconductor layer are stacked,
A source region (9) and a drain region (disposed in one direction in the planar direction of the substrate) that are spaced apart from each other and are formed so as to reach the first nitride semiconductor layer from the surface of the two-dimensional electron gas stack. 10) and
A gate insulating film (6a) is disposed in a recess (5) disposed between the source region and the drain region and formed to reach the first nitride semiconductor layer from the surface of the two-dimensional electron gas stack. ), And a gate structure (6) configured by being provided with a gate electrode (6b),
A lower channel layer formed on the first nitride semiconductor layer side at the bottom of the gate structure portion with application of a gate voltage to the gate region, and a plurality of two-dimensional electron gas stacks formed in each of the plurality of sets. A lateral switching device for passing a current between the source region and the drain region,
A two-dimensional electron gas stack formed in each of the plurality of sets is led to the side surface on the source region and drain region side of the recess in the gate structure portion, and the lower channel layer is formed below the gate structure portion. And a side channel layer (20, 40) flowing on the opposite side of the gate structure. The first nitride semiconductor layer and the third nitride semiconductor layer are made of GaN,
The second nitride semiconductor layer is made of AlGaN;
The said side surface channel layer is comprised by the n-type GaN layer (20), n-type impurity density | concentration shall be ^5x10 < ¹⁸ > cm < ^-3 > or more, and thickness shall be 5 nm or more. Nitride semiconductor device. The first nitride semiconductor layer and the third nitride semiconductor layer are made of GaN,
The second nitride semiconductor layer is made of AlGaN;
2. The nitride semiconductor according to claim 1, wherein the side surface channel layer is composed of an n-type silicon layer, has an n-type impurity concentration of 5 × 10 ¹⁸ cm ⁻³ or more, and a thickness of 5 nm or more. apparatus. The first nitride semiconductor layer and the third nitride semiconductor layer are made of GaN,
The second nitride semiconductor layer is made of AlGaN;
The nitride semiconductor device according to claim 1, wherein the side channel layer is constituted by a side metal film (40) made of metal.   The nitride semiconductor device according to claim 1, wherein the bottom surface of the recess has a two-stage structure.   The nitride semiconductor device according to any one of claims 1 to 5, further comprising a side insulating film (50) provided between the side channel layer and the gate insulating film. A method for manufacturing a nitride semiconductor device, comprising:
Preparing a semi-insulating or semiconductor substrate (1);
A first nitride semiconductor layer (2) constituting an electron transit layer is formed on the substrate, and a forbidden band width is formed on the first nitride semiconductor layer as compared with the first nitride semiconductor layer. A second nitride semiconductor layer (3, 3a to 3c) that largely constitutes an electron supply section and a third nitride semiconductor layer (4, 4a to 4c) having a forbidden band width smaller than that of the second nitride semiconductor layer A step of forming a two-dimensional electron gas stack in which a plurality of the heterojunction structures according to (2) and the second nitride semiconductor layer and the third nitride semiconductor layer are stacked as a set;
Forming a recess (5) reaching the first nitride semiconductor layer from the surface of the two-dimensional electron gas stack;
Forming a gate structure (6) provided with a gate electrode (6b) in the recess through a gate insulating film (6a);
A source region that reaches the first nitride semiconductor layer from the surface of the two-dimensional electron gas stack so as to be disposed on both sides of the gate structure portion and spaced apart from each other in one plane direction of the substrate (9) and forming a drain region (10),
The carrier of the two-dimensional electron gas layer formed in each of the plurality of sets is guided below the gate structure portion on the side surface on the source region and drain region side of the recess, and formed at the bottom of the gate structure portion. And forming a side channel layer (20, 40) that flows to the opposite side of the gate structure portion through the lower channel layer.   8. The method for manufacturing a nitride semiconductor device according to claim 7, wherein the step of forming the side surface channel layer is a step of ion-implanting n-type impurities into the side surface of the recess after the step of forming the recess.   8. The method of manufacturing a nitride semiconductor device according to claim 7, wherein the step of forming the side surface channel layer is a step of selectively epitaxially growing an n-type semiconductor on a side surface of the concave portion after the step of forming the concave portion.   The step of forming the side surface channel layer includes the step of forming an n-type impurity layer in a portion corresponding to the concave portion and the side surface channel layer and forming the concave portion before the step of forming the concave portion. The nitride semiconductor device according to claim 7, further comprising: forming the recesses in the type impurity layer to leave the n-type impurity layer on the side surfaces of the recesses to form the side surface channel layers. Manufacturing method.

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