CN113644128A - GaN-based high electron mobility transistor with groove-grid multi-channel structure and manufacturing method - Google Patents
GaN-based high electron mobility transistor with groove-grid multi-channel structure and manufacturing method Download PDFInfo
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Abstract
The invention relates to a GaN-based high electron mobility transistor with a groove gate multi-channel structure and a manufacturing method thereof, wherein the high electron mobility transistor comprises: the substrate, at least four layers of heterojunction structures, a source electrode, a drain electrode, an intermediate layer and a gate electrode, wherein the at least four layers of heterojunction structures are sequentially stacked on the substrate, and a gate groove is formed in the at least four layers of heterojunction structures and used for isolating two-dimensional electron gas formed by the at least four layers of heterojunction structures; the source electrode is embedded into one end of the at least four-layer heterojunction structure; the drain electrode is embedded into the other end of the at least four-layer heterojunction structure; the middle layer is positioned in the gate groove and on the surface of the at least four-layer heterojunction structure, one end of the middle layer is in contact with the source electrode, the other end of the middle layer is in contact with the drain electrode, and two-dimensional electron gas is formed between the middle layer and the at least four-layer heterojunction structure; the gate electrode is located in the gate trench and on the intermediate layer. The high electron mobility transistor realizes larger forward current and obtains smaller on-resistance under the condition that the threshold voltage and the transconductance are not seriously deteriorated.
Description
Technical Field
The invention belongs to the field of semiconductor device structures and manufacturing, and particularly relates to a GaN-based high electron mobility transistor with a groove gate multi-channel structure and a manufacturing method thereof.
Background
With the rapid development of the semiconductor field, the third generation semiconductor typified by GaN attracts attention. The forbidden bandwidth of the GaN material is greatly improved compared with that of Si, so that the GaN has more excellent performances, such as high critical breakdown field strength, high thermal conductivity, high saturated electron velocity, good high temperature resistance, radiation resistance and the like. In terms of device manufacturing, GaN can be combined with AlGaN to form an AlGaN/GaN HEMT device, and electrons with high concentration are formed at the interface of AlGaN/GaN two materials, are confined in a potential well and can move freely only in two directions, so that the AlGaN/GaN HEMT device has higher mobility and is called two-dimensional electron gas (2DEG), and thus research on the AlGaN/GaN HEMT device becomes a hot spot.
In order to pursue larger saturation current and smaller series resistance, multi-channel AlGaN/GaN HEMT devices have come into the sight of people and are widely researched. The multi-channel AlGaN/GaN HEMT device is formed by overlapping a plurality of layers of AlGaN/GaN channels, and the current carriers in the channels are expected to show multiple increase along with the increase of the number of the channels, so that more excellent performance is realized.
As early as 2005, Jie Liu et Al realized Al with high linearity by inserting a layer of AlGaN with a thickness of 6nm and an Al composition of 5% into the channel region0.3Ga0.7N–Al0.05Ga0.95An N-GaN composite channel structure device. The device is measured by direct current and radio frequency, and the transconductance and the cut-off frequency can be maintained near the peak value. These characteristics facilitate linear large signal operation and are suitable for advanced 3G wireless systems, such as W-CDMA/UMTS.
In 2010, Xian electronics science university's Ministry of technology took Si as SiH4Is introduced into the reaction chamber by applying a concentration of 3 x 10 to the barrier layer of graded aluminum composition nearest to the substrate19And doping Si delta to obtain the AlGaN/GaN/AlGaN/GaN double-channel heterojunction material. The HEMT device is manufactured by the double-channel heterojunction material through a tape, the measured ohmic contact resistance of the doped double-channel device is 0.0495 ohm.mm, the drain-source current when a grid electrode is suspended reaches 2A/mm, and experiments prove that the mobility and other electrical characteristics of current carriers in the double channels still have good stability in a high-temperature environment. The device can be used for realizing large current and reducing the resistance of a source region and a drain region.
In 2020, Y.H Chang et al improved the off-state breakdown voltage of a dual-channel AlGaN/GaN HEMT by using an air bridge field plate (AFP) and a tilted field plate on the gate. According to the double-channel AlGaN/GaN HEMT, the peak electric field near the edge of a grid can be reduced to a certain extent only by using AFP, if an inclined field plate is added, a better effect can be obtained, and the breakdown voltage is improved by 10 times; the air bridge field plate and the inclined field plate are proved to reduce the peak electric field of the channel and increase the breakdown voltage of the double-channel HEMT device.
The multi-channel device has only two channels, because the gate has difficulty in controlling the underlying channels as the number of channels increases, but the number of channels needs to be increased for higher current requirements, and other methods are sought for controlling all channels.
In 2021, Luca Nela et al combined a Si-based four channel device with a FinFET structure and passivated the device. Experiments found that the same breakdown voltage V is maintainedBRIn the case of (3), the on-resistance RONCompared with the traditional single-channel device, the single-channel device is reduced by about 3 times, and the SiN passivation layer effectively reduces traps at the contact position of the grid and the channel and improves breakdown voltage. Researches find that the multi-channel device is combined with a FinFET structure, and the grid electrodes on two sides of the channel can control 2DEG in the channel by depositing the grid electrodes on the side wall of the channel, so that the effect that one grid electrode simultaneously controls a plurality of channels is achieved, current carriers in the channel can be effectively depleted, and the device has good performance。
However, the manufacturing process of the FinFET structure is too complex and precise, and when the FinFET structure is combined with a multi-channel HEMT device, the complexity of the process is further increased, and it is difficult to realize the preparation and mass production of high-quality devices; at the same time, the use of FinFET structures can deplete the concentration of carriers in the channel, thereby reducing current.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a GaN-based high electron mobility transistor with a trench gate multi-channel structure and a manufacturing method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a high electron mobility transistor with a groove gate multi-channel structure, which comprises: the solar cell comprises a substrate, at least four layers of heterojunction structures, a source electrode, a drain electrode, an intermediate layer and a gate electrode, wherein the at least four layers of heterojunction structures are sequentially stacked on the substrate, and a gate groove is formed in each of the at least four layers of heterojunction structures and used for cutting off two-dimensional electron gas formed by the at least four layers of heterojunction structures;
the source electrode is embedded into one end of the at least four-layer heterojunction structure;
the drain electrode is embedded into the other end of the at least four-layer heterojunction structure;
the intermediate layer is positioned in the gate groove and on the surface of the at least four-layer heterojunction structure, one end of the intermediate layer is in contact with the source electrode, the other end of the intermediate layer is in contact with the drain electrode, and two-dimensional electron gas is formed between the intermediate layer and the at least four-layer heterojunction structure;
the gate electrode is located in the gate trench and on the intermediate layer.
In one embodiment of the invention, the heterojunction structure comprises an intrinsic layer and a barrier layer, wherein the barrier layer is on the intrinsic layer.
In one embodiment of the invention, the thickness of the intrinsic layer on the substrate is 200nm, and the thickness of the intrinsic layer on the barrier layer is 20-50 nm.
In one embodiment of the invention, the barrier layer has a thickness of 10-30 nm.
In one embodiment of the invention, the material of the intrinsic layer is GaN, and the material of the barrier layer is AlxGa1-xN, the material of the intermediate layer comprises AlyGa1-yN, AlN, wherein the value of x is different from the value of y.
In one embodiment of the present invention, when the material of the barrier layer is AlxGa1-xN and the material of the intermediate layer is AlyGa1-yWhen N is contained, x is 10-25% and y is greater than or equal to 35%.
In one embodiment of the invention, the thickness of the intermediate layer is 5-30 nm.
Another embodiment of the present invention provides a method for manufacturing a high electron mobility transistor with a trench gate multi-channel structure, including the steps of:
s1, repeatedly preparing heterojunction structures on the substrate to form at least four layers of heterojunction structures which are sequentially stacked, wherein each heterojunction structure forms two-dimensional electron gas;
s2, preparing a source electrode at one end of the at least four-layer heterojunction structure, and preparing a drain electrode at the other end of the at least four-layer heterojunction structure;
s3, etching the at least four layers of heterojunction structures to form a gate groove, wherein the gate groove cuts off two-dimensional electron gas formed by the at least four layers of heterojunction structures;
s4, preparing intermediate layers in the gate groove and on the surface of the at least four-layer heterojunction structure, wherein a two-dimensional electron gas is formed between the intermediate layers and the at least four-layer heterojunction structure;
and S5, preparing a gate electrode on the intermediate layer.
In one embodiment of the present invention, step S1 includes:
s11, sequentially growing an intrinsic layer and a barrier layer on the substrate by utilizing a metal organic chemical vapor deposition process to form a heterojunction structure;
s22, repeatedly growing the intrinsic layer and the barrier layer on the heterojunction structure to obtain the at least four-layer heterojunction structure.
In one embodiment of the invention, the material of the intrinsic layer is GaN, and the material of the barrier layer is AlxGa1-xN, the material of the intermediate layer comprises AlyGa1-yN, AlN, wherein the value of x is different from the value of y.
Compared with the prior art, the invention has the beneficial effects that:
in the high electron mobility transistor, multiple channels formed by at least four layers of heterojunction structures are combined with the groove gate, the middle layer is deposited between the gate electrode and the heterojunction structures, the middle layer can generate a polarization effect with the heterojunction structures to form two-dimensional electron gas, and when forward bias is applied to the gate electrode, carriers in the isolated heterojunction structures flow and are communicated along the middle layer, so that the gate electrode can simultaneously control the two-dimensional electron gas in all the channels of the device, and under the condition that threshold voltage and transconductance are not seriously deteriorated, larger forward current is realized, and smaller on-resistance is obtained.
Drawings
Fig. 1 is a schematic structural diagram of a high electron mobility transistor with a trench gate multi-channel structure according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a method for manufacturing a high electron mobility transistor with a trench gate multi-channel structure according to an embodiment of the present invention;
fig. 3a to fig. 3i are schematic process diagrams of a method for manufacturing a high electron mobility transistor with a trench gate multi-channel structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a high electron mobility transistor with a trench gate multi-channel structure according to an embodiment of the present invention, where the high electron mobility transistor includes: a substrate 1, at least a four-layer heterojunction structure 2, a source electrode 3, a drain electrode 4, an intermediate layer 5 and a gate electrode 6.
Wherein, at least four layers of heterojunction structures 2 are sequentially laminated on the substrate 1, and a gate groove 23 is arranged in at least four layers of heterojunction structures 2, and the gate groove 23 cuts off two-dimensional electron gas formed by at least four layers of heterojunction structures 2; the source electrode 3 is embedded into one end of the at least four-layer heterojunction structure 2; the drain electrode 4 is embedded in the other end of the at least four-layer heterojunction structure 2; the intermediate layer 5 is positioned in the gate groove 23 and on the surface of the at least four-layer heterojunction structure 2, one end of the intermediate layer is contacted with the source electrode 3, the other end of the intermediate layer is contacted with the drain electrode 4, and two-dimensional electron gas is formed between the intermediate layer 5 and the at least four-layer heterojunction structure 2; the gate electrode 6 is located in the gate trench 23 and on the intermediate layer 5.
Specifically, the high electron mobility transistor adopts a multi-channel HEMT device, the device comprises at least four layers of heterojunction structures 2, each layer of heterojunction structure 2 forms two-dimensional electron gas, so that a plurality of channels are formed, the channels are overlapped, the device can form channels of a plurality of carriers between a source and a drain, series resistance between the source and the drain is obviously reduced, and the device has large current driving capability.
In the embodiment, when the number of the heterojunction is 1-3, the control capability of the conventional gate electrode on the current carrier in the lower channel is weakened to a certain extent compared with that of a single channel, but the flow of the current carrier in the lower channel can be directly controlled; when the number of the heterojunction is continuously increased, the control capability of the conventional gate electrode on the current carrier in the lower-layer channel is further weakened, and the control capability is poor; the device is damaged by etching, so that the performance of the device is reduced, and if the number of the heterojunction is small, the performance of the device is obviously deteriorated by the damage; when the number of the heterojunction is more than or equal to 4, the carrier concentration in the device is higher, and the performance deterioration caused by etching damage is weakened; therefore, in the embodiment, the number of the heterojunction in the multi-channel HEMT device is more than or equal to 4.
A grid groove 23 is etched in at least four layers of the heterojunction structures 2, the uppermost heterojunction structure 2 penetrates through the grid groove 23 to the lowermost heterojunction structure 2, and two-dimensional electron gas formed by the heterojunction structures 2 on all layers is separated. A source electrode 3 is embedded in one end of at least four layers of the heterojunction structures 2, a drain electrode 4 is embedded in the other end of the heterojunction structures, and the two-dimensional electron gas formed by the heterojunction structures 2 in each layer is isolated by the source electrode 3 and the drain electrode 4.
The intermediate layer 5 covers the sides and bottom of the heterojunction structure 2 in the gate trench 23, forming a recess in the gate trench 23, in which the gate electrode 6 is disposed, thereby forming a trench gate, the gate electrode 6 penetrating deep into the channel layer lower layer; meanwhile, the intermediate layer 5 is positioned on the surface of the uppermost heterojunction structure 2, one end of the intermediate layer 5 is in contact with the source electrode 3, and the other end of the intermediate layer 5 is in contact with the drain electrode 4; further, a polarization effect is generated between the intermediate layer 5 and the at least four-layer heterojunction structure 2, and a two-dimensional electron gas is formed.
The high electron mobility transistor of the embodiment adopts a trench gate structure, and the gate electrode is deep into the lower layer of the channel layer and can directly control carriers in all channels, so that the transconductance of the device is not deteriorated, and the threshold voltage can move in the forward direction.
The high electron mobility transistor of this embodiment deposits the intermediate level between gate electrode and heterojunction structure, there is the polarization effect between intermediate level and the heterojunction structure, can form 2DEG, when exerting forward bias to the gate electrode, the carrier in the channel of being carved off can flow UNICOM along the intermediate level, thereby all channels are all linked by the carrier, form heavy current, and then the gate electrode can control the two-dimentional electron gas in all channels in the device simultaneously, under the condition that threshold voltage and transconductance do not seriously worsen, bigger forward current has been realized, smaller on-resistance has been obtained. Meanwhile, the middle layer can effectively reduce the damage caused by etching the gate groove, reduce the interface state and weaken the current collapse effect of the device.
In a particular embodiment, the heterojunction structure 2 comprises an intrinsic layer 21 and a barrier layer 22, wherein the barrier layer 22 is located on the intrinsic layer 21.
Specifically, the gate trench 23 is etched into the intrinsic layer 21 of the bottom heterojunction structure 2, and the source electrode 3 and the drain electrode 4 are both located in the intrinsic layer 21 of the bottom heterojunction structure 2.
In one embodiment, the intrinsic layer 21 is GaN and the barrier layer 22 is AlxGa1-xN, forming AlGaN/GaN hetero-layer between the intrinsic layer 21 and the barrier layer 22Knot formation; the material of the intermediate layer comprises AlyGa1-yN, AlN; wherein the value of x is different from the value of y.
When the material of the middle layer 5 is AlN, the AlN can generate two-dimensional electron gas with AlGaN in the AlGaN/GaN heterojunction, and can also generate two-dimensional electron gas with GaN in the AlGaN/GaN heterojunction, so that carriers in the etched channel can flow and communicate along the middle layer to form large current. When the material of the intermediate layer 5 is AlyGa1-yN，AlyGa1-yN can generate two-dimensional electron gas between GaN in AlGaN/GaN heterojunction, and 2DEG, Al can be generated between AlGaN with different Al compositions due to different values of x and yyGa1-yN may also be reacted with AlxGa1-xN generates a two-dimensional electron gas, so that a large current can be formed.
Specifically, Al is selected as the material of the intermediate layer 5yGa1-yWhen N is, AlxGa1-xX in the N barrier layer 22 is 10% to 25%, AlyGa1-yY of the N intermediate layer 5 is 35% or more.
In one embodiment, the intrinsic layer 21 on the substrate 1 has a thickness of 200nm, and the intrinsic layer 21 on the barrier layer 22 has a thickness of 20 to 50nm, i.e., when the number of the heterojunction structures 2 is 5, the thickness of the intrinsic layer 21 on the lowermost layer is 200nm, and the thickness of the intrinsic layer 21 on the upper 4 layers is 20 to 50 nm; the barrier layer 22 has a thickness of 10 to 30nm, and the intermediate layer 5 has a thickness of 5 to 30 nm.
The high electron mobility transistor of the embodiment can exert the advantages of a multi-channel HEMT device, namely, high 2DEG concentration and high current can be realized, and meanwhile, a smaller source-drain series resistor is obtained, so that the application under the high-current working condition is realized.
Example two
On the basis of the first embodiment, please refer to fig. 2 and fig. 3a to fig. 3i, fig. 2 is a schematic flow chart of a method for manufacturing a high electron mobility transistor with a trench gate multi-channel structure according to an embodiment of the present invention, and fig. 3a to fig. 3i are schematic process diagrams of a method for manufacturing a high electron mobility transistor with a trench gate multi-channel structure according to an embodiment of the present invention. The manufacturing method comprises the following steps:
s1, repeatedly preparing heterojunction structures on the substrate 1 to form at least four layers of heterojunction structures 2 which are sequentially stacked, wherein each heterojunction structure 2 forms two-dimensional electron gas.
In this embodiment, the material of the substrate 1 comprises sapphire or SiC, see fig. 3 a.
When the number of layers of the heterojunction structure 2 is 5, the step S1 specifically includes:
s11, using Metal-Organic Chemical Vapor Deposition (MOCVD), sequentially growing the intrinsic layer 21 and the barrier layer 22 on the substrate 1 to form a heterojunction structure, as shown in fig. 3 b.
First, on the substrate 1, the GaN intrinsic layer 21 is grown by the MOCVD process.
Then, on the GaN intrinsic layer 21, the AlGaN barrier layer 22 continues to grow, forming a heterojunction structure 2; the contact position of the AlGaN barrier layer 22 and the GaN intrinsic layer 21 forms 2 DEG.
S22, repeating the growth of the intrinsic layer 21 and the barrier layer 22 on the heterojunction structure 2, resulting in at least a four-layer heterojunction structure 2, see fig. 3 c.
And continuously growing the GaN intrinsic layer 21 and the AlGaN barrier layer 22 on the AlGaN barrier layer 22 by using an MOCVD process, and repeatedly growing the GaN intrinsic layer 21 and the AlGaN barrier layer 22 until a five-layer heterojunction structure is formed, thereby obtaining the multi-channel material with five layers of heterojunction.
In the five-layer heterojunction structure, the thickness of an intrinsic layer 21 on a substrate 1 is 200nm, and the thickness of the intrinsic layer 21 on a barrier layer 22 is 20-50 nm; in the AlGaN barrier layer 22, the Al component is 10-25%, and the thickness of the AlGaN barrier layer 22 is 10-30 nm.
S2, preparing a source electrode 3 at one end of the at least four-layer heterojunction structure 2 and a drain electrode 4 at the other end.
Firstly, spin coating at a rotation speed of 3500 revolutions per minute by using a spin coater to obtain a photoresist mask; exposing by using a photoetching machine to form a mask pattern of the mesa source and drain electrode region; then, an inductively coupled plasma etcher is adopted on the substrate with the mask made, and BCl is used3/Cl2And etching the substrate by the plasma at an etching rate of 1nm/s to an etching depth of 150-300 nm to form a source electrode groove 31 and a drain electrode groove 41, as shown in fig. 3 d.
Then, manufacturing source and drain electrodes in the source electrode groove 31 and the drain electrode groove 41 at an evaporation rate of 0.1nm/s by adopting an electron beam evaporation table, wherein Ti/Al/Ni/Au is sequentially selected for the source and drain metals, the thickness of Ti is 30nm, the thickness of Al is 180nm, the thickness of Ni is 80nm, and the thickness of Au is 100 nm; and (4) stripping metal after the evaporation of the source-drain ohmic contact metal is finished to obtain a complete source-drain electrode, please refer to fig. 3 e.
Finally, the mixture is subjected to a rapid thermal annealing furnace at 870 ℃ N2And carrying out rapid thermal annealing for 30s in the atmosphere, and alloying the ohmic contact metal to finish the manufacture of the source electrode and the drain electrode.
S3, fabricating an active region, please refer to fig. 3 f.
Firstly, spin coating at a rotation speed of 3500 revolutions per minute by using a spin coater to obtain a photoresist mask; exposing by using a photoetching machine to form a mask pattern of the table-board active region; then, an inductively coupled plasma etcher is adopted on the substrate with the mask made, and BCl is used3/Cl2The plasma is used for isolating the table board at the etching rate of 1nm/s, and the etching depth is 200-300 nm.
S4, etching the at least four layers of the heterojunction structure 2 to form a gate trench 23, wherein the gate trench 23 blocks the two-dimensional electron gas formed by the at least four layers of the heterojunction structure 2, as shown in fig. 3 g.
Specifically, positive photoresist is thrown on the surface of the epitaxial material at the rotating speed of 5000 revolutions per minute to obtain a photoresist mask with the thickness of 0.8 mu m, the photoresist mask is baked for 10min in a high-temperature oven at the temperature of 80 ℃, and then a photoetching machine is adopted to carry out photoetching to obtain a grid region open hole pattern; then, an inductively coupled plasma etcher using BCl was used3/Cl2And etching and removing the 150-300 nm AlGaN/GaN heterojunction layer at the grid region by the plasma at an etching rate of 0.5nm/s to separate two-dimensional electron gas formed by the five-layer heterojunction structure 2 and form a grid groove 23.
S5, preparing an intermediate layer 5 in the gate trench 23 and on the surface of the at least four layers of the heterojunction structure 2, forming a two-dimensional electron gas between the intermediate layer 5 and the at least four layers of the heterojunction structure 2, see fig. 3 h.
Specifically, by using the MOCVD process, an intermediate layer material of 10nm is grown on the surface of the AlGaN barrier layer 22 of the heterojunction structure 2 on the uppermost layer and the gate trench region, to form the intermediate layer 5.
Specifically, the material of the intermediate layer 5 includes AlyGa1-yN, AlN; wherein, AlxGa1-xThe value of x and Al in the N-barrier layer 22yGa1-yThe value of y in the N intermediate layers 5 is different.
When the material of the middle layer 5 is AlN, the AlN can generate two-dimensional electron gas with AlGaN in the AlGaN/GaN heterojunction, and can also generate two-dimensional electron gas with GaN in the AlGaN/GaN heterojunction, so that carriers in the etched channel can flow and communicate along the middle layer to form large current. When the material of the intermediate layer 5 is AlyGa1-yN，AlyGa1-yN can generate two-dimensional electron gas between GaN in AlGaN/GaN heterojunction, and 2DEG, Al can be generated between AlGaN with different Al compositions due to different values of x and yyGa1-yN may also be reacted with AlxGa1-xN generates a two-dimensional electron gas, so that a large current can be formed.
Specifically, Al is selected as the material of the intermediate layer 5yGa1-yWhen N is, AlxGa1-xX in the N barrier layer 22 is 10% to 25%, AlyGa1-yY of the N intermediate layer 5 is 35% or more.
Specifically, the thickness of the intermediate layer 5 is 5-30 nm.
S6, preparing a gate electrode 6 on the intermediate layer 5, see fig. 3 i.
Firstly, spin coating with a spin coater at a rotating speed of 5000 r/min to obtain a photoresist mask with a thickness of 0.8 μm; then, baking for 10min in a high-temperature oven at the temperature of 80 ℃, exposing by adopting a photoetching machine, and forming a gate region mask pattern on the dielectric layer 5; finally, evaporating gate metal at an evaporation rate of 0.1nm/s by adopting an Ohmiker-50 electron beam evaporation table, wherein the gate metal is sequentially Ni/Au, the thickness of Ni is 40nm, and the thickness of Au is 400 nm; after the evaporation is finished, metal stripping is carried out to obtain the complete gate electrode 6.
And S7, completing the manufacture of the interconnection lead.
Firstly, throwing positive photoresist at the rotating speed of 5000 r/min by using a photoresist spinner; then, exposing by using a photoetching machine to form an electrode lead mask pattern; then, conducting lead electrode metal evaporation on the substrate with the manufactured mask at an evaporation rate of 0.3nm/s by adopting an Ohmiker-50 electron beam evaporation table, wherein the metal is 20nm in Ti thickness and 200nm in Au thickness; and finally, stripping after the evaporation of the lead electrode metal is finished to obtain the complete lead electrode.
In this embodiment, an AlN or AlGaN interlayer is deposited at the etch site prior to the gate deposition. A polarization effect exists between the AlN or AlGaN intermediate layer and the side face of the AlGaN/GaN heterojunction, 2DEG can be formed, and when forward bias is applied to the grid electrode, carriers in the etched channel can flow and communicate along the intermediate layer to form large current.
In the embodiment, the AlN or AlGaN intermediate layer is deposited below the grid, so that the damage caused by etching can be effectively reduced, the interface state is reduced, and the current collapse effect of the device is weakened.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A trench-gate multi-channel high electron mobility transistor comprising: a substrate (1), at least a four-layer heterojunction structure (2), a source electrode (3), a drain electrode (4), an intermediate layer (5) and a gate electrode (6), wherein,
the at least four layers of heterojunction structures (2) are sequentially stacked on the substrate (1), grid grooves (23) are formed in the at least four layers of heterojunction structures (2), and the grid grooves (23) are used for isolating two-dimensional electron gas formed by the at least four layers of heterojunction structures (2);
the source electrode (3) is embedded in one end of the at least four-layer heterojunction structure (2);
the drain electrode (4) is embedded in the other end of the at least four-layer heterojunction structure (2);
the intermediate layer (5) is positioned in the gate groove (23) and on the surface of the at least four-layer heterojunction structure (2), one end of the intermediate layer is in contact with the source electrode (3), the other end of the intermediate layer is in contact with the drain electrode (4), and two-dimensional electron gas is formed between the intermediate layer (5) and the at least four-layer heterojunction structure (2);
the gate electrode (6) is located in the gate trench (23) and on the intermediate layer (5).
2. The trench-gate multi-channel structure hemt of claim 1, wherein said heterojunction structure (2) comprises an intrinsic layer (21) and a barrier layer (22), wherein said barrier layer (22) is located on said intrinsic layer (21).
3. The trench-gate multi-channel structure HEMT according to claim 2, wherein the thickness of the intrinsic layer (21) on the substrate (1) is 200nm, and the thickness of the intrinsic layer (21) on the barrier layer (22) is 20-50 nm.
4. The trench-gate multi-channel high electron mobility transistor according to claim 2, wherein the thickness of the barrier layer (22) is 10-30 nm.
5. The trench-gate multi-channel structure HEMT according to claim 2, wherein the intrinsic layer (21) is GaN and the barrier layer (22) is AlxGa1-xN, the material of the intermediate layer (5) comprises AlyGa1-yN, AlN, wherein the value of x is different from the value of y.
6. The trench-gate multi-channel structure HEMT of claim 5 which isCharacterized in that when the material of the barrier layer (22) is AlxGa1-xN and the material of the intermediate layer (5) is AlyGa1-yWhen N is contained, x is 10-25% and y is greater than or equal to 35%.
7. The trench-gate multi-channel high electron mobility transistor according to claim 1, wherein the thickness of the intermediate layer (5) is 5 to 30 nm.
8. A manufacturing method of a high electron mobility transistor with a groove gate multi-channel structure is characterized by comprising the following steps:
s1, repeatedly preparing heterojunction structures on the substrate (1) to form at least four layers of heterojunction structures (2) which are sequentially stacked, wherein each heterojunction structure (2) forms two-dimensional electron gas;
s2, preparing a source electrode (3) at one end of the at least four-layer heterojunction structure (2), and preparing a drain electrode (4) at the other end;
s3, etching the at least four layers of heterojunction structures (2) to form gate grooves (23), wherein the gate grooves (23) isolate two-dimensional electron gas formed by the at least four layers of heterojunction structures (2);
s4, preparing an intermediate layer (5) in the gate groove (23) and on the surface of the at least four-layer heterojunction structure (2), wherein a two-dimensional electron gas is formed between the intermediate layer (5) and the at least four-layer heterojunction structure (2);
s5, preparing a gate electrode (6) on the intermediate layer (5).
9. The method of claim 8, wherein step S1 includes:
s11, sequentially growing an intrinsic layer (21) and a barrier layer (22) on the substrate (1) by utilizing a metal organic chemical vapor deposition process to form a heterojunction structure;
s22, repeatedly growing the intrinsic layer (21) and the barrier layer (22) on the heterojunction structure (2), resulting in the at least four-layer heterojunction structure (2).
10. The method for manufacturing a trench-gate multi-channel high electron mobility transistor according to claim 8, wherein the intrinsic layer (21) is made of GaN, and the barrier layer (22) is made of AlxGa1-xN, the material of the intermediate layer (5) comprises AlyGa1-yN, AlN, wherein the value of x is different from the value of y.
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