CN106206299A - A kind of VDMOS device and preparation method thereof - Google Patents
A kind of VDMOS device and preparation method thereof Download PDFInfo
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Abstract
The invention provides a kind of VDMOS device and preparation method thereof, relate to semiconductor chip and manufacture field, solve the problem that the EAS of existing VDMOS device easily lost efficacy, this manufacture method includes: in N-type substrate layer superficial growth the first N-type epitaxy layer；At the first N-type epitaxy layer superficial growth p-type epitaxial layer；The second N-type epitaxy layer is grown in p-type epi-layer surface；In second N-type epitaxy layer superficial growth the first oxide layer；First oxide layer, the second N-type epitaxy layer and p-type epitaxial layer presumptive area are performed etching, forms the difference in height of bottom of the first groove, the bottom of the first groove and p-type epitaxial layer in preset range；The sidewall implantation concentration of the first groove is regulated impurity；First groove is proceeded etching, makes the bottom of the first groove extend in the first N-type epitaxy layer；Remove the first oxide layer, and growth regulation dioxide layer, polycrystalline grid, medium of oxides layer and metal level.The solution of the present invention improves the EAS ability of device.
Description
Technical field
The present invention relates to semiconductor chip and manufacture field, particularly to a kind of VDMOS device and making thereof
Method.
Background technology
VDMOS (Vertical double diffused metal oxide semiconductor, vertical double diffusion
Metal oxide semiconductor field effect tube) device has a very important parameter, EAS
(Single Pulsed Avalanche Energy, pulse avalanche energy), is defined as under single avalanche condition
The ceiling capacity that device can consume.Under the applied environment that source electrode and drain electrode can produce bigger due to voltage spikes,
The avalanche energy of device have to be considered.EAS ability be also weigh one of VDMOS device the heaviest
The parameter wanted.
But the manufacture method of VDMOS device brings the biggest being stranded to the EAS ability of optimised devices at present
Difficulty, the EAS easily producing device lost efficacy.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of VDMOS device and preparation method thereof, solves
In prior art, the manufacture method of VDMOS device brings the biggest being stranded to the EAS ability of optimised devices
Difficulty, easily produces the problem that the EAS of device lost efficacy.
For solving above-mentioned technical problem, embodiments of the invention provide the making side of a kind of VDMOS device
Method, including:
In N-type substrate layer superficial growth the first N-type epitaxy layer；
At described first N-type epitaxy layer superficial growth p-type epitaxial layer；
The second N-type epitaxy layer is grown in described p-type epi-layer surface；
In described second N-type epitaxy layer superficial growth the first oxide layer；
To described first oxide layer, described second N-type epitaxy layer and described p-type epitaxial layer presumptive area
Part performs etching, and forms the bottom of the first groove, the bottom of described first groove and described p-type epitaxial layer
Between difference in height in preset range；
The sidewall implantation concentration of described first groove is regulated impurity；
Described first groove is proceeded etching, makes the bottom of described first groove extend to a described N
In type epitaxial layer；
Remove described first oxide layer, and growth regulation dioxide layer, polycrystalline grid, medium of oxides layer and gold
Belong to layer.
Wherein, the resistance value of described first N-type epitaxy layer is more than the first preset value, described p-type epitaxial layer
And the resistance value of described second N-type epitaxy layer is less than the second preset value.
Wherein, described concentration adjustment impurity is N-type impurity.
Wherein, described to described first oxide layer, described second N-type epitaxy layer and described p-type epitaxial layer
The part of presumptive area performs etching, and forms the first groove, including:
To described first oxide layer, described second N-type epitaxy layer and described p-type epitaxial layer presumptive area
After part carries out photoetching, then perform etching, form the first groove；
After forming described first groove, remove photoresist.
Wherein, described growth regulation dioxide layer, polycrystalline grid medium of oxides layer and metal level, including:
At described second N-type epitaxy layer and described first flute surfaces growth regulation dioxide layer；
In described first groove, fill polycrystalline material, form polycrystalline grid, and carry out polycrystal etching, make institute
State the second N-type epitaxy layer, described second oxide layer maintains an equal level with the surface of described polycrystalline grid；
At described second N-type epitaxy layer, described second oxide layer and the surface deposition oxygen of described polycrystalline grid
Compound dielectric layer；
After described medium of oxides layer is performed etching, between two the first adjacent grooves, carry out groove quarter
Erosion, forms the second groove；
Fill on the surface of described second N-type epitaxy layer, described medium of oxides layer and described second groove
Metal, is formed and covers described second N-type epitaxy layer, described medium of oxides layer and described second groove
Metal level.
Wherein, described second oxide layer is grid oxic horizon.
For solving above-mentioned technical problem, embodiments of the invention also provide for a kind of VDMOS device, including:
N-type substrate layer；
In epontic first N-type epitaxy layer of described N-type substrate layer；
At described first N-type epitaxy layer epontic p-type epitaxial layer；
The second N-type epitaxy layer in the growth of described p-type epi-layer surface；
It is formed at described second N-type epitaxy layer and the first groove of described p-type epitaxial layer presumptive area, institute
The sidewall stating the first groove is marked with concentration regulation impurity, and the bottom of described first groove extends to a described N
In type epitaxial layer；
Have in the second oxide layer, and described first groove in described first flute surfaces growth and be filled with polycrystalline material
Material, forms polycrystalline grid, wherein said second N-type epitaxy layer, described second oxide layer and described polycrystalline
The surface of grid maintains an equal level；
Surface deposition at described second N-type epitaxy layer, described second oxide layer and described polycrystalline grid has
The second groove is had between medium of oxides layer, and two the first adjacent grooves；
It is coated with in described second N-type epitaxy layer, described medium of oxides layer and described second flute surfaces
Metal level.
Wherein, the resistance value of described first N-type epitaxy layer is more than the first preset value, described p-type epitaxial layer
And the resistance value of described second N-type epitaxy layer is less than the second preset value.
Wherein, described concentration adjustment impurity is N-type impurity.
Wherein, described second oxide layer is grid oxic horizon.
Having the beneficial effect that of the technique scheme of the present invention:
The manufacture method of the VDMOS device of the embodiment of the present invention, first on N-type substrate layer surface successively
Grow the first N-type epitaxy layer, p-type epitaxial layer, the second N-type epitaxy layer and the first oxide layer, then enter
The etching of row the first groove, and the sidewall implantation concentration of the first groove is regulated impurity, then remove removing oxide layer,
And growth regulation dioxide layer, polycrystalline grid, medium of oxides layer and metal level, complete the follow-up making of device.
Use dense doped epitaxial floor (p-type epitaxial layer) to instead of conventional bulk district, and carry out raceway groove regulation injection, have
Effect improves the EAS ability of device, does not interferes with other parameters of device simultaneously.
Accompanying drawing explanation
Fig. 1 represents the manufacture method flow chart of the VDMOS device of the embodiment of the present invention；
What Fig. 2 represented the manufacture method of the VDMOS device of the embodiment of the present invention realizes schematic diagram 1；
What Fig. 3 represented the manufacture method of the VDMOS device of the embodiment of the present invention realizes schematic diagram 2；
What Fig. 4 represented the manufacture method of the VDMOS device of the embodiment of the present invention realizes schematic diagram 3；
What Fig. 5 represented the manufacture method of the VDMOS device of the embodiment of the present invention realizes schematic diagram 4；
What Fig. 6 represented the manufacture method of the VDMOS device of the embodiment of the present invention realizes schematic diagram 5；
What Fig. 7 represented the manufacture method of the VDMOS device of the embodiment of the present invention realizes schematic diagram 6；
What Fig. 8 represented the manufacture method of the VDMOS device of the embodiment of the present invention realizes schematic diagram 7；
What Fig. 9 represented the manufacture method of the VDMOS device of the embodiment of the present invention realizes schematic diagram 8；
Figure 10 represents the structural representation of the VDMOS device of the embodiment of the present invention.
Description of reference numerals:
1-N type substrate layer, 2-the first N-type epitaxy layer, 3-P type epitaxial layer, 4-the second N-type epitaxy layer,
5-the first oxide layer, 6-the first groove, 7-concentration regulation impurity, 8-the second oxide layer, 9-polycrystalline grid,
10-medium of oxides layer, 11-the second groove, 12-metal level.
Detailed description of the invention
For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, below in conjunction with attached
Figure and specific embodiment are described in detail.
The EAS of general VDMOS device lost efficacy and had both of which, and cause thermal damage and parasitic triode conducting are damaged
Bad.Parasitic triode conducting damage refer to device one parasitic audion of existence itself (epitaxial layer-body district-
Source region), when the device is switched off, when the reverse current between source and drain flows through body district, produce pressure drop.If this pressure
Fall is more than the cut-in voltage of parasitic triode, then this reverse current can be because the amplification of audion be by parasitism
Triode ON, causes out of control, and now, grid voltage can not turn off VDMOS.
For from principle, produce for preventing EAS to lose efficacy, it is important to prevent the triode ON of parasitism,
Then have to reduce body district resistance or increase source region and the short circuit area in body district.But VDMOS device at present
In the manufacture method of part, owing to deep body offset is close to channel region, it is contemplated that the problem of device cut-in voltage,
The overrich or the deepest that can not be done in Shen Ti district, this just brings the biggest difficulty to optimised devices EAS ability.
The manufacture method of the VDMOS device of the embodiment of the present invention, uses dense doped epitaxial layer to instead of biography
Tong Ti district, and carry out raceway groove regulation injection, it is effectively improved the EAS ability of device, does not interferes with simultaneously
Other parameters of device.
As it is shown in figure 1, the manufacture method of the VDMOS device of the embodiment of the present invention, including:
Step 101, in N-type substrate layer 1 superficial growth the first N-type epitaxy layer 2；
Step 102, at described first N-type epitaxy layer 2 superficial growth p-type epitaxial layer 3；
Step 103, in described p-type epitaxial layer 3 superficial growth the second N-type epitaxy layer 4；
Step 104, in described second N-type epitaxy layer 4 superficial growth the first oxide layer 5；
Step 105, to described first oxide layer 5, described second N-type epitaxy layer 4 and described p-type extension
The part of layer 3 presumptive area performs etching, and forms the first groove 6, the bottom of described first groove 6 and institute
State the difference in height between the bottom of p-type epitaxial layer 3 in preset range；
Step 106, regulates impurity to the sidewall implantation concentration of described first groove 6；
Step 107, proceeds etching, makes the bottom of described first groove 6 prolong described first groove 6
Extend in described first N-type epitaxy layer 2；
Step 108, removes described first oxide layer 5, and growth regulation dioxide layer 8, polycrystalline grid 9, oxygen
Compound dielectric layer 10 and metal level 12.
The manufacture method of the VDMOS device of the embodiment of the present invention, first depends on N-type substrate layer 1 surface
Secondary growth the first N-type epitaxy layer 2, p-type epitaxial layer the 3, second N-type epitaxy layer 4 and the first oxide layer 5,
Then carry out the etching of the first groove 6, and the sidewall implantation concentration of the first groove 6 is regulated impurity, then go
Removing oxide layer, and growth regulation dioxide layer 8, polycrystalline grid 9, medium of oxides layer 10 and metal level 12,
Complete the follow-up making of device.Dense doped epitaxial floor (p-type epitaxial layer 3) is used to instead of conventional bulk district,
And carry out raceway groove regulation injection, it is effectively improved the EAS ability of device, does not interferes with device its simultaneously
His parameter.
Preferably, the resistance value of described first N-type epitaxy layer 2 is more than the first preset value, outside described p-type
Prolong the resistance value of layer 3 and described second N-type epitaxy layer 4 less than the second preset value.
Now, the first N-type epitaxy layer 2 is resistive formation, can be used for undertaking device pressure-bearing；P-type epitaxial layer 3
For low-resistance P-type layer, can be as device low resistance body district；Second N-type epitaxy layer 4 is low-resistance N-type region, can
As device source region.Three layers of epitaxial layer cooperate, and the performance of device has been better achieved.
Wherein, the first oxide layer 5 can tilt, as the mask layer of follow-up etching groove and groove, the screen injected
Covering layer, thickness may be configured as 5000-8000A.
Further, in above-mentioned steps 106, due to the shielding action of the first oxide layer 5, can use from right
Quasi-mode is to the first groove 6 sidewall slope implantation concentration regulation impurity, thus is effectively saved device cost.
Wherein, it can be N-type impurity that described concentration adjusts impurity, such as P or As etc., in order to carry out channel concentration
Regulation, thus improve the EAS ability of device.
In the specific embodiment of the present invention, as it is shown on figure 3, the step of above-mentioned steps 105 may include that
Step 1051, to described first oxide layer 5, described second N-type epitaxy layer 4 and described p-type outside
Prolong after the part of layer 3 presumptive area carries out photoetching, then perform etching, form the first groove 6；
Step 1052, after forming described first groove 6, removes photoresist.
Wherein, the bottom of the first groove 6 should keep consistent with the bottom of p-type epitaxial layer 3 as far as possible, can control
Difference in height between the two is in preset range, within 0.1um.
In the specific embodiment of the present invention, as illustrated in figures 6-10, the step of above-mentioned steps 108 may include that
Step 1081, at described second N-type epitaxy layer 4 and described first groove 6 superficial growth the second oxygen
Change layer 8；
Step 1082, fills polycrystalline material in described first groove 6, forms polycrystalline grid 9, and carry out
Polycrystal etching, makes described second N-type epitaxy layer 4, described second oxide layer 8 and described polycrystalline grid 9
Surface maintains an equal level；
Step 1083, at described second N-type epitaxy layer 4, described second oxide layer 8 and described polysilicon gate
The surface deposition medium of oxides layer 10 of pole 9；
Step 1084, after performing etching described medium of oxides layer 10, at two the first adjacent grooves
Carry out etching groove between 6, form the second groove 11；
Step 1085, at described second N-type epitaxy layer 4, described medium of oxides layer 10 and described second
The surface filler metal of groove 11, is formed and covers described second N-type epitaxy layer 4, described medium of oxides
Layer 10 and the metal level 12 of described second groove 11.
Now, completed the making of grid oxygen, polycrystalline grid etc. by above-mentioned steps after, VDMOS is i.e. completed
The making of device.
Wherein, described second oxide layer 8 is grid oxic horizon.
Below the specific embodiment of the present invention is illustrated below.
First the manufacture method of the VDMOS device of the embodiment of the present invention, as in figure 2 it is shown, serve as a contrast in N-type
Bottom 1 superficial growth the first N-type epitaxy layer 2；Again outside the first N-type epitaxy layer 2 superficial growth p-type
Prolong layer 3；Then in p-type epitaxial layer 3 superficial growth the second N-type epitaxy layer 4；Again in the second N-type extension
Layer 4 superficial growth the first oxide layer 5.Wherein, the first N-type epitaxy layer 2 is resistive formation, in order to undertake device
Part pressure-bearing；P-type epitaxial layer 3 is low resistivity layer, follow-up as low resistance body district；Second N-type epitaxy layer 4
For low resistivity layer, in order to become device source region.First oxide layer 5 as follow-up etching groove mask layer and
Groove tilts the screen layer injected, and thickness is 5000-8000A.
Next step, as it is shown on figure 3, to the first oxide layer the 5, second N-type epitaxy layer 4 and p-type epitaxial layer
After the part of 3 presumptive areas carries out photoetching, then carry out etching groove, form the first groove 6, and ensure
Difference in height between bottom and the bottom of p-type epitaxial layer 3 of one groove 6 is within 0.1um；Formed described
After first groove 6, remove photoresist.
Next step, as shown in Figure 4, use self-aligned manner to tilt to inject N the sidewall of the first groove 6
Type impurity, to be adjusted groove concentration.
Next step, as it is shown in figure 5, continue to perform etching the first groove 6, make the bottom of the first groove 6
Extend in the first N-type epitaxy layer 2, and remove the first oxide layer 5 after etching.
Next step, as shown in Figure 6, at the second N-type epitaxy layer 4 and the first groove 6 superficial growth grid
Oxide layer.
Next step, as it is shown in fig. 7, fill polycrystalline material in the first groove 6, form polycrystalline grid 9,
And carry out polycrystal etching, make the second N-type epitaxy layer 4, grid oxic horizon maintain an equal level with the surface of polycrystalline grid 9.
Next step, as shown in Figure 8, at the second N-type epitaxy layer 4, grid oxic horizon and polycrystalline grid 9
Surface deposition medium of oxides layer 10.
Next step, as it is shown in figure 9, after medium of oxides layer 10 is performed etching, at two adjacent
Carry out etching groove between one groove 6, form the second groove 11.
Next step, fill on the second N-type epitaxy layer 4, medium of oxides layer 10 and the second groove 6 surface
Metal, is formed and covers the second N-type epitaxy layer 4, medium of oxides layer 10 and the metal level of the second groove 6
12。
So far, complete the making of VDMOS device, obtain VDMOS device as described in Figure 10.
The manufacture method of the VDMOS device of the embodiment of the present invention, optimizes VDMOS Making programme,
Use dense doped epitaxial floor (p-type epitaxial layer 3) to replace conventional bulk district, and carry out raceway groove regulation injection, have
Effect improves the EAS ability of device, does not interferes with other parameters of device simultaneously.And have employed autoregistration
The mode that regulation is injected, is effectively saved the cost of device.
As shown in Figure 10, embodiments of the invention additionally provide a kind of VDMOS device, including:
N-type substrate layer 1；
In epontic first N-type epitaxy layer 2 of described N-type substrate layer 1；
At described first N-type epitaxy layer 2 epontic p-type epitaxial layer 3；
In epontic second N-type epitaxy layer 4 of described p-type epitaxial layer 3；
It is formed at described second N-type epitaxy layer 4 and the first groove 6 of described p-type epitaxial layer 3 presumptive area,
The sidewall of described first groove 6 is marked with concentration regulation impurity, and the bottom of described first groove 6 extends to described
In first N-type epitaxy layer 2；
Have in the second oxide layer 8, and described first groove 6 in described first groove 6 superficial growth and be filled with
Polycrystalline material, forms polycrystalline grid 9, wherein said second N-type epitaxy layer 4, described second oxide layer 8
Maintain an equal level with the surface of described polycrystalline grid 9；
Form sediment on the surface of described second N-type epitaxy layer 4, described second oxide layer 8 and described polycrystalline grid 9
Amass to have between oxide dielectric layer 10, and two the first adjacent grooves 6 and have the second groove 11；
On described second N-type epitaxy layer 4, described medium of oxides layer 10 and described second groove 11 surface
It is coated with metal level 12.
Wherein, the resistance value of described first N-type epitaxy layer 2 is more than the first preset value, described p-type extension
The resistance value of layer 3 and described second N-type epitaxy layer 4 is less than the second preset value.
Preferably, described concentration adjustment impurity is N-type impurity.
Wherein, described second oxide layer 8 is grid oxic horizon.
The VDMOS device of the embodiment of the present invention, uses dense doped epitaxial layer (p-type epitaxial layer 3) to replace
Conventional bulk district, and carry out raceway groove regulation injection, it is effectively improved the EAS ability of device, simultaneously will not shadow
Other parameters of Chinese percussion instrument part.
It should be noted that this VDMOS device is to apply manufacturer's legal system of above-mentioned VDMOS device
Making, the implementation of the manufacture method embodiment of above-mentioned VDMOS device is applicable to this VDMOS
Device, also can reach identical technique effect.
The above is the preferred embodiment of the present invention, it is noted that for the common skill of the art
For art personnel, on the premise of without departing from principle of the present invention, it is also possible to make some improvements and modifications,
These improvements and modifications also should be regarded as protection scope of the present invention.
Claims (10)
1. the manufacture method of a VDMOS device, it is characterised in that including:
In N-type substrate layer superficial growth the first N-type epitaxy layer；
At described first N-type epitaxy layer superficial growth p-type epitaxial layer；
The second N-type epitaxy layer is grown in described p-type epi-layer surface；
In described second N-type epitaxy layer superficial growth the first oxide layer；
To described first oxide layer, described second N-type epitaxy layer and described p-type epitaxial layer presumptive area
Part performs etching, and forms the bottom of the first groove, the bottom of described first groove and described p-type epitaxial layer
Between difference in height in preset range；
The sidewall implantation concentration of described first groove is regulated impurity；
Described first groove is proceeded etching, makes the bottom of described first groove extend to a described N
In type epitaxial layer；
Remove described first oxide layer, and growth regulation dioxide layer, polycrystalline grid, medium of oxides layer and gold
Belong to layer.
Manufacture method the most according to claim 1, it is characterised in that described first N-type epitaxy layer
Resistance value more than the first preset value, described p-type epitaxial layer and the resistance value of described second N-type epitaxy layer
Less than the second preset value.
Manufacture method the most according to claim 1, it is characterised in that described concentration adjustment impurity is
N-type impurity.
Manufacture method the most according to claim 1, it is characterised in that described to described first oxidation
The part of layer, described second N-type epitaxy layer and described p-type epitaxial layer presumptive area performs etching, and is formed
First groove, including:
To described first oxide layer, described second N-type epitaxy layer and described p-type epitaxial layer presumptive area
After part carries out photoetching, then perform etching, form the first groove；
After forming described first groove, remove photoresist.
Manufacture method the most according to claim 1, it is characterised in that described growth regulation dioxide layer,
Polycrystalline grid medium of oxides layer and metal level, including:
At described second N-type epitaxy layer and described first flute surfaces growth regulation dioxide layer；
In described first groove, fill polycrystalline material, form polycrystalline grid, and carry out polycrystal etching, make institute
State the second N-type epitaxy layer, described second oxide layer maintains an equal level with the surface of described polycrystalline grid；
At described second N-type epitaxy layer, described second oxide layer and the surface deposition oxygen of described polycrystalline grid
Compound dielectric layer；
After described medium of oxides layer is performed etching, between two the first adjacent grooves, carry out groove quarter
Erosion, forms the second groove；
Fill on the surface of described second N-type epitaxy layer, described medium of oxides layer and described second groove
Metal, is formed and covers described second N-type epitaxy layer, described medium of oxides layer and described second groove
Metal level.
Manufacture method the most according to claim 1, it is characterised in that described second oxide layer is grid
Pole oxide layer.
7. a VDMOS device, it is characterised in that including:
N-type substrate layer；
In epontic first N-type epitaxy layer of described N-type substrate layer；
At described first N-type epitaxy layer epontic p-type epitaxial layer；
The second N-type epitaxy layer in the growth of described p-type epi-layer surface；
It is formed at described second N-type epitaxy layer and the first groove of described p-type epitaxial layer presumptive area, institute
The sidewall stating the first groove is marked with concentration regulation impurity, and the bottom of described first groove extends to a described N
In type epitaxial layer；
Have in the second oxide layer, and described first groove in described first flute surfaces growth and be filled with polycrystalline material
Material, forms polycrystalline grid, wherein said second N-type epitaxy layer, described second oxide layer and described polycrystalline
The surface of grid maintains an equal level；
Surface deposition at described second N-type epitaxy layer, described second oxide layer and described polycrystalline grid has
The second groove is had between medium of oxides layer, and two the first adjacent grooves；
It is coated with in described second N-type epitaxy layer, described medium of oxides layer and described second flute surfaces
Metal level.
VDMOS device the most according to claim 7, it is characterised in that outside described first N-type
Prolong the resistance value of layer more than the first preset value, described p-type epitaxial layer and the electricity of described second N-type epitaxy layer
Resistance is less than the second preset value.
VDMOS device the most according to claim 7, it is characterised in that described concentration is adjusted miscellaneous
Matter is N-type impurity.
VDMOS device the most according to claim 7, it is characterised in that described second oxidation
Layer is grid oxic horizon.
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| US20080283909A1 (en) * | 2007-05-18 | 2008-11-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
| US20090061584A1 (en) * | 2007-08-27 | 2009-03-05 | Wei-Chieh Lin | Semiconductor Process for Trench Power MOSFET |
| CN102254825A (en) * | 2010-05-20 | 2011-11-23 | 国际整流器公司 | Method for fabricating a shallow and narrow trench fet and related structures |
| JP2013219161A (en) * | 2012-04-09 | 2013-10-24 | Mitsubishi Electric Corp | Semiconductor device and semiconductor device manufacturing method |
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- 2015-04-29 CN CN201510213867.XA patent/CN106206299A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080283909A1 (en) * | 2007-05-18 | 2008-11-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
| US20090061584A1 (en) * | 2007-08-27 | 2009-03-05 | Wei-Chieh Lin | Semiconductor Process for Trench Power MOSFET |
| CN102254825A (en) * | 2010-05-20 | 2011-11-23 | 国际整流器公司 | Method for fabricating a shallow and narrow trench fet and related structures |
| JP2013219161A (en) * | 2012-04-09 | 2013-10-24 | Mitsubishi Electric Corp | Semiconductor device and semiconductor device manufacturing method |
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