CN105244277A - Junction-free field effect transistor and formation method thereof - Google Patents
Junction-free field effect transistor and formation method thereof Download PDFInfo
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- CN105244277A CN105244277A CN201410298265.4A CN201410298265A CN105244277A CN 105244277 A CN105244277 A CN 105244277A CN 201410298265 A CN201410298265 A CN 201410298265A CN 105244277 A CN105244277 A CN 105244277A
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Abstract
The invention provides a junction-free field effect transistor and a formation method thereof. The formation method comprises the steps of providing a substrate with a first region and a second region; forming a first doped region and a second doped region; removing part of the substrate so as to form a first opening and a second opening; and filling with openings with a metal containing material layer so as to form a source region and a drain region in the first opening and the second opening respectively. The invention further provides a junction-free field effect transistor, which comprises a substrate, a first doped region, a second doped region, a first gate structure, a second gate structure, a first opening and a second opening, and is characterized in that the first opening and the second opening are internally provided with metal containing material layers which act as a source region and a drain region respectively. The beneficial effects of the invention lie in that contact resistance between the source/drain region and a conductive plug is small, turn-on current is increased, and the performance of the junction-free field effect transistor is improved; and the difficulty of a doping process is simplified, and the degree of an interface scattering problem possibly occurred in the doped regions is reduced to a certain extent.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of without junction field effect transistor and forming method thereof.
Background technology
Metal-oxide layer semiconductcor field effect transistor (MetalOxideSemiconductorFieldEffectTransistor, MOSFET) in except comprising source-drain area, grid, in the channel region between source-drain area, also there is the channel junction (junction) of such as PN junction, heterojunction etc.
Along with the characteristic size of MOSFET reduce gradually, increasing problem starts to manifest gradually.Such as, along with the size of MOSFET reduces, MOSFET electric leakage degree operationally increases.
In addition, in order to improve the performance of MOSFET further, the resistance reduced between source-drain area is also one of comparatively crucial problem as best one can.In general, the doping level of the size or adjustment source-drain area that reduce grid can reduce the resistance between source-drain area to a certain extent.
But along with the reduction of characteristic size, the difficulty of doping process increases, along with the increase of doping process difficulty, comparatively difficulty is become by the doping resistance reduced between source-drain area, and the size reducing grid means that the size of channel region also diminishes accordingly, this may aggravate the short-channel effect of MOSFET.
In addition, the source-drain area due to MOSFET of the prior art is the semi-conducting material of doping, when the conductive plunger that follow-up formation is connected with source-drain area, there is larger contact resistance between conductive plunger (being generally metal material) and source-drain area.
The problems affect such as the resistance between transistor leakage, source-drain area is comparatively large, between conductive plunger and source-drain area contact resistance the is larger performance of transistor.
Summary of the invention
The problem that the present invention solves is to provide a kind of without junction field effect transistor and forming method thereof, to optimize the performance of transistor.
In order to solve the problem, the invention provides a kind of formation method without junction field effect transistor, comprising:
There is provided substrate, described substrate has first area and second area;
Carry out the first doping to form the first doped region to the substrate of described first area, carry out the second doping to form the second doped region to the substrate of described second area, described first doping is different from described second doping type;
Substrate is formed first grid structure and second grid structure, makes described first grid structure corresponding with the position of described first doped region, and make second grid structure corresponding with the position of described second doped region;
The substrate of removal between described first and second grid structures to form the first opening, and forms the second opening respectively in the substrate of first grid structure away from second grid structure side and in the substrate of second grid structure away from first grid structure side;
The material layer containing metal is filled in described first opening and the second opening, be total to drain region to be formed in described first opening and form source region in described second opening, or, in described first opening, form common source district and form drain region in described second opening.
Optionally, the step of the material layer of filling containing metal in the first opening and the second opening comprises: the material layer forming aluminium, tungsten, copper, nickel, silver, gold, titanium, titanium nitride, ramet or alloy material.
Optionally, fill material layer containing metal in the opening with after the step forming source region or drain region, described formation method also comprises:
Annealing in process is carried out to the described material layer containing metal.
Optionally, the step of annealing in process comprises: adopt rapid thermal anneal process to carry out annealing in process to the described material layer containing metal.
Optionally, the step of substrate is provided to comprise:
Substrate is provided;
Form oxygen buried layer on the substrate;
Described oxygen buried layer forms semiconductor layer;
Remove the described semiconductor layer of part, to form fin;
The step forming the first and second doped regions comprises: in described fin, form described first and second doped regions respectively;
The step forming the first and second grid structures comprises: form the first grid structure across the first doped region in described fin, and makes first grid structure cover sidewall and the top of described fin; Form the second grid structure across the second doped region in described fin, and make second grid structure cover sidewall and the top of described fin;
The step forming the first and second openings comprises: remove fin between described first and second grid structures to form the first opening, and in the fin of first grid structure away from second grid structure side and in the fin of second grid structure away from first grid structure side, forming the second opening respectively, described first opening and the second opening expose described oxygen buried layer.
Optionally, the step of substrate is provided to comprise: the substrate providing silicon materials; The step forming oxygen buried layer comprises: form buried silicon oxide oxygen layer.
Optionally, the step forming oxygen buried layer comprises: make the thickness of described oxygen buried layer in the scope of 20 ~ 50 nanometers.
Optionally, the step described oxygen buried layer forming semiconductor layer comprises: the semiconductor layer forming silicon, germanium material.
Optionally, remove the described semiconductor layer of part, comprise with the step forming fin: remove the described semiconductor layer of part, make the thickness of the fin of formation in the scope of 10 ~ 100 nanometers.
Optionally, remove part of semiconductor layer, comprise with the step forming fin: Formation cross-section is the fin of triangle, rectangle or circle.
Optionally, the step forming the first and second doped regions comprises: the doping content of the first doped region and the second doped region is reduced gradually from substrate surface to substrate center.
Optionally, the step forming the first and second doped regions comprises: form the first doped region of arsenic doping and boron doped second ditch doped region.
Optionally, the step forming the first and second doped regions comprises:
Make the implant energy of arsenic in the scope of 5 ~ 40 kiloelectron-volts, and dopant dose is 1 × 10
16~ 5 × 10
16in the scope of square centimeter;
Make the implant energy of boron in the scope of 1 ~ 10 kiloelectron-volt, and dopant dose is 1 × 10
16~ 5 × 10
16in the scope of square centimeter.
In addition, the present invention also provides a kind of without junction field effect transistor, comprising:
Substrate, described substrate has first area and second area;
Second doped region of the first doped region being arranged in the substrate of first area and the substrate being arranged in second area, the doping type of described first and second doped regions is different;
Be positioned at the first grid structure on the substrate of the first doped region and be positioned at the second grid structure on described second doped region substrate;
Be formed with the first material layer containing metal in substrate between described first and second grid structures, be used as drain region altogether; First grid structure away from the second material layer be formed in the side of second grid structure and the substrate of second grid structure away from the side of first grid structure containing metal, as source region; Or the first material layer is used as common source district, the second material layer is used as drain region.
Optionally, described substrate comprises:
Substrate;
Be formed at described suprabasil oxygen buried layer;
Be formed at the first fin on described oxygen buried layer and the second fin, the first fin and the second fin adulterate the ion of different doping type respectively;
Described first grid structure across described first fin, and covers sidewall and the top of described first fin, and described second grid structure across described second fin, and covers sidewall and the top of described second fin;
Described first material layer is between described first fin and the second fin, and described second material layer is positioned at described first fin away from the side of described first material layer and the described second fin side away from described first material layer.
Optionally, the material of described fin is silicon or germanium material.
Optionally, the cross section of described fin is triangle, rectangle or circle.
Optionally, the doping content of described first doped region and the second doped region reduces gradually from substrate surface to substrate center.
Optionally, described first doped region is arsenic doping district, and described second doped region is boron doped region.
Optionally, the material of the described material layer containing metal is aluminium, tungsten, copper, nickel, silver, gold, titanium, titanium nitride, ramet or alloy material.
Compared with prior art, technical scheme of the present invention has the following advantages:
Removal is positioned at the section substrate of described first and second grid structure both sides to form the first and second openings, in described first and second openings, then fills the material layer containing metal, to form source region, drain region, common source district or common drain region.Because the resistance of metal is much smaller than the resistance of semi-conducting material, this source-drain area is compared to the source-drain area of semi-conducting material of the prior art, on the one hand, source region, contact resistance between drain region and the follow-up conductive plunger that will be formed are less, form the contact layer of the silicide reducing contact resistance without the need to setting process step extra as prior art; On the other hand, resistance between source region and drain region is relatively little, that is to say, under onesize cut-in voltage, firing current increases relatively, this is conducive to improving the performance (such as, improving the electric leakage degree etc. when turning off without junction field effect transistor) without junction field effect transistor to a certain extent.
In addition, technical scheme of the present invention forms the first and second different doped regions of doping type respectively in described substrate, and namely the first and second doped regions doping type is separately identical, and this simplifies the difficulty of doping process to a certain extent; Simultaneously, the source-drain area formed is positioned at the first and second both sides, doped region, that is under transistor state, channel region between source-drain area is all through the first or second doped region of overdoping, such charge carrier almost can be distributed in the middle of whole first and second doped regions, can reduce the degree of contingent interface scattering problem in doped region relative to existing field-effect transistor to a certain extent.
Further, the doping content of the first doped region and the second doped region is reduced gradually from substrate surface to substrate center, is conducive to the shutoff without junction field effect transistor, and then reduce electric leakage degree.Its reason is, when turning off without junction field effect transistor, because electric field strength and distance are inversely proportional to, more less away from doped region surface field intensity, namely away from the charge carrier on surface, doped region compare be not easy depleted; The present invention makes doping content reduce gradually from substrate surface to substrate center, and decrease the quantity of the charge carrier away from surface, doped region to a certain extent, the charge carrier be conducive to like this away from surface, doped region is depleted as best one can when turning off without junction field effect transistor, and then when reducing to turn off without junction field effect transistor, the probability of electric leakage occurs.
Accompanying drawing explanation
Fig. 1 is the structural representation of the present invention without junction field effect transistor one embodiment;
Fig. 2 and Fig. 3 is Fig. 1 along the structural representation in A-A` direction and B-B` direction respectively;
Fig. 4 to Figure 14 is the structural representation of the present invention without each step in formation method one embodiment of junction field effect transistor;
Figure 15 is that the present invention is without the schematic diagram in junction field effect transistor one embodiment during specific works.
Embodiment
Because the existing characteristic size without junction field effect transistor (such as MOSFET) reduces gradually, the difficulty for doping process during making MOSFET also little by little increases.
Meanwhile, because the source-drain area of existing MOSFET is generally semi-conducting material, the resistance between source-drain area is difficult to improve always; And there is larger contact resistance between the conductive plunger in semi-conducting material and interconnection structure, generally need extra process step to form the suicide contact layer reducing contact resistance on source-drain area.
In addition, when MOSFET is in running order, interface scattering (surfacescattering) phenomenon of the generation of charge carrier in channel region also becomes comparatively serious, interface scattering phenomenon can affect the service behaviour without junction field effect transistor to a certain extent, such as, noise change when causing MOSFET to work is large.
So in order to solve the problem, the invention provides a kind of without junction field effect transistor, in the present embodiment, comprising following structure:
Substrate, described substrate has first area and second area;
Second doped region of the first doped region being arranged in the substrate of first area and the substrate being arranged in second area, the doping type of described first and second doped regions is different;
Be positioned at the first grid structure on the substrate of the first doped region and be positioned at the second grid structure on described second doped region substrate;
Be formed with the first material layer containing metal in substrate between described first and second grid structures, be used as drain region altogether; First grid structure away from the second material layer be formed in the side of second grid structure and the substrate of second grid structure away from the side of first grid structure containing metal, as source region; Or the first material layer is used as common source district, the second material layer is used as drain region.
Because the resistance of metal is much smaller than the resistance of semi-conducting material, the source-drain area that the source-drain area adopting the material layer containing metal to be formed is formed by semi-conducting material in prior art, on the one hand, contact resistance between source-drain area and the follow-up conductive plunger that will be formed can relatively diminish, thus without the need to forming the contact layer of the silicide reducing contact resistance to extra setting process step in the prior art.
On the other hand, the resistance between the source-drain area of the material layer formation of metal also diminishes accordingly, this means that firing current increases relatively under same cut-in voltage.Electric current is relatively increased in and is conducive to a certain extent improving the performance (such as improving the electric leakage degree etc. when turning off without junction field effect transistor) without junction field effect transistor.
In addition, the first doped region and the second doped region doping type difference, that is the first doped region and the second doped region are same kind doping separately, and this simplifies the difficulty of doping process to a certain extent.
Simultaneously, the source-drain area formed is positioned at the first and second both sides, doped region, that is under transistor state, channel region between source-drain area is all through the first doped region or second doped region of overdoping, such charge carrier almost can be distributed in the middle of whole first and second doped regions, the degree of contingent interface scattering (surfacescattering) problem in doped region can be reduced to a certain extent relative to existing field-effect transistor, its reason is, existing field-effect transistor is generally only distributed in the surface of channel region for the doping of channel region, when this existing field-effect transistor work, charge carrier is also only concentrate on surface, channel region, this can make the degree of generation interface scattering larger.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Referring to figs. 1 to Fig. 3, in the present embodiment, the structural representation without junction field effect transistor of the present invention.
First with reference to figure 1, for of the present invention without the structural representation of junction field effect transistor in an embodiment, combine with reference to figure 2 and Fig. 3, wherein, Fig. 2 is the cutaway view of Fig. 1 along A-A` direction simultaneously, Fig. 3 be Fig. 1 along B-B` to cutaway view.As can be seen from the figure, in the present embodiment, described fin field-effect transistor (FinField-EffectTransistor, the FinFET) structure being specially complementary type without junction field effect transistor, describedly comprises without junction field effect transistor:
Substrate, described substrate comprises substrate 1, oxygen buried layer 2 and fin 3, and in Fig. 1 of the present embodiment, described fin 3 comprises the first fin and the second fin.
Described substrate has first area 10 and second area 20, is respectively used to be formed P type without junction field effect transistor or N-type without junction field effect transistor.
Described oxygen buried layer 2 is formed at the surface of substrate 1; Described fin 3 is formed at described oxygen buried layer 2 surface, and is arranged in first area 10 and the second area 20 of described substrate.
Concrete, can adopt the substrate of silicon materials in the present embodiment, accordingly, described oxygen buried layer 2 can be silicon dioxide oxygen buried layer.But it should be noted that, be prior art, the present invention does not repeat this, is not also limited in any way herein.
In the present embodiment, the material of described fin 3 can be the semi-conducting material such as silicon or germanium.But the present invention is to this and be not construed as limiting, other III-V material such as indium gallium arsenic (InGaAs) etc. also can as the material of described fin 3.
In addition, in the present embodiment, the cross section of described fin 3 is also not limited only to the rectangle shown in figure, and in other embodiments of the invention, also can be other shape such as triangle or circle, the present invention limit this.
First fin and the second fin adulterate the ion of different doping type respectively, and then form the first doped region 6 and the second doped region 7; Described first doped region 6 and the second doped region 7 lay respectively in first area 10 and second area 20.Because between the first doped region 6 from the second doped region 7, doping type is different, namely the first and second doped regions doping type is separately identical, and this simplifies the difficulty of the doping process when making first area 10 and second area 20 to a certain extent.
On the other hand, source-drain area is positioned at the first and second both sides, doped region, that is of the present invention in running order without junction field effect transistor time, channel region between source-drain area is all through the first doped region 6 or the second doped region 7 of overdoping, that is, charge carrier can almost be distributed in the middle of whole first doped region 6 and the second doped region 7, relative to existing field-effect transistor, the degree of contingent interface scattering problem in doped region can be reduced to a certain extent, its reason is, existing field-effect transistor is generally only distributed in the surface of channel region for the doping of channel region, when this existing field-effect transistor work, charge carrier also focuses only on surface, channel region, the degree that interface scattering occurs is larger.
Concrete, in the present embodiment, described first doped region 6 is arsenic (As) doping of N-type dopant, boron (B) doping that described 7, second doped region is the P type alloy that corresponds, but which kind of element the present invention adopts carry out N-type or P type adulterates and is not construed as limiting to concrete; Simultaneously, also not limiting must be that the first doped region 6 is carried out to N-type doping, carried out the doping of P type to the second doped region 7, doping type between one doped region 6 and the second doped region 7 can exchange, that is, in other embodiments of the invention, also can be that the first doped region 6 is carried out to the doping of P type, carried out N-type doping to the second doped region 7.
In addition, in the present embodiment, the doping content of the first doped region 6 and the second doped region 7 reduces gradually from substrate surface to substrate center, is conducive to the shutoff without junction field effect transistor of the present invention like this, and then reduces electric leakage degree.Its reason is, scene effect transistor turn off time, based on the principle that electric field strength and distance are inversely proportional to, from surface, doped region more away from, electric field strength is correspondingly less, and the charge carrier that is away from surface, doped region is not easy depleted; The present invention makes the doping content of the first doped region 6 and the second doped region 7 reduce gradually from substrate surface to substrate center, and decrease the quantity of the charge carrier away from channel region upper surface, the charge carrier be conducive to like this away from doped region upper surface is depleted as best one can, and then when reducing to turn off without junction field effect transistor, the probability of electric leakage occurs.
In addition, in the present embodiment, the doping content on described first channel region 6 and the second surface, channel region 7 is greater than or equal to 1 × 10
19atoms per cubic centimeter, the first and second channel regions 6 and 7 within the scope of this doping content are formed than being easier to, simultaneously also better without junction field effect transistor performance operationally.But it should be noted that, above span is only the present embodiment and adopts to illustrate, the present invention is to concrete doping content and do not limit.
The present embodiment also comprise the first and second grid structures 4 without junction field effect transistor, be across on described first fin and the second fin respectively, the position of described first and second grid structures 4 is corresponding with described first doped region 6 and the second doped region 7, that is, described first grid structure across described first fin, and is covered in sidewall and the top of described first fin; Second grid structure across described second fin, and covers sidewall and the top of described second fin.
In the present embodiment, described first and second grid structures 4 comprise grid 41, grid oxide layer 43 and are formed at the side wall 42 of described gate lateral wall.
The present embodiment also comprise the first material layer 32 and the second material layer 31,33 without junction field effect transistor, wherein said first material layer 32 is located at the first material layer 32 containing metal between described first and second grid structures in substrate, and described first material layer 32 is used as drain region altogether; Now, first grid structure away from the side of second grid structure and second grid structure away from the second material layer 31,33 containing metal in the substrate of the side of first grid structure, as source region; Or the first material layer 32 is used as common source district, corresponding second material layer 31,33 is used as drain region.
Because the source-drain area formed comprises (drain region or common source district altogether, and source region or drain region) containing metal, be conducive to the contact resistance between the conductive plunger (not shown) that reduces to be formed in described source-drain area and subsequent step like this, and without the need to picture additionally formed in the prior art one deck reduce source-drain area and to contact resistance between conductive plunger suicide contact layer this simplify technological process to a certain extent.
In addition, relative to prior art, resistance between source-drain area containing metal also can obtain reduction to a certain degree, resistance between source-drain area reduces to mean under same cut-in voltage, firing current becomes large, this is conducive to improving the performance (such as, improving the electric leakage degree etc. when turning off without junction field effect transistor) without junction field effect transistor to a certain extent.
Further, in the present embodiment, aluminium, tungsten, copper, nickel, silver, gold, titanium, titanium nitride, ramet or alloy material etc. can be adopted to form the described material layer containing metal.But the present invention is not construed as limiting this, other metal or the material containing metal equally can as the materials in source region of the present invention and drain region.
In addition it should be noted that, above-mentioned FinFET structure be only the embodiment that the present invention plays signal effect without junction field effect transistor, in other embodiments of the invention, also can be other structure without junction field effect transistor, such as planar structure without junction field effect transistor.
In addition, the present invention also provides a kind of without junction field effect transistor and forming method thereof, can be, but not limited to formation above-mentioned without junction field effect transistor.
In the present embodiment, described formation method comprises the following steps:
There is provided substrate, described substrate has first area and second area; Carry out the first doping to form the first doped region to the substrate of described first area, carry out the second doping to form the second doped region to the substrate of described second area, described first doping is different from described second doping type; Substrate is formed first grid structure and second grid structure, makes described first grid structure corresponding with the position of described first doped region, and make second grid structure corresponding with the position of described second doped region; The substrate of removal between described first and second grid structures to form the first opening, and forms the second opening respectively in the substrate of first grid structure away from second grid structure side and in the substrate of second grid structure away from first grid structure side; The material layer containing metal is filled in described first opening and the second opening, be total to drain region to be formed in described first opening and form source region in described second opening, or, in described first opening, form common source district and form drain region in described second opening.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The present embodiment for formed FinFET structure in Fig. 1 to Fig. 3 without junction field effect transistor.
Fig. 6, Fig. 8, Figure 10 and Figure 14 for prepare shown in Fig. 1 without the cross-sectional view of each step during junction field effect transistor process along B-B` direction;
Fig. 4, Fig. 5, Fig. 7, Fig. 9, Figure 11 to Figure 13 and Figure 15 for prepare shown in Fig. 1 without the cross-sectional view of each step during junction field effect transistor process along A-A` direction.
First with reference to figure 4, provide substrate, and described substrate is had be respectively used to be formed P type without junction field effect transistor or N-type without the first area 11 of junction field effect transistor and second area 22.
In the present embodiment, the step of substrate is provided specifically to comprise:
Substrate 100 is provided; In the present embodiment, described substrate 100 adopts silicon as material.
Described substrate 100 forms oxygen buried layer 110; Because described substrate 100 adopts silicon as material, accordingly, described oxygen buried layer 110 can be the oxygen buried layer of silica material;
Concrete, can make the thickness of oxygen buried layer 110 in the scope of 20 ~ 50 nanometers, described like this oxygen buried layer while having adequate thickness isolation substrate 100 and the follow-up fin 200 that will be formed, can be unlikely to again blocked up and affects the whole structure without junction field effect transistor.But the present invention is to the material of oxygen buried layer 110 and thickness and be not construed as limiting, but should adjust according to actual conditions, the present invention does not repeat this, does not also do any restriction.
After the described oxygen buried layer of formation, described oxygen buried layer 110 forms semiconductor layer (not shown), and described semiconductor layer is for the formation of fin;
Concrete, in the present embodiment, silicon or germanium can be adopted to form described semiconductor layer as material, but the present invention is not construed as limiting to this, other III-V material such as indium gallium arsenic (InGaAs) etc. also can as the material of described semiconductor layer.
After the described semiconductor layer of formation, remove the described semiconductor layer of part to form described fin 200.
Fin 200 is now undoped state, and described fin 200 adulterates to form the first doped region and the second doped region for carrying out in subsequent steps, so of the present invention work without junction field effect transistor time form the first channel region and the second channel region.
In the present embodiment, can make the thickness of the fin 200 of formation in the scope of 10 ~ 100 nanometers.But this is only the thickness range adopted in the present embodiment, should adjust accordingly according to the size without junction field effect transistor during practical operation, the present invention is not limited in any way this.
With reference to figure 5 and Fig. 6, adulterate to form the first doped region 210, doped region 210, second to the part of fin 200 in first area 11 and second area 22 respectively.Wherein, first doping is carried out to form the first doped region 210 to the substrate of described first area, carry out the second doping to form the second doped region 220 to the substrate of described second area, described first and second doped regions 210,220 are for forming the first channel region when working without junction field effect transistor and the second channel region respectively.
Make the doping type between described first doped region 210 and the second doped region 220 different, that is, first doped region 210 and the second doped region 220 are material of the same race doping separately, follow-up work without junction field effect transistor time, to not exist " knot " in existing fieldistor channel district, this reach with existing without junction field effect transistor same purpose while, simplify the difficulty of doping process to a certain extent.
Concrete, in the present embodiment, described first doped region 210 is arsenic (As) doping of N-type dopant, described 220, second doped region is boron (B) doping of corresponding P type alloy, but the present invention carries out N-type to which kind of element of employing or P type adulterates and is not construed as limiting; Simultaneously, also not limiting must be that the first doped region 210 is carried out to N-type doping, carried out the doping of P type to the second doped region 220, doping type between one doped region 210 and the second doped region 220 can exchange, that is, in other embodiments of the invention, also can be that the first doped region 210 is carried out to the doping of P type, carried out N-type doping to the second doped region 220.
Further, the present embodiment can make the implant energy of arsenic in the scope of 5 ~ 40 kiloelectron-volts, and dopant dose is 1 × 10
16~ 5 × 10
16in the scope of every square centimeter; And make the implant energy of boron in the scope of 1 ~ 10 kiloelectron-volt, and dopant dose is 1 × 10
16~ 5 × 10
16in the scope of every square centimeter.
But same, above-mentioned Doped ions and the parameter of doping process only adopted in the present embodiment, and the present invention does not limit concrete implant energy, dopant dose, but should adjust accordingly according to actual conditions.
In the present embodiment, when concrete operations, can first adopt mask layer (such as, be with figuratum photoresist etc.) block first area 11 or second area 22, then adulterated in the region be not blocked, then, remove mask and form new mask to block the region after doping, to adulterate to unadulterated region.Concrete doping process is prior art, and the present invention does not repeat this, does not also do any restriction.
In addition, in the present embodiment, the doping content of the first doped region 210 and the second doped region 220 can be made to reduce gradually from substrate surface to substrate center from the direction on vertical substrates surface, that is, in the present embodiment, doping content near fin 200 surface is higher, and close to fin 200 center, doping content is lower.Being conducive to when working without junction field effect transistor like this, as the first doped region 210 of the first and second channel regions and the shutoff of the second doped region 220, and then reducing electric leakage degree when turning off without junction field effect transistor.
Its reason is, when turning off without junction field effect transistor, because electric field strength and distance are inversely proportional to, more less away from channel region surface field intensity, the charge carrier away from surface, channel region is not easy depleted; The present invention makes doping content reduce gradually from substrate surface to substrate center, and decrease the quantity of the charge carrier away from surface, channel region, the charge carrier be conducive to like this away from surface, channel region is depleted as best one can, and then when reducing to turn off without junction field effect transistor, the probability of electric leakage occurs.
Specifically, can when adulterating to fin 200 in the present embodiment, the mode that limited surface source can be adopted to spread is adulterated to fin 200: form the doped layer with Doped ions respectively in the position that will form described first doped region 210 and the second doped region 220 respectively, then by the mode of high annealing, the Doped ions in doped layer is progressed in fin 200.Owing to adopting the ion doping in limited surface source diffusion (doped layer namely in the present embodiment) generally to follow Gaussian Profile, the first doped region 210 and the second doped region 220 that described doping content reduces gradually from substrate surface to substrate center so just can be formed.
In the present embodiment, the doping content on the first doped region 210 and the second surface, doped region 220 can be made to be greater than or equal to 1 × 10
19atoms per cubic centimeter.But the present invention does not limit equally to this, but should adjust accordingly according to actual conditions.
With reference to figure 7 to Figure 10, the first grid structure across described fin 200 and second grid structure 300 is formed respectively in first area 11 and second area 22, and make the position of described first and second grid structures 300 corresponding with the position of follow-up described first and second channel regions that will be formed respectively, that is, first grid structure to be formed at above described first doped region and to cover sidewall and the top of described fin; Second grid structure to be formed at above described second doped region and to cover sidewall and the top of described fin; Described first grid structure and second grid structure 300 are for defining the position of the source-drain area of follow-up formation.
In the present embodiment, described first grid structure is formed and second grid structure 300 comprises step by step following:
The part being positioned at first area 11 and second area 22 at described fin respectively forms the grid oxide layer 320 across described fin 200 respectively;
Described grid oxide layer 320 is formed the grid 310 across described fin 200;
Side wall 330 is formed at the sidewall of described grid 310.
But it should be noted that, the step of above formation grid structure is only the present embodiment and adopts, and the present invention does not limit this.
With reference to Figure 11, after the described first grid structure of formation and second grid structure 300, remove substrate between described first and second grid structures 300 (being fin 200 in the present embodiment) to form the first independent opening 50, and first grid structure away from second grid structure side and second grid structure away from the substrate (being fin 200 in the present embodiment) of first grid structure side in form the second opening 51 respectively.Described first opening 50 and the second opening 51 are for forming source-drain area at subsequent step.
Now, the first doped region 210 in remaining fin 200 and the second doped region 220 will become the first channel region and the second channel region when working without junction field effect transistor.
Because the first doped region 210 and the second doped region 220 are that material of the same race adulterates separately, when in running order without junction field effect transistor, whole first doped region 210 and the second doped region 220 become the first and second channel regions, that is, charge carrier is almost distributed in the middle of whole first and second channel regions.And the doping of existing field-effect transistor is generally only limitted to substrate surface, that is, existing field-effect transistor operationally most of charge carrier concentrates on surface, channel region, this can cause the degree of interface scattering to increase, so the present invention can reduce contingent interface scattering problem in channel region to a certain extent.
Continue with reference to Figure 12, in described first opening 50 and the second opening 51, fill the material layer 70 containing metal, to form the source-drain area without junction field effect transistor, source-drain area herein comprises source region, drain region, common source district or common drain region.Wherein, in the first opening 50, formation is total to drain region and then forms source region accordingly in the second opening 51; Or, in described first opening 50, form common source district and form drain region in described second opening 51.
In the present embodiment, nickel material layer can be formed, but the concrete material of the present invention to described material layer 70 does not limit, other metal or the compound containing metal can be used for forming described material layer 70 equally, and such as aluminium, tungsten, copper, silver, gold, titanium, titanium nitride, ramet and other some alloy materials may be used for forming described material layer 70 equally.
Specifically, selective chemical vapour deposition (selectiveCVD) in the present embodiment, can be adopted, in described opening 50, form the described material layer 70 containing metal.Due in deposition process, pre-reaction material is less than the reaction rate in growing surface (sidewall of opening 50 and bottom) in the reaction rate of non-growth surface, optionally can form described material layer 70 in opening 50 like this.So this generation type can deposit when not forming mask and form material layer 70, and has good stepcoverage performance.
Further, Metalorganic chemical vapor deposition (Metal-organicChemicalVaporDeposition can be adopted, the step coverage of the material layer 70 containing metal MOCVD) formed like this is comparatively better, can be covered in preferably in the middle of the first opening 50.
Source-drain area containing metal is conducive to reducing the contact resistance between the conductive plunger of follow-up formation, and additionally forms one deck suicide contact layer in the prior art without the need to picture and reduce contact resistance between source-drain area and conductive plunger.
In addition, resistance between source-drain area containing metal also can diminish little to a certain extent, this means under same cut-in voltage, firing current becomes large, this be conducive to a certain extent improve without junction field effect transistor performance (such as, improve under operating state without junction field effect transistor shutoff time electric leakage degree etc.).
In the present embodiment, after the described material layer 70 of formation, further comprising the steps of:
Annealing in process is carried out to the described material layer 70 containing metal.
Annealing in process can repair as best one can before etching fin 200 to form the first opening 50 time damage that the semi-conducting material (being silicon in the present embodiment) of fin 200 is produced, make the source region of formation and the metal material in drain region and semi-conducting material form good ohmic contact, so reduce form the source region of metal, the contact resistance between drain region and semi-conducting material.
Concrete, rapid thermal annealing (RapidThermalAnnealing can be adopted, RTA) technique carries out described annealing in process, and make the temperature of annealing in process in the scope of 450 ~ 550 degrees Celsius, while annealing, the impact on other parts of device can be reduced in this temperature range as far as possible.
Continue, with reference to Figure 13 and Figure 14, described substrate, the first and second grid structures 300 and source-drain area to form interlayer dielectric layer 500, and forms conductive plunger 90.As mentioned before, because described source region and drain region adopt the material containing metal to be formed, source region and the contact resistance between drain region and conductive plunger 90 relatively little.
With reference to Figure 15, when working without junction field effect transistor, the first and second grid structures 300 are met signal input part V
iN, the common drain region of the first and second grid structures 300 is met signal output part V
oUT; Because the first doped region 210 is N-type doping, and 220, the second doped region is corresponding P type doping, by the side ground connection GND of first grid structure away from second grid structure, by the side joint operating voltage V of second grid structure away from first grid structure
dD(+).
Work as V
iNwhen being input as low level, the first doped region 210 exhausts, now V
oUTexport as high level; Otherwise, work as V
iNwhen being input as high level, the second doped region 220 exhausts, now V
oUTexport as low level, thus realize the anti-phase function of constrained input.
In addition it should be noted that, above-mentioned formation method is only one embodiment of the present of invention, in other embodiments of the invention, described fin 200 is not limited in and forms above-mentioned cross section is the structure of rectangle, in of the present invention other are implemented, can also form other structures, the fin that such as cross section is triangular in shape or circular, the present invention is not limited in any way this.
In addition, the present invention be also not limited only to be formed FinFET structure in above-described embodiment without junction field effect transistor, in other embodiments of the invention, also can be formed other structures without junction field effect transistor, such as, planar structure without junction field effect transistor.
For formed planar structure without junction field effect transistor, specifically, semiconductor layer can be formed in the substrate, and in the semiconductor layer of planar structure, form the first doped region and the second doped region, and form first grid structure corresponding with the first doped region and the second doping position respectively and second grid structure;
After this, formed in the semiconductor layer and be positioned at the first opening of first grid structure and second grid structure and be positioned at the second opening of first grid structure and second grid structure opposite side, and the material layer formed in the first and second openings containing metal, to form source-drain area.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1., without a formation method for junction field effect transistor, it is characterized in that, comprising:
There is provided substrate, described substrate has first area and second area;
Carry out the first doping to form the first doped region to the substrate of described first area, carry out the second doping to form the second doped region to the substrate of described second area, described first doping is different from described second doping type;
Substrate is formed first grid structure and second grid structure, makes described first grid structure corresponding with the position of described first doped region, and make second grid structure corresponding with the position of described second doped region;
The substrate of removal between described first and second grid structures to form the first opening, and forms the second opening respectively in the substrate of first grid structure away from second grid structure side and in the substrate of second grid structure away from first grid structure side;
The material layer containing metal is filled in described first opening and the second opening, be total to drain region to be formed in described first opening and form source region in described second opening, or, in described first opening, form common source district and form drain region in described second opening.
2. form method as claimed in claim 1, it is characterized in that, the step of the material layer of filling containing metal in the first opening and the second opening comprises: the material layer forming aluminium, tungsten, copper, nickel, silver, gold, titanium, titanium nitride, ramet or alloy material.
3. form method as claimed in claim 1 or 2, it is characterized in that, fill material layer containing metal in the opening with after the step forming source region or drain region, described formation method also comprises:
Annealing in process is carried out to the described material layer containing metal.
4. form method as claimed in claim 3, it is characterized in that, the step of annealing in process comprises: adopt rapid thermal anneal process to carry out annealing in process to the described material layer containing metal.
5. form method as claimed in claim 1, it is characterized in that, provide the step of substrate to comprise:
Substrate is provided;
Form oxygen buried layer on the substrate;
Described oxygen buried layer forms semiconductor layer;
Remove the described semiconductor layer of part, to form fin;
The step forming the first and second doped regions comprises: in described fin, form described first and second doped regions respectively;
The step forming the first and second grid structures comprises: form the first grid structure across the first doped region in described fin, and makes first grid structure cover sidewall and the top of described fin; Form the second grid structure across the second doped region in described fin, and make second grid structure cover sidewall and the top of described fin;
The step forming the first and second openings comprises: remove fin between described first and second grid structures to form the first opening, and in the fin of first grid structure away from second grid structure side and in the fin of second grid structure away from first grid structure side, forming the second opening respectively, described first opening and the second opening expose described oxygen buried layer.
6. form method as claimed in claim 5, it is characterized in that, provide the step of substrate to comprise: the substrate providing silicon materials; The step forming oxygen buried layer comprises: form buried silicon oxide oxygen layer.
7. the formation method as described in claim 5 or 6, is characterized in that, the step forming oxygen buried layer comprises: make the thickness of described oxygen buried layer in the scope of 20 ~ 50 nanometers.
8. form method as claimed in claim 5, it is characterized in that, the step that described oxygen buried layer is formed semiconductor layer comprises: the semiconductor layer forming silicon, germanium material.
9. the formation method as described in claim 5 or 8, is characterized in that, removes the described semiconductor layer of part, comprises with the step forming fin: remove the described semiconductor layer of part, make the thickness of the fin of formation in the scope of 10 ~ 100 nanometers.
10. the formation method as described in claim 5 or 8, is characterized in that, removes part of semiconductor layer, comprises: Formation cross-section is the fin of triangle, rectangle or circle with the step forming fin.
11. form method as claimed in claim 1, it is characterized in that, the step forming the first and second doped regions comprises: the doping content of the first doped region and the second doped region is reduced gradually from substrate surface to substrate center.
12. formation methods as described in claim 1 or 11, it is characterized in that, the step forming the first and second doped regions comprises: form the first doped region of arsenic doping and boron doped second ditch doped region.
13. form method as claimed in claim 12, it is characterized in that, the step forming the first and second doped regions comprises:
Make the implant energy of arsenic in the scope of 5 ~ 40 kiloelectron-volts, and dopant dose is 1 × 10
16~ 5 × 10
16in the scope of every square centimeter;
Make the implant energy of boron in the scope of 1 ~ 10 kiloelectron-volt, and dopant dose is 1 × 10
16~ 5 × 10
16in the scope of every square centimeter.
14. 1 kinds without junction field effect transistor, is characterized in that, comprising:
Substrate, described substrate has first area and second area;
Second doped region of the first doped region being arranged in the substrate of first area and the substrate being arranged in second area, the doping type of described first and second doped regions is different;
Be positioned at the first grid structure on the substrate of the first doped region and be positioned at the second grid structure on described second doped region substrate;
Be formed with the first material layer containing metal in substrate between described first and second grid structures, be used as drain region altogether; First grid structure away from the second material layer be formed in the side of second grid structure and the substrate of second grid structure away from the side of first grid structure containing metal, as source region; Or the first material layer is used as common source district, the second material layer is used as drain region.
15. is as claimed in claim 14 without junction field effect transistor, and it is characterized in that, described substrate comprises:
Substrate;
Be formed at described suprabasil oxygen buried layer;
Be formed at the first fin on described oxygen buried layer and the second fin, the first fin and the second fin adulterate the ion of different doping type respectively;
Described first grid structure across described first fin, and covers sidewall and the top of described first fin, and described second grid structure across described second fin, and covers sidewall and the top of described second fin;
Described first material layer is between described first fin and the second fin, and described second material layer is positioned at described first fin away from the side of described first material layer and the described second fin side away from described first material layer.
16. is as claimed in claim 15 without junction field effect transistor, and it is characterized in that, the material of described fin is silicon or germanium material.
17. is as claimed in claim 16 without junction field effect transistor, and it is characterized in that, the cross section of described fin is triangle, rectangle or circle.
18. as described in claims 14 or 15 without junction field effect transistor, it is characterized in that, the doping content of described first doped region and the second doped region reduces gradually from substrate surface to substrate center.
19. as described in claims 14 or 15 without junction field effect transistor, it is characterized in that, described first doped region is arsenic doping district, and described second doped region is boron doped region.
20., as claimed in claim 14 without junction field effect transistor, is characterized in that, the material of the described material layer containing metal is aluminium, tungsten, copper, nickel, silver, gold, titanium, titanium nitride, ramet or alloy material.
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Application publication date: 20160113 |