US20130292776A1 - Semiconductor device employing fin-type gate and method for manufacturing the same - Google Patents

Semiconductor device employing fin-type gate and method for manufacturing the same Download PDF

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US20130292776A1
US20130292776A1 US13/941,125 US201313941125A US2013292776A1 US 20130292776 A1 US20130292776 A1 US 20130292776A1 US 201313941125 A US201313941125 A US 201313941125A US 2013292776 A1 US2013292776 A1 US 2013292776A1
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semiconductor device
gate
active region
region
device isolation
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US13/941,125
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Seung Hyun Lee
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SK Hynix Inc
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SK Hynix Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

Definitions

  • Embodiments of the present invention generally relate to a semiconductor device comprising of a fin-type gate, and more specifically, to a semiconductor device and a method for manufacturing the same that can effectively reduce the resistance of a source and drain of an active region.
  • a process margin for forming an active region and a device isolation region has been reduced. Specifically, as a semiconductor device is manufactured with lower-power or higher-speed elements, a gate width has been narrowed and a channel length has been reduced. This reduction will degrade an electrical characteristic of the semiconductor device and result in a short channel effect. As a result, methods to improve the reliability of the device have been required.
  • a multi-channel field effect transistor such as a recess gate and a fin-type gate
  • the recess gate is obtained by etching a given depth of a semiconductor substrate of a gate expected region to increase a channel length.
  • the fin-type gate increases the contact area between the active region and the gate to improve the driving capacity of the gate and the electrical characteristics of the device.
  • a fin-type transistor has a fin channel structure where a three-side gate surrounds a channel.
  • a fin channel structure does not go beyond the established manufacturing technique but can be manufactured to have a three-dimensional structure. Due to its structural characteristic, the fine channel structure has a good gate control capacity to reduce the short channel effect, thereby minimizing the effect between the drain region and the source region. Additionally, the fin channel structure can reduce the channel doping concentration, thereby preventing leakage current through a junction region.
  • a damascene method such as a method of exposing both sides of the active region has been generally used.
  • the process includes forming a device isolation region to set the active region and recessing a partial surface of the device isolation region.
  • a gate line is formed in a recess groove formed in the device isolation region so that the gate may be disposed on both side surfaces of the active region.
  • the entire resistance of the fin-type gate is determined by the channel resistance and resistance in the source and drain region.
  • the resistance of the source and drain region of the fin-type gate is determined by an interface between metal silicide and silicon formed in a silicon part of the source and drain region.
  • Various embodiments of the invention are directed to preventing increase of the entire resistance due to increase of resistance in the source and drain region in a semiconductor device comprising a fin-type gate that has a fin channel structure where a three-side gate surrounds a channel, thereby improving degradation of characteristics of the semiconductor device.
  • a semiconductor device comprises: an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region; and a silicide film disposed over the upper portion and the sidewall portion of the active region.
  • the semiconductor device further comprises a gate line disposed over the active region.
  • the gate line includes a gate oxide film, a gate layer and a gate hard mask layer.
  • the semiconductor device further comprises an interlayer insulating film planarized with the gate line over the device isolation region.
  • the semiconductor device further comprises a landing plug connected to the top surface of the silicide film and planarized with the interlayer insulating film.
  • a method for manufacturing a semiconductor device comprises: forming a device isolation region in a semiconductor substrate; forming a trench in the device isolation region to protrude an upper portion and a sidewall portion of an active region; and forming a silicide film in the upper portion and the sidewall portion of the active region.
  • the method further comprises forming a gate line buried in the device isolation region.
  • the forming-a-gate-line includes: forming a recess in the device isolation region; forming a gate oxide film on the device isolation region including the recess and the active region; forming a gate layer on the upper portion of the gate oxide film; forming a gate hard mask layer on the upper portion of the gate layer; and forming a photoresist pattern on the gate hard mask to perform a patterning process with the photoresist pattern as an etching mask.
  • After forming a gate line includes: forming a source/drain region in the active region at a side of gate line.
  • the forming-a-silicide-film includes: forming a metal layer on the gate line, the isolation region and the active region, the metal layer being in contact with the source/drain region of the active region; performing a thermal process to react the active region with the metal layer; and selectively removing the metal layer that does not react with the active region.
  • the metal layer is formed by a chemical vapor deposition (CVD) process.
  • the forming-a-metal-layer includes forming Ti, Co or Ni.
  • the method further comprises forming a landing plug connected to the silicide film.
  • the forming-a-landing-plug includes: forming an interlayer insulating film on the gate line, the device isolation region and the active film including the silicide film; etching the interlayer insulating film to expose the silicide film; forming a conductive material on the silicide film; and performing a planarizing process on the conductive material to expose the interlayer insulating film.
  • the active region is formed at a higher level than the device isolation region.
  • the active region formed to have a fin shape having a top surface formed at a higher level than the device isolation region and a sidewall extending from the top surface of the active region to the device isolation region, wherein the silicide film is formed over the top surface and the sidewall of the active region, and wherein the source/drain region is formed over the active region.
  • a semiconductor device in one embodiment, includes a substrate including an active region and a device isolation region; a fin-shaped gate pattern formed in the active region; a source/drain pattern formed in the substrate at a side of the fin-shaped gate in the active region; a conductive pattern electrically coupled to the source/drain region; and a silicide film formed between the source/drain pattern and the conductive pattern, the silicide film formed in the active region.
  • the silicide film is formed external to the device isolation region.
  • the active region is formed at a higher level than the device isolation region.
  • the active region has a fin shape having a top surface formed at a higher level than the device isolation region and a sidewall extending from the top surface of the active region to the device isolation region, wherein the silicide film is formed over the top surface and the sidewall of the active region, and wherein the source/drain pattern is formed over the top surface of the active region.
  • FIG. 1 is a cross-sectional diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • FIGS. 2 a to 2 j are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • FIG. 1 is a cross-sectional diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • a semiconductor device includes a device isolation region 102 buried in a trench obtained by etching a given thickness of a semiconductor substrate 100 , an active region 104 having an upper portion and a sidewall portion which are protruded from the top surface of the device isolation region 102 , a silicide film 124 formed in the upper portion and the sidewall portion of the active region 104 , an interlayer insulating film 126 formed on the upper portion of the device isolation region 102 , a gate line 114 disposed between the interlayer insulating films 126 to divide the active region 104 into three regions to have a height planarized with the interlayer insulating film 126 , and a landing plug 128 connected to the silicide film 124 and planarized with the gate line 114 .
  • the gate line 114 has a stacked structure including a gate oxide film (not shown), a gate layer 108 and a gate hard mask layer 110 .
  • the silicide film 124 is obtained by performing a thermal process on the active region 104 and a metal layer (not shown) formed over the upper portion and the sidewall portion of the active region 104 .
  • the metal layer (not shown) includes any of Ti, Co or Ni, which is formed by a chemical vapor deposition (CVD) process.
  • a dopant implanting region (not shown) may be formed in the active region 104 .
  • the semiconductor device of FIG. 1 includes the silicide film formed in the upper portion and the sidewall portion of the active region to prevent an increase of resistance of a source and drain region of a fin-type gate.
  • FIGS. 2 a to 2 j are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • an insulating material is buried in the trench (not shown) to form the device isolation region 102 .
  • the active region 104 is defined by the device isolation region 102 formed in the semiconductor substrate 100 .
  • the active region 104 includes an insulating material field oxide film.
  • a photoresist pattern (not shown) that defines a fin-type gate region is formed on the semiconductor substrate 100 including the device isolation region 102 .
  • a given thickness of the device isolation region 102 is etched with the photoresist pattern (not shown) to form a recess 106 .
  • the gate oxide film (not shown), the gate layer 108 and the gate hard mask layer 110 are formed on the device isolation region 102 including the recess 106 .
  • a photoresist pattern (not shown) to define a gate line is formed on the gate hard mask layer 110 .
  • the gate hard mask layer 110 is etched with the photoresist pattern (not shown) as an etching mask.
  • the gate layer 108 and the gate oxide film (not shown) are etched with the gate hard mask layer as an etching mask to form a gate line 114 .
  • a gate spacer material is deposited on the gate line 114 .
  • An etch-back process is performed on the gate spacer material to form a gate spacer 118 over the sidewall of the gate line 114 .
  • a given thickness of the device isolation region 102 is etched with the gate line 114 including the gate spacer 118 as an etching mask to form a trench 120 .
  • the depth of the trench 120 is identical with that of the recess 106 formed to define the fin-type gate region so that the device isolation region 102 disposed in a source and drain peripheral region may be removed. That is, the upper portion and the sidewall portion of the active region 104 are protruded by the trench 120 . Accordingly, the active region 104 is formed at a higher level than the device isolation region 102 .
  • the active region 104 formed to have a fin shape having a top surface formed at a higher level than the device isolation region 102 and a sidewall extending from the top surface of the active region 104 to the device isolation region 102 ,
  • a dopant implanting region (not shown) may be formed in the protruded active region 104 so that a silicide layer formed in a subsequent process can form an ohmic-contact.
  • a metal layer 122 is formed on the trench 120 .
  • the metal layer 122 is formed by a chemical vapor deposition (CVD) process.
  • the metal layer 122 can be formed of Ti, Co or Ni.
  • a thermal process is performed to form the silicide film 124 in the upper portion and the sidewall portion of the active region 104 .
  • the silicide film 124 is formed only on the upper portion of the active region 104 because the active region 104 has a silicon substrate which is in contact with the metal layer 122 (see FIG. 2 g ).
  • the silicide film 124 is formed between the source/drain region and the gate pattern 114 , the silicide film 124 formed in the active region 104 . That is, when a thermal process is performed after the metal layer 122 (see FIG. 2 g ) is formed, the device isolation region 102 which includes no silicon substrate in contact with the metal layer 122 (see FIG. 2 g ) is not subject to the silicide reaction.
  • the unsilicidized metal layer is selectively removed.
  • the silicide film 124 may be formed only over the upper portion and the sidewall of the substrate pattern in the active region 104 .
  • the interlayer insulating film 126 is formed on the gate line 114 , the isolation region 102 and the active region 104 including the silicide film 124 so that a gap between the silicide film 124 and the gate line 114 may be filled.
  • a planarizing process is performed on the interlayer insulating film 126 to expose the gate line 114 .
  • a photoresist pattern (not shown) that defines a landing plug hole is formed on the planarized upper portion of the interlayer insulating film 126 .
  • the interlayer insulating film 126 is etched with the photoresist pattern (not shown) as an etching mask to expose the silicide layer 124 .
  • a conductive material is buried so that the landing plug hole (not shown) may be filled to form a landing plug 128 .
  • the above-described method includes exposing the upper portion and the sidewall of the active region, and performing a thermal process to form the silicide film by reaction with the metal layer formed on the upper portion and the sidewall of the active region, thereby reducing resistance of the source and drain region to improve characteristics of the semiconductor device.
  • a semiconductor device and a method for manufacturing the same can effectively reduce resistance in a source and drain region of the semiconductor device, thereby reducing the entire resistance of the semiconductor device comprising a fin-type gate to improve characteristics of the semiconductor device.

Abstract

A semiconductor device comprises an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region, and a silicide film disposed in the upper portion and the sidewall portion of the active region, thereby effectively reducing resistance in a source/drain region of the semiconductor device. As a result, the entire resistance of the semiconductor device comprising a fin-type gate can be reduced to improve characteristics of the semiconductor device.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • The priority of Korean patent application No. 10-2009-0117118 filed on Nov. 30, 2009, the disclosure of which is hereby incorporated in its entirety by reference, is claimed.
    • BACKGROUND OF THE INVENTION
  • Embodiments of the present invention generally relate to a semiconductor device comprising of a fin-type gate, and more specifically, to a semiconductor device and a method for manufacturing the same that can effectively reduce the resistance of a source and drain of an active region.
  • Due to the high integration of semiconductor devices, a process margin for forming an active region and a device isolation region has been reduced. Specifically, as a semiconductor device is manufactured with lower-power or higher-speed elements, a gate width has been narrowed and a channel length has been reduced. This reduction will degrade an electrical characteristic of the semiconductor device and result in a short channel effect. As a result, methods to improve the reliability of the device have been required.
  • Of these methods, a multi-channel field effect transistor (McFET) such as a recess gate and a fin-type gate has been used. The recess gate is obtained by etching a given depth of a semiconductor substrate of a gate expected region to increase a channel length. The fin-type gate increases the contact area between the active region and the gate to improve the driving capacity of the gate and the electrical characteristics of the device.
  • A fin-type transistor has a fin channel structure where a three-side gate surrounds a channel. A fin channel structure does not go beyond the established manufacturing technique but can be manufactured to have a three-dimensional structure. Due to its structural characteristic, the fine channel structure has a good gate control capacity to reduce the short channel effect, thereby minimizing the effect between the drain region and the source region. Additionally, the fin channel structure can reduce the channel doping concentration, thereby preventing leakage current through a junction region.
  • In order to form the fin-type transistor, a damascene method such as a method of exposing both sides of the active region has been generally used. The process includes forming a device isolation region to set the active region and recessing a partial surface of the device isolation region. A gate line is formed in a recess groove formed in the device isolation region so that the gate may be disposed on both side surfaces of the active region.
  • Meanwhile, the entire resistance of the fin-type gate is determined by the channel resistance and resistance in the source and drain region. Generally, the resistance of the source and drain region of the fin-type gate is determined by an interface between metal silicide and silicon formed in a silicon part of the source and drain region.
    • BRIEF SUMMARY OF THE INVENTION
  • Various embodiments of the invention are directed to preventing increase of the entire resistance due to increase of resistance in the source and drain region in a semiconductor device comprising a fin-type gate that has a fin channel structure where a three-side gate surrounds a channel, thereby improving degradation of characteristics of the semiconductor device.
  • According to an embodiment of the present invention, a semiconductor device comprises: an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region; and a silicide film disposed over the upper portion and the sidewall portion of the active region.
  • The semiconductor device further comprises a gate line disposed over the active region.
  • The gate line includes a gate oxide film, a gate layer and a gate hard mask layer.
  • The semiconductor device further comprises an interlayer insulating film planarized with the gate line over the device isolation region.
  • The semiconductor device further comprises a landing plug connected to the top surface of the silicide film and planarized with the interlayer insulating film.
  • According to an embodiment of the present invention, a method for manufacturing a semiconductor device comprises: forming a device isolation region in a semiconductor substrate; forming a trench in the device isolation region to protrude an upper portion and a sidewall portion of an active region; and forming a silicide film in the upper portion and the sidewall portion of the active region.
  • After forming a device isolation region, the method further comprises forming a gate line buried in the device isolation region.
  • The forming-a-gate-line includes: forming a recess in the device isolation region; forming a gate oxide film on the device isolation region including the recess and the active region; forming a gate layer on the upper portion of the gate oxide film; forming a gate hard mask layer on the upper portion of the gate layer; and forming a photoresist pattern on the gate hard mask to perform a patterning process with the photoresist pattern as an etching mask.
  • After forming a gate line includes: forming a source/drain region in the active region at a side of gate line.
  • The forming-a-silicide-film includes: forming a metal layer on the gate line, the isolation region and the active region, the metal layer being in contact with the source/drain region of the active region; performing a thermal process to react the active region with the metal layer; and selectively removing the metal layer that does not react with the active region.
  • The metal layer is formed by a chemical vapor deposition (CVD) process.
  • The forming-a-metal-layer includes forming Ti, Co or Ni.
  • After forming-a-silicide-film, the method further comprises forming a landing plug connected to the silicide film.
  • The forming-a-landing-plug includes: forming an interlayer insulating film on the gate line, the device isolation region and the active film including the silicide film; etching the interlayer insulating film to expose the silicide film; forming a conductive material on the silicide film; and performing a planarizing process on the conductive material to expose the interlayer insulating film.
  • The active region is formed at a higher level than the device isolation region.
  • The active region formed to have a fin shape having a top surface formed at a higher level than the device isolation region and a sidewall extending from the top surface of the active region to the device isolation region, wherein the silicide film is formed over the top surface and the sidewall of the active region, and wherein the source/drain region is formed over the active region.
  • In one embodiment, a semiconductor device includes a substrate including an active region and a device isolation region; a fin-shaped gate pattern formed in the active region; a source/drain pattern formed in the substrate at a side of the fin-shaped gate in the active region; a conductive pattern electrically coupled to the source/drain region; and a silicide film formed between the source/drain pattern and the conductive pattern, the silicide film formed in the active region. The silicide film is formed external to the device isolation region. The active region is formed at a higher level than the device isolation region. The active region has a fin shape having a top surface formed at a higher level than the device isolation region and a sidewall extending from the top surface of the active region to the device isolation region, wherein the silicide film is formed over the top surface and the sidewall of the active region, and wherein the source/drain pattern is formed over the top surface of the active region.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • FIGS. 2 a to 2 j are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
    •  DESCRIPTION OF EMBODIMENTS
  • The present invention will be described in detail with reference to the attached drawings.
  • FIG. 1 is a cross-sectional diagram illustrating a semiconductor device according to an embodiment of the present invention.
  • Referring to FIG. 1, a semiconductor device includes a device isolation region 102 buried in a trench obtained by etching a given thickness of a semiconductor substrate 100, an active region 104 having an upper portion and a sidewall portion which are protruded from the top surface of the device isolation region 102, a silicide film 124 formed in the upper portion and the sidewall portion of the active region 104, an interlayer insulating film 126 formed on the upper portion of the device isolation region 102, a gate line 114 disposed between the interlayer insulating films 126 to divide the active region 104 into three regions to have a height planarized with the interlayer insulating film 126, and a landing plug 128 connected to the silicide film 124 and planarized with the gate line 114. The gate line 114 has a stacked structure including a gate oxide film (not shown), a gate layer 108 and a gate hard mask layer 110. The silicide film 124 is obtained by performing a thermal process on the active region 104 and a metal layer (not shown) formed over the upper portion and the sidewall portion of the active region 104. The metal layer (not shown) includes any of Ti, Co or Ni, which is formed by a chemical vapor deposition (CVD) process. A dopant implanting region (not shown) may be formed in the active region 104.
  • The semiconductor device of FIG. 1 includes the silicide film formed in the upper portion and the sidewall portion of the active region to prevent an increase of resistance of a source and drain region of a fin-type gate.
  • FIGS. 2 a to 2 j are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • Referring to FIG. 2 a, after a given thickness of the semiconductor device 100 is etched to form a trench (not shown), an insulating material is buried in the trench (not shown) to form the device isolation region 102. The active region 104 is defined by the device isolation region 102 formed in the semiconductor substrate 100. The active region 104 includes an insulating material field oxide film.
  • Referring to FIG. 2 b, a photoresist pattern (not shown) that defines a fin-type gate region is formed on the semiconductor substrate 100 including the device isolation region 102. A given thickness of the device isolation region 102 is etched with the photoresist pattern (not shown) to form a recess 106.
  • Referring to FIG. 2 c, the gate oxide film (not shown), the gate layer 108 and the gate hard mask layer 110 are formed on the device isolation region 102 including the recess 106.
  • Referring to FIG. 2 d, a photoresist pattern (not shown) to define a gate line is formed on the gate hard mask layer 110. The gate hard mask layer 110 is etched with the photoresist pattern (not shown) as an etching mask. The gate layer 108 and the gate oxide film (not shown) are etched with the gate hard mask layer as an etching mask to form a gate line 114.
  • Referring to FIG. 2 e, a gate spacer material is deposited on the gate line 114. An etch-back process is performed on the gate spacer material to form a gate spacer 118 over the sidewall of the gate line 114. A source/drain region(not shown) formed in the active region.
  • Referring to FIG. 2 f, a given thickness of the device isolation region 102 is etched with the gate line 114 including the gate spacer 118 as an etching mask to form a trench 120. The depth of the trench 120 is identical with that of the recess 106 formed to define the fin-type gate region so that the device isolation region 102 disposed in a source and drain peripheral region may be removed. That is, the upper portion and the sidewall portion of the active region 104 are protruded by the trench 120. Accordingly, the active region 104 is formed at a higher level than the device isolation region 102. The active region 104 formed to have a fin shape having a top surface formed at a higher level than the device isolation region 102 and a sidewall extending from the top surface of the active region 104 to the device isolation region 102, A dopant implanting region (not shown) may be formed in the protruded active region 104 so that a silicide layer formed in a subsequent process can form an ohmic-contact.
  • Referring to FIG. 2 g, a metal layer 122 is formed on the trench 120. The metal layer 122 is formed by a chemical vapor deposition (CVD) process. The metal layer 122 can be formed of Ti, Co or Ni.
  • Referring to FIG. 2 h, a thermal process is performed to form the silicide film 124 in the upper portion and the sidewall portion of the active region 104. The silicide film 124 is formed only on the upper portion of the active region 104 because the active region 104 has a silicon substrate which is in contact with the metal layer 122 (see FIG. 2 g). The silicide film 124 is formed between the source/drain region and the gate pattern 114, the silicide film 124 formed in the active region 104. That is, when a thermal process is performed after the metal layer 122 (see FIG. 2 g) is formed, the device isolation region 102 which includes no silicon substrate in contact with the metal layer 122 (see FIG. 2 g) is not subject to the silicide reaction. The unsilicidized metal layer is selectively removed. The silicide film 124 may be formed only over the upper portion and the sidewall of the substrate pattern in the active region 104.
  • Referring to FIG. 2 i, the interlayer insulating film 126 is formed on the gate line 114, the isolation region 102 and the active region 104 including the silicide film 124 so that a gap between the silicide film 124 and the gate line 114 may be filled.
  • Referring to FIG. 2 j, a planarizing process is performed on the interlayer insulating film 126 to expose the gate line 114. A photoresist pattern (not shown) that defines a landing plug hole is formed on the planarized upper portion of the interlayer insulating film 126. The interlayer insulating film 126 is etched with the photoresist pattern (not shown) as an etching mask to expose the silicide layer 124. A conductive material is buried so that the landing plug hole (not shown) may be filled to form a landing plug 128.
  • That is, the above-described method includes exposing the upper portion and the sidewall of the active region, and performing a thermal process to form the silicide film by reaction with the metal layer formed on the upper portion and the sidewall of the active region, thereby reducing resistance of the source and drain region to improve characteristics of the semiconductor device.
  • As described above, a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention can effectively reduce resistance in a source and drain region of the semiconductor device, thereby reducing the entire resistance of the semiconductor device comprising a fin-type gate to improve characteristics of the semiconductor device.
  • The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps describe herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims (6)

1. A semiconductor device comprising:
an active region having an upper portion and a sidewall portion protruding from an upper portion of a device isolation region; and
a silicide film disposed over the upper portion and the sidewall portion of the active region.
2. The semiconductor device according to claim 1, further comprising a gate line disposed over the active region.
3. The semiconductor device according to claim 2, wherein the gate line includes a gate oxide film, a gate layer and a gate hard mask layer.
4. The semiconductor device according to claim 1, further comprising an interlayer insulating film planarized with the gate line over the device isolation region.
5. The semiconductor device according to claim 4, further comprising a landing plug connected to the silicide film.
6-20. (canceled)
US13/941,125 2009-11-30 2013-07-12 Semiconductor device employing fin-type gate and method for manufacturing the same Abandoned US20130292776A1 (en)

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