CN105990138A - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN105990138A CN105990138A CN201510051501.7A CN201510051501A CN105990138A CN 105990138 A CN105990138 A CN 105990138A CN 201510051501 A CN201510051501 A CN 201510051501A CN 105990138 A CN105990138 A CN 105990138A
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Abstract
A transistor and a forming method thereof are disclosed. The forming method of the transistor comprises the following steps: providing a substrate which comprises a first semiconductor layer, an insulating layer on the first semiconductor layer, and a second semiconductor layer on the surface of the insulating layer; forming a gate structure on the second semiconductor layer, wherein the gate structure comprises a gate dielectric layer covering part of the second semiconductor layer and a gate on the surface of the gate dielectric layer; forming spacers on the sidewall surfaces of the gate structure; forming an amorphous silicon layer on the surface of the second semiconductor layer, wherein the amorphous silicon layer covers the spacers, and the surface of the amorphous silicon layer is flush with the top surface of the gate structure; carrying out metal induced lateral crystallization on the amorphous silicon layer at the two sides of the gate structure to convert the amorphous silicon layer into a polycrystalline silicon layer; back-etching the polycrystalline silicon layer to make the surface of the polycrystalline silicon layer lower than the top surface of the gate structure; and forming a source and a drain in the polycrystalline silicon layer at the two sides of the gate structure. Through the method, the cost of the transistor is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of transistor and forming method thereof.
Background technology
Transistor is the most basic element in semiconductor manufacturing, and it is widely used in various integrated circuit.Brilliant
Body pipe generally comprises: is positioned at the grid structure of semiconductor substrate surface, is positioned at partly leading of grid structure both sides
Source electrode in body substrate and drain electrode.Wherein source electrode and drain electrode are by highly doped formation, according to device class
Type is different, can be divided into n-type doping (NMOS) and p-type doping (PMOS).
In order to improve the parasitic capacitance reducing transistor, improve the work efficiency of transistor, can be at the insulation end
Form transistor on upper silicon substrate (SOI), at the bottom of described insulation on silicon include: bottom silicon layer, be positioned at bottom
The silicon oxide layer of silicon surface and be positioned at the top silicon layer on silicon oxide layer surface.Silicon substrate on the insulation end
(SOI) the upper transistor formed is by isolating between silicon oxide layer and bottom silicon layer, such that it is able to reduce crystalline substance
The parasite current of body pipe.The channel region of described transistor, source-drain electrode are respectively positioned in top silicon layer, described
The thickness of top silicon layer is less, easily forms the fully-depleted of channel region, such that it is able to effectively suppress short ditch
Channel effect and drain induced barrier reduce effect.But owing to the thickness of described top silicon layer is less, it is impossible to formed
Good source and drain metal contact, thus the source-drain series resistance between the source-drain electrode of transistor can be caused relatively big,
Thus cause the driving electric current of transistor to decline, affect the performance of transistor.
In prior art, it is usually formed the source-drain electrode 10 raised to reduce source-drain series resistance Rext(refer to
Fig. 1).The generally top silicon layer surface in grid structure both sides forms silicon epitaxial layers so that ultimately form
The thickness of source-drain electrode 10 increases, due to source-drain series resistance RextIt is inversely proportional to the volume of source-drain electrode 10, so,
The thickness of source-drain electrode 10 is the biggest, source-drain series resistance RextThe least.Further, source-drain electrode 10 thickness increase big it
After, the contact of effective metal can be formed on source-drain electrode 10 surface, thus reduce source and drain series electrical further
Resistance Rext。
But, prior art formation has the relatively costly of the transistor of the source drain structure raised.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor and forming method thereof, reduces the transistor formed
Cost.
For solving the problems referred to above, the present invention provides the forming method of a kind of transistor, including: substrate is provided,
Described substrate includes: the first semiconductor layer, the insulating barrier being positioned on the first semiconductor layer and be positioned at insulating barrier
Second semiconductor layer on surface；Described second semiconductor layer is formed grid structure, described grid structure
Gate dielectric layer and the grid being positioned at described gate dielectric layer surface including covering part the second semiconductor layer；?
Described gate structure sidewall surface forms side wall；Amorphous silicon layer is formed in described second semiconductor layer surface,
Described amorphous silicon layer covers side wall and the surface of described amorphous silicon layer flushes with the top surface of grid structure；
The amorphous silicon layer of described grid structure both sides is carried out metal induced longitudinal crystallization process, makes described non-crystalline silicon
Layer is changed into polysilicon layer；It is etched back to described polysilicon layer, makes the surface of described polysilicon layer less than grid
The top surface of structure；Source-drain electrode is formed in the polysilicon layer of described grid structure both sides.
Optionally, the method carrying out metal induced longitudinal crystallization process includes: in described grid structure, side
Wall and amorphous silicon layer surface form the mask layer with opening, and described opening exposes grid structure both sides
The part surface of amorphous silicon layer；Inducing metal layer is formed at described mask layer and opening inner wall surface；Carry out
First annealing so that amorphous silicon layer is crystallization under the induction of inducing metal layer, is changed into polysilicon layer；
Remove described inducing metal layer and mask layer.
Optionally, the material of described inducing metal layer is Al, Cu, Au, Ag, Ni or Pb.
Optionally, the thickness of described inducing metal layer is 1nm～20nm.
Optionally, sputtering technology, electron beam evaporation is used to form described inducing metal layer.
Optionally, described first annealing is at N2, carry out under Ar, He or Ne atmosphere, temperature is 350 DEG C
～600 DEG C, the time is 5h～20h.
Optionally, the width of the crystal grain in described polysilicon layer is 0.8 μm～1 μm, crystal grain a length of
1 μm～15 μm.
Optionally, also include: after removing described inducing metal layer and mask layer, carry out the second annealing
Process, make the crystallite dimension in described polysilicon layer increase.
Optionally, described second annealing is at N2, carry out under Ar, He or Ne atmosphere, temperature is 650 DEG C
～1000 DEG C, the time is 10min～60min.
Optionally, the material of described mask layer is silicon nitride or silicon oxide.
Optionally, before forming described side wall, in the second semiconductor layer of described grid structure both sides
Carry out ion implanting is lightly doped.
Optionally, described grid structure also includes the protective layer being positioned at gate top surface.
Optionally, the method forming described grid structure includes: sequentially forms grid at described substrate surface and is situated between
Material layer, it is positioned at the gate material layers on gate dielectric material layer surface and is positioned at gate material layers surface
Protection material layer；Etch described protection material layer, gate material layers and gate dielectric material layer to substrate table
Face, forms grid structure.
Optionally, the material of described gate dielectric layer be silicon oxide, grid material be polysilicon, protective layer material
Material is silicon oxide.
Optionally, use low-pressure chemical vapor deposition process to form described amorphous silicon layer, specifically include: adopt
Use SiH4As deposition gases, SiH4Flow be 30sccm～200sccm, temperature is 450 DEG C～600 DEG C,
Pressure is 200mTorr～400mTorr.
Optionally, wet-etching technology is used to remove described mask layer and inducing metal layer.
Optionally, the mixed solution using sulphuric acid and hydrogen peroxide removes described inducing metal layer, described sulphuric acid
It it is 60 DEG C～130 DEG C with the temperature of the mixed solution of hydrogen peroxide.
Optionally, described grid structural length is less than 100nm, and described grid structural length is grid structure
It is parallel to the size in the source-drain electrode line direction of grid structure both sides.
Optionally, described substrate is silicon substrate at the insulation end.
For solving the problems referred to above, technical scheme also provides for a kind of crystalline substance using said method to be formed
Body pipe, including substrate, described substrate includes: the first semiconductor layer, be positioned on the first semiconductor layer
Insulating barrier and the second semiconductor layer being positioned at surface of insulating layer；It is positioned at the grid on described second semiconductor layer
Structure, described grid structure includes the gate dielectric layer of covering part the second semiconductor layer and is positioned at described grid Jie
The grid on matter layer surface；It is positioned at the side wall on described gate structure sidewall surface；It is positioned at described second quasiconductor
The polysilicon layer on layer surface, described polysilicon layer covers side wall and the surface of described amorphous silicon layer, and described
The surface of polysilicon layer flushes less than the top surface of grid structure；It is positioned at described grid structure both sides many
Source-drain electrode in crystal silicon layer.
Compared with prior art, technical scheme has the advantage that
Technical scheme, after forming grid structure on substrate, at the lining of grid structure both sides
Basal surface forms the amorphous silicon layer flushed with grid structure top surface, then to described grid structure both sides
Amorphous silicon layer carry out metal induced longitudinal crystallization process, make described amorphous silicon layer be changed into polysilicon layer；
Then etch described polysilicon layer, make the surface top surface less than grid structure of described polysilicon layer,
And in described polysilicon layer, form the source-drain electrode of transistor.With directly use epitaxy technique the second half
Conductor layer surface forms crystalline silicon and compares, and the depositing temperature of formation non-crystalline silicon is relatively low, sedimentation rate very fast,
Can effectively reduce process costs, improve efficiency.And metal induced longitudinal crystallization processes, the crystalline substance of process
Changing temperature relatively low, the defect concentration in the polysilicon layer of formation is low, forms the cost of described polysilicon layer relatively
Low, and the quality of the polysilicon layer formed is high, is conducive to improving the performance of the transistor formed.
Further, the method that described metal induced longitudinal crystallization processes includes: in described grid structure, side
Wall and amorphous silicon layer surface form the mask layer with opening, and described opening exposes grid structure both sides
The part surface of amorphous silicon layer；Inducing metal layer is formed at described mask layer and opening inner wall surface；Carry out
First annealing so that amorphous silicon layer is crystallization under the induction of inducing metal layer, is changed into polysilicon layer；
Remove described inducing metal layer and mask layer.In described first annealing process, described inducing metal
Layer and amorphous silicon layer react formation metal silicide layer, at the interface of described metal silicide layer Yu non-crystalline silicon
On, metal silicide and silicon carry out displacement exchange, gradually form silicon crystal grain, along with the growth of crystal grain,
Whole metal silicide layer can form cavity and crush, and and then, after crushing, the metal silicide of formation is little
Agglomerate is diffused in the top layer of non-crystalline silicon and forms a crystallization interval.Simultaneously as inducing metal layer is only
Covering part amorphous silicon layer, by the edge of described inducing metal layer overlay area, forms some
The lumps of metal silicide, and in annealing process, be laterally into connected amorphous silicon region
Territory, the non-crystalline silicon on the path of described metal silicide transverse movement will all be crystallized, and forms polycrystalline
Silicon layer.
Further, after removing described inducing metal layer and mask layer, it is also possible to carry out second annealing treatment
Reason, makes the crystal grain continued growth in described polysilicon layer, thus improves the size of described crystal grain further,
Thus improve the carrier mobility in the source-drain electrode being subsequently formed, improve the performance of the transistor formed.
Accompanying drawing explanation
Fig. 1 is the structural representation of the transistor of the prior art of the present invention；
Fig. 2 is the schematic diagram that non-crystalline silicon carries out metal induced longitudinal crystallization process；
Fig. 3 to Figure 12 is the structural representation of the forming process of the transistor of the present invention.
Detailed description of the invention
As described in the background art, prior art forms the cost with the transistor raising source drain structure
Higher, form epitaxial silicon mainly due to using the epitaxy technique top silicon layer surface in grid structure both sides
Layer relatively costly, and the time is longer, so so that the transistor of formation relatively costly.
Inventor finds, can make described non-by non-crystalline silicon carries out metal induced longitudinal crystallization process
Crystal silicon crystallization forms polysilicon.Refer to Fig. 2, Semiconductor substrate 20 forms insulating barrier 21, absolutely
Edge layer 21 surface forms amorphous silicon layer 22, forms the mask with opening on described amorphous silicon layer 22 surface
Layer 30, described opening exposes the surface of portion of amorphous silicon layer 22；Formed on described mask layer 30 surface
Inducing metal layer 31, described inducing metal layer 31 contacts, so with amorphous silicon layer 22 surface of open bottom
After anneal so that described amorphous silicon layer 22 is positioned at opening lower zone to both sides, crystallization occurs,
Form crystallization polysilicon region 22a.The cost that described method forms polysilicon is relatively low.
In embodiments of the invention, directly the second semiconductor layer surface in grid structure both sides forms amorphous
Silicon, is then processed by metal induced longitudinal crystallization and makes described amorphous silicon layer be changed into polysilicon layer, then
The source-drain electrode of transistor is formed, it is not necessary to use epitaxy technique, shape can be reduced in described polysilicon layer
Become the process costs of transistor.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
Refer to Fig. 3, it is provided that substrate 100, described substrate 100 includes: the first semiconductor layer 101, position
Insulating barrier 102 on the first semiconductor layer 101 and the second semiconductor layer being positioned at insulating barrier 102 surface
103。
The material of described first semiconductor layer 101 is the semi-conducting materials such as silicon, germanium, SiGe, described absolutely
The material of edge layer 102 can be the insulating dielectric materials such as silicon oxide, silicon oxynitride, described second quasiconductor
The material of layer 103 is the semi-conducting materials such as silicon, germanium, SiGe.
Described insulating barrier 102 is as the isolation between the first semiconductor layer 101 and the second semiconductor layer 103
Layer, forms transistor on described substrate 100, can reduce the parasitic capacitance of transistor, improve crystal
The operating rate of pipe.
In the present embodiment, described substrate 100 is silicon substrate at the insulation end, concrete, and described the first half lead
The material of body layer 101 be silicon, the material of insulating barrier 102 be silicon oxide, the material of the second semiconductor layer 103
Material is silicon.
Refer to Fig. 4, sequentially form gate dielectric material layer 201 on described substrate 100 surface, be positioned at grid Jie
The gate material layers 202 on material layer 201 surface.
Chemical vapor deposition method can be used to sequentially form described gate dielectric material layer 201 and grid material
Layer 202.The material of described gate dielectric material layer 201 is silicon oxide, silicon oxynitride, it is also possible to be high K
Dielectric material, such as hafnium oxide, zirconium oxide, silicon hafnium oxide, aluminium oxide or silicon zirconium oxide etc..Described grid
The material of pole material layer 202 is polysilicon, it is also possible to be metal material, such as aluminum, copper or tungsten etc..
In the present embodiment, after forming described gate material layers 202, in described gate material layers 202
Surface forms protection material layer 203, and described protection material layer 203 is for protecting described grid in subsequent technique
Pole material layer 202.The material of described protection material layer 203 is silicon oxide or silicon nitride.
In the present embodiment, the material of described gate dielectric material layer 201 is silicon oxide, described gate material layers
The material of 202 is polysilicon.The material of described protection material layer 203 is silicon oxide, can use deposition work
Skill forms described protection material layer 203 on described gate material layers 202 surface, it would however also be possible to employ oxidation technology,
Described gate material layers 202 surface is aoxidized, forms described protection material layer 203.The present invention's
In one embodiment, the thickness of described protection material layer 203 is 1nm～10nm, it is possible to described grid material
Enough protective effects are played on the bed of material 202 surface.
Refer to Fig. 5, etch described gate material layers 202 (refer to Fig. 4) and gate dielectric material layer
201 (refer to Fig. 4), to substrate 100 surface, form grid structure, and described grid structure includes covering
The gate dielectric layer 201a of part the second semiconductor layer and the grid 202a being positioned at described gate dielectric layer surface.
Concrete, described gate material layers 202 is formed Patterned masking layer, described pattern mask
Layer can be photoresist layer, and described Patterned masking layer defines size and the position of grid structure to be formed
Put, then, gate material layers 202 described in described Patterned masking layer as mask etching and gate medium material
The bed of material 201, forms grid structure, exposes the surface of the second semiconductor layer 103 of grid structure both sides.
Grid 202a, shape after described gate dielectric material layer 201 etching is formed after described gate material layers 202 etching
Become gate dielectric layer 201a.
In the present embodiment, described gate material layers 202 surface is formed with protection material layer 203 and (refer to figure
4), it is sequentially etched described protection material layer 203, gate material layers 202 and gate dielectric material layer 201, shape
Become grid structure.Described grid structure includes gate dielectric layer 201a, is positioned at the grid on gate dielectric layer 201a surface
Pole 202a and be positioned at the protective layer 203a of grid 202a top surface.Described protective layer 203a is follow-up
Technique is protected the top surface of described grid 202a.
In the present embodiment, the material of described gate dielectric layer 201a is silicon oxide, the material of described grid 202a
It is silicon oxide for polysilicon, described protective layer 203a material.
In the present embodiment, the follow-up source-drain electrode formed in grid structure both sides, the length of described grid structure
Less than 100nm, described grid structural length is the source-drain electrode line direction being parallel to grid structure both sides
Size.
Refer to Fig. 6, carry out ion is lightly doped in the second semiconductor layer 103 of described grid structure both sides
Inject.
In the present embodiment, being formed after described grid structure, can be to the of described grid structure both sides
Two semiconductor layers 103 carry out ion implanting is lightly doped, at the second semiconductor layer of described grid structure both sides
Formed in 103 and district 103a is lightly doped.
The described dopant ion type that ion implanting employing is lightly doped and the type phase of transistor to be formed
With, if described transistor to be formed is nmos pass transistor, then described in the doping of ion implanting is lightly doped
Ion is one or more ions in n-type doping ion, such as P, As or Sb；Shape is treated described in if
The transistor become is PMOS transistor, then described in the dopant ion of ion implanting is lightly doped is p-type doping
One or more ions in ion, such as B, Ga or In.
Ion implanted region 103a is lightly doped described in formation and can aid in the short-channel effect improving transistor,
Improve the performance of transistor.
During ion implanted region 103a being lightly doped described in being formed, described grid 202a top is protected
Layer 203a covers, it is to avoid described grid 202a, by implant damage, affects the performance of grid 202a.
In other embodiments of the invention, it is also possible to district 103a described in being formed without, is lightly doped.
Refer to Fig. 7, form side wall on described gate structure sidewall surface.
In the present embodiment, described side wall includes the first side wall 204 and the position covering gate structure sidewall surface
The second side wall 205 in the first side wall 204 surface.In the present embodiment, the material of described first side wall 204
Material for silicon oxide, described second side wall 205 is silicon nitride.Described first side wall 204 is used for repairing
Etching is formed during grid 202a, and the etching injury that causes described grid 202a sidewall surfaces is also protected
Described grid structure, described second side wall 205 for limit the source-drain electrode and grid 202a that are subsequently formed it
Between distance.
In other embodiments of the present invention, the material of described second side wall 205 can also is that low-K dielectric material
Material, such as silicon oxide carbide, many empty silicon oxides etc., can reduce the source-drain electrode raised and grid being subsequently formed
Parasitic capacitance between the 202a of pole.
The method forming described side wall includes: at described second semiconductor layer 103 surface, grid structure table
Face sequentially forms the first spacer material layer and is positioned at the second spacer material layer on the first spacer material layer surface,
Then use without mask etching technique, etch described second side wall along the direction being perpendicular to substrate 100 surface
Material layer and the first spacer material layer, remove grid structure top surface and the second semiconductor layer 103
Second spacer material layer of part surface and the first spacer material layer, formed and cover gate structure sidewall surface
Side wall.
In other described examples of the present invention, it is also possible in forming described first spacer material layer, directly
Etch described first spacer material layer, form the first side wall being positioned at gate structure sidewall surface；Then,
The second side wall is formed again on described second semiconductor layer 103, grid structure top surface, the first side wall surface
Material layer, then etches described second spacer material layer, forms the second side wall being positioned at the first side wall surface.
In other embodiments of the invention, described side wall can be oxide-nitride-oxide or nitridation
The three level stack structure of silicon-silicon oxide-silicon nitride.
On the one hand described side wall protects described grid structure, on the other hand as the source raised being subsequently formed
Isolation structure between drain electrode and grid structure, between source-drain electrode and the grid structure raised described in restriction
Distance, it is to avoid be short-circuited between described source-drain electrode and grid structure, the performance of the transistor that impact is formed.
Refer to Fig. 8, form amorphous silicon layer 300, described amorphous on described second semiconductor layer 102 surface
Silicon layer 300 covers side wall, and the surface of described amorphous silicon layer 300 flushes with the top surface of grid structure.
Low-pressure chemical vapor deposition process can be used to form described amorphous silicon layer 300, and directly use extension
Technique second semiconductor layer 103 surface formed crystalline silicon compare, formed non-crystalline silicon depositing temperature relatively low,
Sedimentation rate is very fast, it is possible to effectively reduce process costs, improves efficiency.
Concrete, the method using low-pressure chemical vapor deposition process to form described amorphous silicon layer 300 includes:
Use SiH4As deposition gases, SiH4Flow be 30sccm～200sccm, temperature is 450 DEG C
～600 DEG C, pressure is 200mTorr～400mTorr.Described low-pressure chemical vapor deposition process is used to be formed
Non-crystalline silicon covers described second semiconductor layer 103 surface and side wall and protective layer 203a surface, the most right
Described non-crystalline silicon planarizes, and forms amorphous silicon layer 300, makes surface and the grid of described amorphous silicon layer 300
Electrode structure top surface flushes, in the present embodiment, and the surface of described amorphous silicon layer 300 and protective layer 203a
Surface flushes.Can use chemical mechanical milling tech that described non-crystalline silicon is planarized.
The surface of described amorphous silicon layer 300 flushes with protective layer 203a surface, it is simple to follow-up to described amorphous
Silicon layer 300 carries out metal induced longitudinal crystallization process.
Refer to Fig. 9, the amorphous silicon layer 300 (refer to Fig. 8) of described grid structure both sides is carried out gold
Belong to induced longitudinal crystallization to process, make described amorphous silicon layer 300 be changed into polysilicon layer 301.
In the present embodiment, the method carrying out metal induced longitudinal crystallization process includes: described grid structure,
Side wall and amorphous silicon layer 300 surface form the mask layer 401 with opening 401a, and described opening 401a is sudden and violent
Expose the part surface of the amorphous silicon layer 300 of grid structure both sides；At described mask layer 401 and opening 401a
Inner wall surface forms inducing metal layer 402；Carry out the first annealing so that amorphous silicon layer 300 is in induction
Crystallization under the induction of metal level 402, is changed into polysilicon layer 301.
The material of described mask layer 401 is silicon nitride or silicon oxide.The surface of described amorphous silicon layer 300 with
Grid structure top surface flushes, it is simple at the surface of described amorphous silicon layer 300 and grid structure top table
Face forms described mask layer 401.After can forming mask layer 401 by chemical vapor deposition method, right
Described mask layer 401 performs etching, and is formed and expose amorphous silicon layer 300 in described mask layer 401
Opening 401a.It is respectively provided with described opening 401a on amorphous silicon layer 300 surface of grid structure both sides, it is simple to
The inducing metal layer 402 formed all contacts with the amorphous silicon layer 300 of grid structure both sides so that grid is tied
The amorphous silicon layer 300 of structure both sides is all converted into polysilicon layer 301.
The material of described inducing metal layer 402 is the metals such as Al, Cu, Au, Ag, Ni or Pb.Permissible
Physical gas-phase deposition, such as sputtering technology, electron beam evaporation process or electroplating technology is used to form institute
State inducing metal layer 402.
In the present embodiment, the material of described inducing metal layer 402 is Ni, uses sputtering technology to be formed described
Inducing metal layer 402, concrete, described sputtering technology uses nickel target as target, and Ar is as sputtering gas
Body, wherein, the gas flow of Ar is 20sccm～100sccm, and pressure is 0.1Pa～10Pa, radio-frequency sputtering
Power density is 2W/cm2～10W/cm2。
The 1/2 of the thickness of described inducing metal layer 402 width less than opening 401a, it is to avoid open described
Mouth 401a fills up, the deposition quality of the inducing metal layer 402 that impact is formed.An enforcement in the present invention
In example, the thickness of described inducing metal layer 402 is 1nm～20nm.It is positioned at bottom described opening 401a
Inducing metal layer 402 is positioned at amorphous silicon layer 300 surface.
After forming described inducing metal layer 402, carry out the first annealing, described first annealing
At N2, carry out under Ar, He or Ne atmosphere, temperature is 350 DEG C～600 DEG C, and the time is 5h～20h.?
In described first annealing process, described inducing metal layer 402 forms gold with amorphous silicon layer 300 reaction
Belong to silicide layer, form nucleus and generate little silicon crystal grain, and at described metal silicide layer and amorphous
On the interface of silicon, metal silicide and silicon carry out displacement exchange, gradually form silicon crystal grain, along with crystal grain
Growth, final metal silicide layer can form cavity and crush, and then, the metallic silicon formed after crushing
The little agglomerate of compound is diffused in the top layer of non-crystalline silicon and forms a crystallization interval.Simultaneously as induction
Metal level 402 only covering part amorphous silicon layer 300, on the limit by described inducing metal layer 402 overlay area
On edge, form the lumps of a number of metal silicide, and in annealing process, transverse movement
Entering the amorphous silicon region being connected, the non-crystalline silicon on the path of described metal silicide transverse movement will be complete
Portion is crystallized, and forms polysilicon layer 301.
In the present embodiment, the material of described inducing metal layer 402 is nickel, described inducing metal layer 402 with
Amorphous silicon layer 300 reaction forms nickel-silicon compound, the lattice paprmeter of described nickel-silicon compound and crystalline silicon
Lattice paprmeter is close, the formation of the nucleus of the least lattice mismatch, beneficially crystalline silicon, thus
More favorably with the described polysilicon layer 301 of formation.
The width of the crystal grain in described polysilicon layer 301 is 0.8 μm～1 μm, crystal grain a length of
1 μm～15 μm.Follow-up in described polysilicon layer 301, carry out heavy doping ion injection, form source-drain electrode.
For the transistor that current size is less, the crystallite dimension in described polysilicon layer 301 can provide higher
Carrier mobility.In the present embodiment, the grid structural length of transistor to be formed is less than 100nm.
Compared with other crystallization methods, the crystallization temperature of described metal induced longitudinal crystallization processing procedure is relatively low,
Defect concentration in the polysilicon layer 301 formed is low, and the cost forming described polysilicon layer 301 is relatively low,
And the quality of the polysilicon layer 301 formed is high, be conducive to improving the performance of the transistor formed.
Refer to Figure 10, remove described inducing metal layer 402 (refer to Fig. 9) and mask layer 402 (please
With reference to Fig. 9).
Wet-etching technology is used to remove described mask layer 401 and inducing metal layer 402 respectively.The present embodiment
In, can use sulphuric acid and hydrogen peroxide mixed solution remove described inducing metal layer 402, described sulphuric acid and
The temperature of the mixed solution of hydrogen peroxide is 60 DEG C～130 DEG C.In the present embodiment, the material of described mask layer 401
Material is silicon nitride, and phosphoric acid solution can be used to remove described mask layer 401, and the quality of described phosphoric acid solution is divided
Number is 85%～95%, and temperature is 80 DEG C～120 DEG C.
In other embodiments of the invention, remove described inducing metal layer 402 and mask layer 401 it
After, it is also possible to carry out the second annealing, make the crystal grain continued growth in described polysilicon layer 301, from
And improve the size of described crystal grain further, thus improve the carrier mobility in the source-drain electrode being subsequently formed
Rate, improves the performance of the transistor formed.
In one embodiment of the invention, described second annealing is at N2, Ar, He or Ne atmosphere
Under carry out, temperature is 650 DEG C～1000 DEG C, and the time is 10min～60min.
Refer to Figure 11, be etched back to described polysilicon layer 301 (refer to Figure 10), make the polycrystalline after etching
The surface of silicon layer 301a is less than the top surface of grid structure.
After forming described polysilicon layer 301, use dry etch process that described polysilicon layer 301 is entered
Row is etched back to, and makes the surface top surface less than grid structure of the polysilicon layer 301a after described etching,
Thus avoid subsequent technique makes to occur between described polysilicon layer 301 and grid structure bridging, impact
The performance of the transistor formed.
Refer to Figure 12, in described grid structure both sides polysilicon layer 301a, form source-drain electrode 301b.
The polysilicon layer 301a of described grid structure both sides is carried out heavy doping ion injection, forms source-drain electrode
301b.The dopant ion type that described heavy doping ion is injected is identical with transistor types to be formed.If
Described transistor to be formed is nmos pass transistor, and the dopant ion that the most described heavy doping ion is injected is
One or more ions in n-type doping ion, such as P, As or Sb；If described crystal to be formed
Pipe is PMOS transistor, and the dopant ion that the most described heavy doping ion is injected is p-type dopant ion, example
Such as one or more ions in B, Ga or In.
In other embodiments of the invention, it is also possible to the second half below described polysilicon layer 301a are led
Body layer 103 carries out heavy doping ion injection.
Surface due to described source-drain electrode 301b is higher than the surface of the second semiconductor layer 103 so that described source
The thickness of drain electrode 301b increases, and contributes to reducing the source-drain series resistance of transistor, and, described source and drain
Pole 301b has enough thickness, can form metal silicide layer on described source-drain electrode 301b surface,
Reduce the surface contacted resistance of described source-drain electrode 301b further, thus improve the performance of the transistor of formation.
In embodiments of the invention, directly the second semiconductor layer surface in grid structure both sides forms amorphous
Silicon, is then processed by metal induced longitudinal crystallization and makes described amorphous silicon layer be changed into polysilicon layer, then
The source-drain electrode of transistor is formed in described polysilicon layer.With directly employing epitaxy technique at the second quasiconductor
Layer surface forms crystalline silicon and compares, and the depositing temperature of formation non-crystalline silicon is relatively low, sedimentation rate is very fast, it is possible to
Effectively reduce process costs, improve efficiency.And metal induced longitudinal crystallization processes, the crystallization temperature of process
Spending relatively low, the defect concentration in the polysilicon layer of formation is low, and the cost forming described polysilicon layer is relatively low,
And the quality of the polysilicon layer formed is high, be conducive to improving the performance of the transistor formed.
Embodiments of the invention also provide for a kind of transistor using said method to be formed.
Refer to Figure 12, described transistor includes: substrate 100, and described substrate 100 includes: the first half
Conductor layer 101, the insulating barrier 102 being positioned on the first semiconductor layer 101 and be positioned at insulating barrier 102 surface
Second semiconductor layer 103；It is positioned at the grid structure on described second semiconductor layer 103, described grid structure
Including the gate dielectric layer 201a of covering part the second semiconductor layer 103 be positioned at described gate dielectric layer 201a
The grid 202a on surface；It is positioned at the side wall on described gate structure sidewall surface；It is positioned at described second quasiconductor
The polysilicon layer 301 on layer surface, described polysilicon layer covers side wall and the surface of described amorphous silicon layer, and institute
The surface stating polysilicon layer flushes less than the top surface of grid structure；It is positioned at described grid structure both sides
Source-drain electrode 301b in polysilicon layer.
The material of described first semiconductor layer 101 is the semi-conducting materials such as silicon, germanium, SiGe, described absolutely
The material of edge layer 102 can be the insulating dielectric materials such as silicon oxide, silicon oxynitride, described second quasiconductor
The material of layer 103 is the semi-conducting materials such as silicon, germanium, SiGe.In the present embodiment, described substrate 100
For silicon substrate at the insulation end, concrete, the material of described first semiconductor layer 101 is silicon, insulating barrier 102
Material be silicon oxide, the material of the second semiconductor layer 103 be silicon.
Described grid structure includes the gate dielectric layer 201a of covering part the second semiconductor layer and is positioned at described grid
The grid 202a of dielectric layer surface.In the present embodiment, described grid structure also includes being positioned at grid 202a top
The protective layer 203a on surface, portion.Described protective layer 203a protects the top surface of described grid 202a.
In the present embodiment, it is also formed with being lightly doped in the second semiconductor layer 103 of described grid structure both sides
Ion implanted region 103a, described in the dopant ion type that is lightly doped in ion implanted region 103a and transistor
Type is consistent, described in ion implanted region 103a be lightly doped can aid in the short-channel effect improving transistor,
Improve the performance of transistor.
Described side wall includes the first side wall 204 covering gate structure sidewall surface and is positioned at the first side wall 204
Second side wall 205 on surface.In the present embodiment, the material of described first side wall 204 is silicon oxide, described
The material of the second side wall 205 is silicon nitride.
The surface of described polysilicon layer is less than the top surface of grid structure, in described polysilicon layer 301
The width of crystal grain is 0.8 μm～1 μm, and a length of 1 μm of crystal grain～15 μm are less for current size
Transistor, the crystallite dimension in described polysilicon layer 301 can provide higher carrier mobility.This
In embodiment, the grid structural length of transistor to be formed is less than 100nm.
Dopant ion type in described source-drain electrode 301b is consistent with the type of transistor.Due to described source and drain
The surface of pole 301b is higher than the surface of the second semiconductor layer 103 so that the thickness of described source-drain electrode 301b
Increase, contribute to reducing the source-drain series resistance of transistor, and, described source-drain electrode 301b has enough
Thickness, metal silicide layer can be formed on described source-drain electrode 301b surface, reduce further described source
The surface contacted resistance of drain electrode 301b, thus improve the performance of the transistor of formation.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a transistor, it is characterised in that including:
Thering is provided substrate, described substrate includes: the first semiconductor layer, the insulation being positioned on the first semiconductor layer
Layer and the second semiconductor layer being positioned at surface of insulating layer；
Forming grid structure on described second semiconductor layer, described grid structure includes covering part second
The gate dielectric layer of semiconductor layer and the grid being positioned at described gate dielectric layer surface；
Side wall is formed on described gate structure sidewall surface；
Forming amorphous silicon layer in described second semiconductor layer surface, described amorphous silicon layer covers side wall and described
The surface of amorphous silicon layer flushes with the top surface of grid structure；
The amorphous silicon layer of described grid structure both sides is carried out metal induced longitudinal crystallization process, makes described non-
Crystal silicon layer is changed into polysilicon layer；
It is etched back to described polysilicon layer, makes the surface top surface less than grid structure of described polysilicon layer；
Source-drain electrode is formed in the polysilicon layer of described grid structure both sides.
The forming method of transistor the most according to claim 1, it is characterised in that carry out metal and laterally lure
The method leading Crystallizing treatment includes: is formed on described grid structure, side wall and amorphous silicon layer surface and has
The mask layer of opening, described opening exposes the part surface of the amorphous silicon layer of grid structure both sides；?
Described mask layer and opening inner wall surface form inducing metal layer；Carry out the first annealing so that non-
Crystal silicon layer is crystallization under the induction of inducing metal layer, is changed into polysilicon layer；Remove described inducing metal
Layer and mask layer.
The forming method of transistor the most according to claim 2, it is characterised in that described inducing metal layer
Material be Al, Cu, Au, Ag, Ni or Pb.
The forming method of transistor the most according to claim 3, it is characterised in that described inducing metal layer
Thickness be 1nm～20nm.
The forming method of transistor the most according to claim 3, it is characterised in that employing sputtering technology,
Electron beam evaporation forms described inducing metal layer.
The forming method of transistor the most according to claim 2, it is characterised in that described first annealing treatment
Reason is at N2, carry out under Ar, He or Ne atmosphere, temperature is 350 DEG C～600 DEG C, and the time is 5h～20h.
The forming method of transistor the most according to claim 2, it is characterised in that in described polysilicon layer
The width of crystal grain be 0.8 μm～1 μm, a length of 1 μm of crystal grain～15 μm.
The forming method of transistor the most according to claim 2, it is characterised in that also include: removing
After described inducing metal layer and mask layer, carry out the second annealing, in making described polysilicon layer
Crystallite dimension increases.
The forming method of transistor the most according to claim 8, it is characterised in that described second annealing treatment
Reason is at N2, carry out under Ar, He or Ne atmosphere, temperature is 650 DEG C～1000 DEG C, and the time is
10min～60min.
The forming method of transistor the most according to claim 2, it is characterised in that the material of described mask layer
Material is silicon nitride or silicon oxide.
The forming method of 11. transistors according to claim 1, it is characterised in that forming described side wall
Before, carry out ion implanting is lightly doped in the second semiconductor layer of described grid structure both sides.
The forming method of 12. transistors according to claim 1, it is characterised in that described grid structure is also
Including the protective layer being positioned at gate top surface.
The forming method of 13. transistors according to claim 12, it is characterised in that form described grid knot
The method of structure includes: sequentially forms gate dielectric material layer at described substrate surface, is positioned at gate dielectric material
The gate material layers on layer surface and be positioned at the protection material layer on gate material layers surface；Etch described guarantor
Protective material layer, gate material layers and gate dielectric material layer, to substrate surface, form grid structure.
The forming method of 14. transistors according to claim 12, it is characterised in that described gate dielectric layer
Material be silicon oxide, grid material be polysilicon, protective layer material be silicon oxide.
The forming method of 15. transistors according to claim 1, it is characterised in that use low pressure chemical gas
Phase depositing operation forms described amorphous silicon layer, specifically includes: use SiH4As deposition gases, SiH4
Flow be 30sccm～200sccm, temperature is 450 DEG C～600 DEG C, and pressure is
200mTorr～400mTorr.
The forming method of 16. transistors according to claim 2, it is characterised in that use wet etching work
Skill removes described mask layer and inducing metal layer.
The forming method of 17. transistors according to claim 16, it is characterised in that use sulphuric acid and dioxygen
The mixed solution of water removes described inducing metal layer, the temperature of the mixed solution of described sulphuric acid and hydrogen peroxide
It it is 60 DEG C～130 DEG C.
The forming method of 18. transistors according to claim 1, it is characterised in that described grid structure is long
Degree is less than 100nm, and described grid structural length is the source and drain that grid structure is parallel to grid structure both sides
The size in line direction, pole.
The forming method of 19. transistors according to claim 1, it is characterised in that described substrate is insulation
Silicon substrate at the end.
20. 1 kinds of transistors formed according to either method in claim 1 to 19, it is characterised in that including:
Substrate, described substrate includes: the first semiconductor layer, the insulating barrier being positioned on the first semiconductor layer and
It is positioned at the second semiconductor layer of surface of insulating layer；
Being positioned at the grid structure on described second semiconductor layer, described grid structure includes covering part second
The gate dielectric layer of semiconductor layer and the grid being positioned at described gate dielectric layer surface；
It is positioned at the side wall on described gate structure sidewall surface；
Being positioned at the polysilicon layer of described second semiconductor layer surface, described polysilicon layer covers side wall and described
The surface of amorphous silicon layer, and the surface of described polysilicon layer flushes less than the top surface of grid structure；
It is positioned at the source-drain electrode of the polysilicon layer of described grid structure both sides.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020133059A1 (en) * | 2018-12-27 | 2020-07-02 | 深圳市柔宇科技有限公司 | Functional device and fabrication method therefor |
| CN113539809A (en) * | 2021-07-19 | 2021-10-22 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582784A (en) * | 1991-09-20 | 1993-04-02 | Sony Corp | Manufacture of mis-type semiconductor device |
| CN1431718A (en) * | 2001-12-19 | 2003-07-23 | 三星Sdi株式会社 | Multigrid thin film transistor utilizing metal for inducing horizontal crystallizing and its mfg. method |
| CN101834138A (en) * | 2010-02-09 | 2010-09-15 | 广东中显科技有限公司 | Method for preparing transistor device of crystallized thin film |
| US20130207189A1 (en) * | 2012-01-06 | 2013-08-15 | International Business Machines Corporation | Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same |
| US20130264658A1 (en) * | 2011-01-31 | 2013-10-10 | International Business Machines Corporation | Reduced S/D Contact Resistance of III-V Mosfet Using Low Temperature Metal-Induced Crystallilzation of n+ Ge |
-
2015
- 2015-01-30 CN CN201510051501.7A patent/CN105990138B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582784A (en) * | 1991-09-20 | 1993-04-02 | Sony Corp | Manufacture of mis-type semiconductor device |
| CN1431718A (en) * | 2001-12-19 | 2003-07-23 | 三星Sdi株式会社 | Multigrid thin film transistor utilizing metal for inducing horizontal crystallizing and its mfg. method |
| CN101834138A (en) * | 2010-02-09 | 2010-09-15 | 广东中显科技有限公司 | Method for preparing transistor device of crystallized thin film |
| US20130264658A1 (en) * | 2011-01-31 | 2013-10-10 | International Business Machines Corporation | Reduced S/D Contact Resistance of III-V Mosfet Using Low Temperature Metal-Induced Crystallilzation of n+ Ge |
| US20130207189A1 (en) * | 2012-01-06 | 2013-08-15 | International Business Machines Corporation | Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020133059A1 (en) * | 2018-12-27 | 2020-07-02 | 深圳市柔宇科技有限公司 | Functional device and fabrication method therefor |
| CN113539809A (en) * | 2021-07-19 | 2021-10-22 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN113539809B (en) * | 2021-07-19 | 2023-07-04 | 长鑫存储技术有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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