CN113539809A - Preparation method of semiconductor structure and semiconductor structure - Google Patents

Preparation method of semiconductor structure and semiconductor structure Download PDF

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Publication number
CN113539809A
CN113539809A CN202110813646.1A CN202110813646A CN113539809A CN 113539809 A CN113539809 A CN 113539809A CN 202110813646 A CN202110813646 A CN 202110813646A CN 113539809 A CN113539809 A CN 113539809A
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layer
forming
grid
gate
material layer
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CN113539809B (en
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张仕然
陈洋
韩欣茹
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate

Abstract

The application relates to a preparation method of a semiconductor structure and the semiconductor structure, wherein the method comprises the following steps: providing a substrate with a grid pattern structure formed on the upper surface; forming a gate sidewall protection layer on at least the sidewall of the gate pattern structure; performing ion implantation on the grid pattern structure; and forming a gate conductive layer at least on the upper surface of the gate pattern structure. The method and the device avoid the phenomenon that the side wall of the grid electrode inclines or distorts in the process of etching the heterostructure subsequently caused by doping nonuniformity, effectively optimize the appearance of the grid electrode, and improve the yield and the reliability of manufactured semiconductor products.

Description

Preparation method of semiconductor structure and semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
With the continuous development of semiconductor integrated circuit device technology, the market demand for the yield and reliability of semiconductor products is continuously increased.
However, in the process of a conventional Complementary Metal Oxide Semiconductor (cmos) device, ion doping is required after the formation of a gate Oxide layer of the cmos device to improve the electrical performance of the gate, and the non-uniformity of doping causes a gate sidewall tilt or twist phenomenon in the subsequent process of etching the heterostructure, which affects the uniformity of an electric field in the working process of the cmos device and seriously affects the yield and the working reliability of the cmos device.
Disclosure of Invention
Accordingly, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure, which can avoid the gate sidewall inclination or distortion phenomenon caused by the non-uniformity of doping in the subsequent process of etching the heterostructure, thereby effectively optimizing the gate morphology and improving the yield and reliability of the manufactured semiconductor product.
To achieve the above and other related objects, an aspect of the present application provides a method for fabricating a semiconductor structure, comprising the steps of:
providing a substrate with a grid pattern structure formed on the upper surface;
forming a gate sidewall protection layer on at least the sidewall of the gate pattern structure;
performing ion implantation on the grid pattern structure;
and forming a gate conductive layer at least on the upper surface of the gate pattern structure.
In the method for manufacturing a semiconductor structure in the above embodiment, after the gate sidewall protection layer is formed on the sidewall of the gate pattern structure, ion implantation is performed on the gate pattern structure through the top of the gate pattern structure to form a doped gate material layer in the gate pattern structure, and then a gate conductive layer is formed on the upper surface of the gate pattern structure. Because the side wall of the grid graphic structure is covered and protected by the grid side wall protective layer in the process of etching the formed heterostructure after ion implantation, the phenomenon that the grid side wall is inclined or distorted in the process of etching the heterostructure caused by doping nonuniformity is avoided, the grid morphology is effectively optimized, and the yield and the reliability of manufactured semiconductor products are improved.
Another aspect of the present application provides a semiconductor structure, including a substrate, a gate sidewall protection layer and a gate conductive layer, wherein a gate pattern structure is formed on an upper surface of the substrate; the grid side wall protection layer at least covers the side wall of the grid graphic structure, wherein a doped grid material layer is formed in the grid graphic structure; the grid conducting layer at least covers the upper surface of the grid pattern structure. Because the side wall of the grid graphic structure is covered and protected by the grid side wall protective layer in the process of etching the formed heterostructure after ion implantation, the phenomenon that the grid side wall is inclined or distorted in the process of etching the heterostructure caused by doping nonuniformity is avoided, the grid morphology is effectively optimized, and the yield and the reliability of manufactured semiconductor products are improved.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those applications disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered limiting of the scope of any of the disclosed applications, the presently described embodiments and/or examples, and the presently understood best mode of such applications.
Fig. 1 is a flow chart illustrating a method for fabricating a semiconductor structure provided in an embodiment of the present application.
Fig. 2 to fig. 3 are schematic cross-sectional views illustrating the structure obtained in step S1 in the method for manufacturing a semiconductor structure provided in the embodiments of the present application.
Fig. 4 to fig. 5 are schematic cross-sectional views illustrating the structure obtained in step S2 in the method for manufacturing a semiconductor structure provided in the embodiments of the present application.
Fig. 6 is a schematic cross-sectional view illustrating a structure obtained in step S3 in a method for manufacturing a semiconductor structure provided in an embodiment of the present application.
Fig. 7 to 12 are schematic cross-sectional views illustrating the structure obtained in step S4 in the method for fabricating a semiconductor structure provided in the embodiments of the present application;
description of reference numerals:
10. a substrate; 11. a trench; 12. a dielectric material layer; 13. a gate oxide layer; 141. a gate material layer; 14. a gate pattern structure; 15. a first patterned photoresist layer; 161. a first protective material layer; 16. a gate sidewall protection layer; 171. a layer of conductive material; 17. a gate conductive layer; 181. a second protective material layer; 18. a top protective layer; 191. a first mask layer; 19. a first graphical mask layer; 201. a second mask layer; 202. a third mask layer; 203. and a second patterned photoresist layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
Please refer to fig. 1-12. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present application, and although the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1, in one embodiment of the present application, a method for fabricating a semiconductor structure is provided, which includes the steps of:
step S1: providing a substrate with a grid pattern structure formed on the upper surface;
step S2: forming a gate sidewall protection layer on at least the sidewall of the gate pattern structure;
step S3: performing ion implantation on the grid pattern structure;
step S4: and forming a gate conductive layer at least on the upper surface of the gate pattern structure.
Specifically, with reference to fig. 1, after a gate sidewall protection layer is formed on the sidewall of the gate pattern structure, ion implantation is performed on the gate pattern structure through the top of the gate pattern structure to form a doped gate material layer in the gate pattern structure, and then a gate conductive layer is formed on the upper surface of the gate pattern structure. Because the side wall of the grid graphic structure is covered and protected by the grid side wall protective layer in the process of etching the formed heterostructure after ion implantation, the phenomenon that the grid side wall is inclined or distorted in the process of etching the heterostructure caused by doping nonuniformity is avoided, the grid morphology is effectively optimized, and the yield and the reliability of manufactured semiconductor products are improved.
In step S1, referring to step S1 of fig. 1, fig. 2 and fig. 3, a substrate 10 having a gate pattern structure 14 formed on an upper surface thereof is provided, wherein the substrate 10 may include, but is not limited to, a semiconductor material (e.g., silicon, germanium, silicon germanium, etc.) or a III-V compound (e.g., GaP, GaAs, GaSb, etc.). In some embodiments, the substrate 10 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. A person skilled in the art may select the type of substrate according to the type of transistors formed on the substrate 10 and therefore the type of substrate 10 should not limit the scope of the present application.
By way of example, continuing with reference to step S1 in fig. 1, fig. 2, and fig. 3, step S1 may include the following steps:
step S11: providing a substrate 10, wherein the substrate 10 is provided with a groove 11, and the groove 11 is filled with a dielectric material layer 12;
step S12: forming a gate oxide layer 13, wherein the gate oxide layer 13 covers the upper surface of the substrate 10 and the upper surface of the dielectric material layer 12;
step S13: forming a gate material layer 141 on the top surface of the gate oxide layer 13, and forming a first patterned photoresist layer 15 on the top surface of the gate material layer 141;
step S14: the gate material layer 141 is etched based on the first patterned photoresist layer 15 to form the gate pattern structure 14.
As an example, the number of the grooves 11 in step S11 may be plural, and the depth of each groove 11 may be the same or different; the width of each groove 11 may be the same or different; the depth of the trench 11 is less than the thickness of the substrate 10.
As an example, in step S12, a gate oxide layer 13 covering the upper surface of the substrate 10 and the upper surface of the dielectric material layer 12 may be formed by a deposition process. The material of the gate oxide layer 13 may include, but is not limited to, silicon dioxide.
As an example, in step S13, a deposition process may be used to form a gate material layer 141 on the upper surface of the gate oxide layer 13, and a first patterned photoresist layer 15 is formed on the upper surface of the gate material layer 141.
As an example, the gate material layer 141 may be etched using a dry etching process based on the first patterned photoresist layer 15 in step S14 to form the gate pattern structure 14. In this embodiment, the parameters of the adopted dry etching process include: qi (Qi)The body comprises fluorocarbon gas, HBr and Cl2And a carrier gas, the fluorocarbon gas comprising CF4、CHF3、CH2F2Or CH3F, the carrier gas is an inert gas, such as He.
As an example, with continued reference to fig. 3, the thicknesses of the gate oxide layers 13 adjacent to the lower surface of the gate pattern structure 14 may not be equal, for example, the thickness d1 may not be equal to the thickness d 2. In other embodiments of the present application, the thickness d2 may be set to d 1.
Referring to step S2 of fig. 1, fig. 4 and fig. 5, the step S2 of forming a gate sidewall protection layer 16 on at least the sidewalls of the gate pattern structure 14 includes:
step S21: forming a first protective material layer 161, wherein the first protective material layer 161 covers the upper surface and the sidewalls of the gate pattern structure 14 and the upper surface of the gate oxide layer 13;
step S22: the first protective material layer 161 on the upper surface of the gate oxide layer 13 and on the upper surface of the gate pattern structure 14 is removed, and the remaining first protective material layer 161 constitutes the gate sidewall protection layer 16.
As an example, in step S21, a deposition process may be used to form the first protective material layer 161, where the first protective material layer 161 covers the upper surface and the sidewalls of the gate pattern structure 14 and the upper surface of the gate oxide layer 13; the material of the first protective material layer 161 includes, but is not limited to, silicon nitride.
As an example, in step S22, the first protective material layer 161 on the upper surface of the gate oxide layer 13 and on the upper surface of the gate pattern structure 14 may be removed by a dry etching process, and the remaining first protective material layer 161 constitutes the gate sidewall protection layer 16.
Referring to step S3 in fig. 1 and fig. 6, the step of performing ion implantation on the gate pattern structure 14 in step S3 includes:
step S31: ion implantation of different conductivity types is performed for adjacent gate pattern structures 14.
As an example, continuing with step S3 in fig. 1 and fig. 6, P-type ion implantation and N-type ion implantation are performed on the adjacent gate pattern structures 14 to form heterostructures, respectively.
Referring to step S4 of fig. 1 and fig. 7, the step S4 of forming the gate conductive layer 17 on at least the upper surface of the gate pattern structure 14 may include:
step S41, forming a conductive material layer 171, wherein the conductive material layer 171 covers the upper surface of the gate pattern structure 14, the upper surface and the sidewalls of the gate sidewall protection layer 16, and the upper surface of the gate oxide layer 13;
in step S42, the conductive material layer 171 covering the gate sidewall protection layer 16 and the upper surface of the gate oxide layer 13 is removed, and the remaining conductive material layer 171 constitutes the gate conductive layer 17.
As an example, in step S41, a deposition process may be used to form the conductive material layer 171, wherein the conductive material layer 171 covers the upper surface of the gate pattern structure 14, the upper surface and the sidewalls of the gate sidewall protection layer 16, and the upper surface of the gate oxide layer 13. The material of the conductive material layer 171 includes, but is not limited to, one or more of titanium nitride, titanium, tungsten silicide, and tungsten.
As an example, in step S42, the conductive material layer 171 covering the gate sidewall protection layer 16 and the upper surface of the gate oxide layer 13 may be removed by a dry etching process, and the remaining conductive material layer 171 constitutes the gate conductive layer 17.
As an example, in an embodiment of the present application, step S4 is followed by:
step S5: and forming a top protective layer on the upper surface of the grid electrode conducting layer.
As an example, referring to fig. 7-12, the step of forming the top protective layer 18 in step S5 includes:
step S51: forming a conductive material layer 171, wherein the conductive material layer 171 covers the upper surface of the gate pattern structure 14, the upper surface and the sidewalls of the gate sidewall protection layer 16, and the upper surface of the gate oxide layer 13;
step S52: forming a second protection material layer 181 on the upper surface of the conductive material layer 171, wherein the upper surface of the second protection material layer 181 is higher than the upper surface of the gate pattern structure 14;
step S53: forming a first patterned mask layer 19 on the upper surface of the second protective material layer 181;
step S54: the second protective material layer 181 is etched on the basis of the first patterned masking layer 19 to form the top protective layer 18.
As an example, the material forming the conductive material layer 171 in step S51 may include one or more of titanium nitride, titanium, tungsten silicide, and tungsten.
As an example, in step S52, a deposition process may be used to form a second protective material layer 181 on the upper surface of the conductive material layer 171, wherein the upper surface of the second protective material layer 181 is higher than the upper surface of the gate pattern structure 14. The material of the second protective material layer 181 may include, but is not limited to, silicon nitride.
As an example, with continued reference to fig. 9-12, in step S53, a first patterned mask layer 19 is formed on the upper surface of the second protective material layer 181, including:
step S531: forming a first mask layer 191 on the upper surface of the second protective material layer 181;
step S532: forming a second patterned photoresist layer 203 on the upper surface of the first mask layer 191;
step S533: the first mask layer 191 is etched based on the second patterned photoresist layer 203 to form the first patterned mask layer 19.
As an example, the material of the first mask layer 191 in step S531 may include, but is not limited to, silicon dioxide.
As an example, the second patterned photoresist layer 203 formed in step S532 may include an anti-reflective layer (not shown) including a thin silicon anti-reflective layer (Si-ARC), an organic material bottom anti-reflective layer (organic BARC), a dielectric anti-reflective layer (DARC), or a combination of an organic bottom anti-reflective layer and a dielectric anti-reflective layer.
As an example, the first patterned mask layer 19 formed in step S533 may include a hard mask layer, which may be a single-layer structure or a multi-layer stacked structure, and may be made of silicon oxide.
As an example, with continued reference to fig. 9-12, after forming the first mask layer 191 on the upper surface of the second protective material layer 181 in step S531, the method includes:
step S5312: sequentially forming a second mask layer 201 and a third mask layer 202 on the upper surface of the first mask layer 191;
step S5313: forming a second patterned photoresist layer 203 on the upper surface of the third mask layer 202;
step S5314: etching the third mask layer 202 and the second mask layer 201 based on the second patterned photoresist layer 203 to form a second patterned mask layer (not shown);
step S5315: the first mask layer 191 is etched based on the second patterned mask layer to form a first patterned mask layer 19.
As an example, the material of the second mask layer 201 in step S5312 may include, but is not limited to, carbon, and the material of the third mask layer 202 may include, but is not limited to, silicon oxynitride.
As an example, after forming the top protection layer 18 in step S54, a step of removing the conductive material layer 171 covering the gate sidewall protection layer 16 and the upper surface of the gate oxide layer 13 is further included, so that the remaining conductive material layer 171 constitutes the gate conductive layer 17.
As an example, the material forming the gate sidewall protection layer 16 and the material forming the top protection layer 18 may be the same, for example, in one embodiment of the present application, the material forming the gate sidewall protection layer 16 and the material forming the top protection layer 18 both comprise silicon nitride.
As an example, the thickness of the gate sidewall protection layer 16 may be 1nm-5nm, for example, the thickness of the gate sidewall protection layer 16 may be 1nm, 2nm, 3nm, 4nm, or 5 nm.
As an example, the thickness of the top protection layer 18 is greater than or equal to the thickness of the gate sidewall protection layer 16 to avoid damage to the gate pattern structure 14 during subsequent etching processes.
As an example, the Deposition process in the embodiment of the present application may be one or more of a Flowable Chemical Vapor Deposition (FCVD) process, a High Density Plasma Deposition (HDP) process, a Plasma enhanced Deposition process, and an atomic layer Deposition process.
Referring to fig. 12, in one embodiment of the present application, a semiconductor structure is provided, which includes a substrate 10, a gate sidewall protection layer 16 and a gate conductive layer 17, wherein a gate pattern structure 14 is formed on an upper surface of the substrate 10; the gate sidewall protection layer 16 at least covers the sidewall of the gate pattern structure 14, wherein a doped gate material layer is formed in the gate pattern structure 14; the gate conductive layer 17 covers at least the upper surface of the gate pattern structure 14. Since the side wall of the gate pattern structure 14 is covered and protected by the gate side wall protection layer 16 in the process of etching the heterostructure after ion implantation, the phenomenon of gate side wall inclination or distortion caused by doping nonuniformity in the subsequent process of etching the heterostructure is avoided, the gate morphology is effectively optimized, and the yield and reliability of the manufactured semiconductor product are improved.
As an example, with continued reference to fig. 12, the semiconductor structure further includes a top protection layer 18, wherein the top protection layer 18 covers the upper surface of the gate conductive layer 17 to prevent damage to the gate pattern structure 14 caused by a subsequent process.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present application.
It should be understood that the steps described are not to be performed in the exact order recited, and that the steps may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps described may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least some of the sub-steps or stages of other steps.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (17)

1. A method for manufacturing a semiconductor structure, comprising the steps of:
providing a substrate with a grid pattern structure formed on the upper surface;
forming a gate sidewall protection layer on at least the sidewall of the gate pattern structure;
performing ion implantation on the grid pattern structure;
and forming a gate conductive layer at least on the upper surface of the gate pattern structure.
2. The method of claim 1, further comprising, after forming a gate conductive layer on at least the top surface of the gate pattern structure:
and forming a top protective layer on the upper surface of the grid electrode conducting layer.
3. The method as claimed in claim 2, wherein the gate sidewall protection layer is formed of the same material as the top protection layer, and the thickness of the gate sidewall protection layer is 1nm to 5 nm.
4. The method of claim 2, wherein a thickness of the top protection layer is greater than or equal to a thickness of the gate sidewall protection layer.
5. The method of claim 3, wherein the material forming the gate sidewall protection layer and the material forming the top protection layer comprise silicon nitride.
6. The method for fabricating a semiconductor structure according to any one of claims 2 to 5, wherein the providing of the substrate having the gate pattern structure on the upper surface comprises:
providing a substrate, wherein the substrate is provided with a groove, and the groove is filled with a dielectric material layer;
forming a grid oxide layer, wherein the grid oxide layer covers the upper surface of the substrate and the upper surface of the dielectric material layer;
forming a gate material layer on the upper surface of the gate oxide layer, and forming a first patterned photoresist layer on the upper surface of the gate material layer;
and etching the grid material layer based on the first patterned photoresist layer to form the grid pattern structure.
7. The method as claimed in claim 6, wherein the gate oxide layers adjacent to the lower surface of the gate pattern structure have different thicknesses.
8. The method as claimed in claim 6, wherein forming a gate sidewall protection layer on at least a sidewall of the gate pattern structure comprises:
forming a first protective material layer, wherein the first protective material layer covers the upper surface and the side wall of the grid graphic structure and the upper surface of the grid oxide layer;
and removing the first protective material layer on the upper surface of the grid oxide layer and on the upper surface of the grid graphic structure, wherein the remained first protective material layer forms the grid side wall protective layer.
9. The method of claim 8, wherein the step of forming the top protective layer comprises:
forming a conductive material layer, wherein the conductive material layer covers the upper surface of the grid graphic structure, the upper surface and the side wall of the grid side wall protection layer and the upper surface of the grid oxidation layer;
forming a second protective material layer on the upper surface of the conductive material layer, wherein the upper surface of the second protective material layer is higher than the upper surface of the gate pattern structure;
forming a first graphical mask layer on the upper surface of the second protective material layer;
and etching the second protective material layer based on the first patterned mask layer to form the top protective layer.
10. The method of claim 9, wherein the step of forming the gate conductive layer comprises:
and removing the conductive material layer covering the upper surfaces of the grid side wall protection layer and the grid oxidation layer, and forming the grid conductive layer by the reserved conductive material layer.
11. The method of claim 9, wherein forming a first patterned mask layer on the top surface of the second protective material layer comprises:
forming a first mask layer on the upper surface of the second protective material layer;
forming a second graphical photoresist layer on the upper surface of the first mask layer;
and etching the first mask layer based on the second patterned photoresist layer to form the first patterned mask layer.
12. The method of claim 9, wherein forming a first patterned mask layer on the top surface of the second protective material layer comprises:
forming a first mask layer on the upper surface of the second protective material layer;
sequentially forming a second mask layer and a third mask layer on the upper surface of the first mask layer;
forming a second graphical photoresist layer on the upper surface of the third mask layer;
etching the third mask layer and the second mask layer based on the second patterned photoresist layer to form a second patterned mask layer;
and etching the first mask layer based on the second patterned mask layer to form the first patterned mask layer.
13. The method of claim 9, wherein:
the material forming the conductive material layer comprises one or more of titanium nitride, titanium, tungsten silicide and tungsten.
14. The method of any of claims 1-5, wherein the step of performing ion implantation on the gate pattern structure comprises:
and performing ion implantation of different conductivity types on the adjacent gate pattern structures.
15. The method as claimed in claim 14, wherein P-type ion implantation and N-type ion implantation are performed respectively on adjacent gate pattern structures.
16. A semiconductor structure, comprising:
a substrate, wherein a grid pattern structure is formed on the upper surface of the substrate;
the grid side wall protection layer at least covers the side wall of the grid graphic structure, wherein a doped grid material layer is formed in the grid graphic structure;
and the grid conducting layer at least covers the upper surface of the grid pattern structure.
17. The semiconductor structure of claim 16, further comprising:
and the top protective layer covers the upper surface of the grid conducting layer.
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Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953601A (en) * 1998-02-17 1999-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. ESD implantation scheme for 0.35 μm 3.3V 70A gate oxide process
US6368907B1 (en) * 1999-11-29 2002-04-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device
US6432763B1 (en) * 2001-03-15 2002-08-13 Advanced Micro Devices, Inc. Field effect transistor having doped gate with prevention of contamination from the gate during implantation
US20020197837A1 (en) * 2001-06-19 2002-12-26 Kwak Noh-Yeal Method of forming a MOS transistor of a semiconductor device
JP2003031683A (en) * 2001-07-19 2003-01-31 Sony Corp Semiconductor device and its manufacturing method
US20030030077A1 (en) * 2001-08-07 2003-02-13 Jung Woo-Chan Semiconductor device and method for manufacturing the same
US20040023478A1 (en) * 2002-07-31 2004-02-05 Samavedam Srikanth B. Capped dual metal gate transistors for CMOS process and method for making the same
US20050153500A1 (en) * 2003-12-31 2005-07-14 Jeong Min H. Method for fabricating a MOS transistor
US20050272193A1 (en) * 2004-06-08 2005-12-08 Kim Dong S Method for manufacturing semiconductor device
US20080105899A1 (en) * 2006-11-03 2008-05-08 Samsung Electronics Co., Ltd. Semiconductor device with epitaxially grown layer and fabrication method
KR20080087269A (en) * 2007-03-26 2008-10-01 주식회사 하이닉스반도체 Method for fabricating semiconductor device
CN102468239A (en) * 2010-11-16 2012-05-23 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN103779277A (en) * 2012-10-18 2014-05-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device manufacturing method
CN104037071A (en) * 2013-03-05 2014-09-10 格罗方德半导体公司 Methods For Forming Integrated Circuit Systems Employing Fluorine Doping
CN104465376A (en) * 2013-09-17 2015-03-25 中芯国际集成电路制造(上海)有限公司 Transistor and forming method thereof
CN105990138A (en) * 2015-01-30 2016-10-05 中芯国际集成电路制造(上海)有限公司 Transistor and forming method thereof
CN106486350A (en) * 2015-08-26 2017-03-08 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN111129107A (en) * 2018-10-30 2020-05-08 长鑫存储技术有限公司 Semiconductor device and method for manufacturing the same

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953601A (en) * 1998-02-17 1999-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. ESD implantation scheme for 0.35 μm 3.3V 70A gate oxide process
US6368907B1 (en) * 1999-11-29 2002-04-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device
US6432763B1 (en) * 2001-03-15 2002-08-13 Advanced Micro Devices, Inc. Field effect transistor having doped gate with prevention of contamination from the gate during implantation
US20020197837A1 (en) * 2001-06-19 2002-12-26 Kwak Noh-Yeal Method of forming a MOS transistor of a semiconductor device
JP2003031683A (en) * 2001-07-19 2003-01-31 Sony Corp Semiconductor device and its manufacturing method
US20030030077A1 (en) * 2001-08-07 2003-02-13 Jung Woo-Chan Semiconductor device and method for manufacturing the same
US20040023478A1 (en) * 2002-07-31 2004-02-05 Samavedam Srikanth B. Capped dual metal gate transistors for CMOS process and method for making the same
US20050153500A1 (en) * 2003-12-31 2005-07-14 Jeong Min H. Method for fabricating a MOS transistor
US20050272193A1 (en) * 2004-06-08 2005-12-08 Kim Dong S Method for manufacturing semiconductor device
US20080105899A1 (en) * 2006-11-03 2008-05-08 Samsung Electronics Co., Ltd. Semiconductor device with epitaxially grown layer and fabrication method
KR20080087269A (en) * 2007-03-26 2008-10-01 주식회사 하이닉스반도체 Method for fabricating semiconductor device
CN102468239A (en) * 2010-11-16 2012-05-23 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN103779277A (en) * 2012-10-18 2014-05-07 中芯国际集成电路制造(上海)有限公司 Semiconductor device manufacturing method
CN104037071A (en) * 2013-03-05 2014-09-10 格罗方德半导体公司 Methods For Forming Integrated Circuit Systems Employing Fluorine Doping
CN104465376A (en) * 2013-09-17 2015-03-25 中芯国际集成电路制造(上海)有限公司 Transistor and forming method thereof
CN105990138A (en) * 2015-01-30 2016-10-05 中芯国际集成电路制造(上海)有限公司 Transistor and forming method thereof
CN106486350A (en) * 2015-08-26 2017-03-08 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN111129107A (en) * 2018-10-30 2020-05-08 长鑫存储技术有限公司 Semiconductor device and method for manufacturing the same

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