CN111129107A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN111129107A
CN111129107A CN201811278696.9A CN201811278696A CN111129107A CN 111129107 A CN111129107 A CN 111129107A CN 201811278696 A CN201811278696 A CN 201811278696A CN 111129107 A CN111129107 A CN 111129107A
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ion implantation
conductive channel
doped region
lightly doped
semiconductor device
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蔡宗叡
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the same, wherein the semiconductor device includes: a semiconductor substrate comprising a conductive channel; a first doped region located on a first side of the conductive channel; a second doped region located on a second side of the conductive channel; and the lightly doped region is positioned between the first doped region and the conductive channel and between the second doped region and the conductive channel, and the concentration of doped ions in the lightly doped region is changed along with the change of the depth of the conductive channel. According to the method, the processing technology is improved, the lightly doped region with gradually changed ion concentration is formed, and meanwhile, the length of the conductive channel is increased along with the increase of the depth of the conductive channel, so that the risk of junction breakdown of a semiconductor device is reduced, the hot carrier effect is inhibited, and the leakage current is reduced.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
After a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device in an integrated circuit works for a period of time, the electrical properties of the device gradually change.
At present, the channel size of semiconductor devices has entered the nanometer-micrometer age, and the short channel effect is particularly serious during the operation of the devices. The short channel effect is further aggravated by a Drain Induced Barrier Lowering (DIBL) effect generated under the high Drain bias effect, which causes a large drop in threshold voltage. Because the energy position distribution space of the nanometer device at the PN junction is shortened, the influence of the leakage current of the short channel effect and the hot carrier injection effect on the device characteristics is further deepened.
Therefore, the prior art solution will greatly reduce the threshold voltage due to the short channel effect and the hot carrier injection effect, and the leakage current generated by the hot carrier injection effect will have an adverse effect on the lifetime and stability of the device, and there is a need for improvement.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a semiconductor device and a method for manufacturing the same, which are used to overcome, at least to a certain extent, the problems of the related art that the threshold voltage is greatly reduced due to the short channel effect and the hot carrier injection effect, and the leakage current generated by the hot carrier injection effect adversely affects the lifetime and stability of the device.
According to an aspect of the present disclosure, there is provided a semiconductor device including:
a semiconductor substrate comprising a conductive channel;
a first doped region located on a first side of the conductive channel;
a second doped region located on a second side of the conductive channel;
and the lightly doped region is positioned between the first doped region and the conductive channel and between the second doped region and the conductive channel, and the concentration of doped ions in the lightly doped region is changed along with the change of the depth of the conductive channel.
In an exemplary embodiment of the present disclosure, the length of the conductive channel increases as the depth of the conductive channel increases.
In an exemplary embodiment of the present disclosure, the concentration of dopant ions in the first lightly doped region and the second lightly doped region decreases as the depth of the conductive channel increases.
In an exemplary embodiment of the present disclosure, further comprising:
a gate structure located over the conductive channel;
the spacing layer is coated on the side wall of the grid structure and consists of at least 2 layers of spacing side walls;
wherein a boundary of the lightly doped region and the conductive channel is defined by a thickness of the spacer sidewall.
In an exemplary embodiment of the present disclosure, the lightly doped region is formed by performing ion implantation of different concentrations for a plurality of times.
According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including:
providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate, and forming a conductive channel in the semiconductor substrate below the gate structure;
forming a first interval side wall on the side wall of the surface of the grid structure, and defining a first-time lightly doped ion implantation area through the first interval side wall;
carrying out first ion implantation according to the first lightly doped ion implantation region;
forming a second interval side wall on the surface of the first interval side wall, and defining a second lightly doped ion implantation area through the second interval side wall;
performing second ion implantation according to the second lightly doped ion implantation region;
the first ion implantation area and the second ion implantation area form a lightly doped area;
and respectively forming a first doping area and a second doping area on two sides of the conductive channel, wherein the lightly doped area is positioned between the first doping area and the conductive channel and between the second doping area and the conductive channel.
In one exemplary embodiment of the present disclosure, at least 2 spacer sidewall formations and 2 ion implantations are performed.
In an exemplary embodiment of the present disclosure, the second ion implantation concentration is less than the first ion implantation concentration, and the second ion implantation depth is greater than the first ion implantation depth.
In an exemplary embodiment of the present disclosure, in the multiple ion implantations, the concentration of the ions implanted at the next time is less than the concentration of the ions implanted at the previous time, and the depth of the ions implanted at the next time is greater than the depth of the ions implanted at the previous time.
In an exemplary embodiment of the present disclosure, further comprising: halo ion implantation is performed prior to the first ion implantation.
The semiconductor device and the manufacturing method thereof provided by the embodiment of the disclosure form the lightly doped region with modulation concentration by controlling the doping concentration of the lightly doped region between the conductive channel and the source/drain electrode region, so that the length of the conductive channel is increased along with the increase of the depth of the conductive channel, thereby effectively increasing the distance between the source/drain regions at two ends below the silicon surface channel, reducing the maximum electric field strength when the drain and the silicon substrate are reversely biased, improving the short channel effect and the hot carrier injection effect of the MOSFET, reducing the leakage current, increasing the breakdown voltage, and improving the reliability of the semiconductor device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic view of a structure of a conventional semiconductor device having an LDD in the related art.
FIG. 2 is a schematic diagram illustrating a leakage current path under the effect of hot carrier injection in the related art.
FIG. 3 is a diagram illustrating a tunneling breakdown current path in the related art.
Fig. 4 is a schematic diagram of a semiconductor device in an embodiment of the disclosure.
Fig. 5 is a flow chart of a method of fabricating a semiconductor device in an embodiment of the disclosure.
Fig. 6 is a flow chart illustrating an implementation of a method for fabricating a semiconductor device according to an embodiment of the present disclosure.
Fig. 7 is a schematic cross-sectional view illustrating the step S601 completed in one embodiment of the disclosure.
Fig. 8 is a schematic cross-sectional view of step S602 after completion in an embodiment of the disclosure.
Fig. 9 is a schematic cross-sectional view of the completed step S603 in one embodiment of the present disclosure.
Fig. 10 is a schematic cross-sectional view illustrating the completion of step S604 in an embodiment of the disclosure.
Fig. 11 is a schematic cross-sectional view of step S605 after completion in an embodiment of the disclosure.
Fig. 12 is a schematic cross-sectional view illustrating the step S606 after being completed according to an embodiment of the disclosure.
Fig. 13 is a schematic cross-sectional view illustrating the completion of step S607 according to an embodiment of the disclosure.
Fig. 14 is a schematic cross-sectional view illustrating the completion of step S608 in an embodiment of the disclosure.
Fig. 15 is a schematic cross-sectional view of step S609 after completion in one embodiment of the present disclosure.
Fig. 16 is a schematic cross-sectional view illustrating the completion of step S610 according to an embodiment of the disclosure.
Fig. 17 is a schematic cross-sectional view of step S611 after completion in an embodiment of the present disclosure.
Fig. 18 is a schematic cross-sectional view illustrating the completion of step S612 according to an embodiment of the disclosure.
Fig. 19 is a schematic cross-sectional view illustrating the completion of step S613 according to an embodiment of the disclosure.
Fig. 20 is a schematic cross-sectional view illustrating the completion of step S614 in one embodiment of the disclosure.
Fig. 21 is a schematic cross-sectional view of the completed step S615 in an embodiment of the disclosure.
Fig. 22 is a schematic cross-sectional view illustrating the completion of step S616 in one embodiment of the disclosure.
Fig. 23 is a schematic cross-sectional view after step S617 is completed in one embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
In the related embodiment of the present disclosure, as the gate width is continuously reduced, the channel length under the gate structure is also continuously reduced, and in order to effectively prevent the short channel effect, a Lightly Doped Drain (LDD) is introduced in the integrated circuit manufacturing process.
Fig. 1 is a schematic structural diagram of a conventional semiconductor device with LDD, and as shown in fig. 1, a semiconductor device 100 includes a substrate 101, a well 102, a source doped region 103, a drain doped region 104, a lightly doped drain region 105 disposed near the source doped region 103 and the drain doped region 104, a gate structure composed of a gate oxide layer 106 and a gate electrode 107, and a spacer layer 108 covering the upper and side walls of the gate structure, where the substrate 101 may be a Si substrate, and the gate oxide layer 106 may be silicon dioxide SiO 2.
FIG. 2 is a schematic diagram of a current leakage path under hot carrier injection effect, as shown in FIG. 2, taking NMOS as an example, wherein N represents electrons, P represents holes, S represents source, D represents drain, G represents gate, and source is grounded due to voltage V at drain DDGreater than the source D voltage VS. When the electric field near the maximum electric field of PN junction reverse bias is high enough, the electrons have enough energy to reach the interface of substrate Si and gate oxide SiO2 and be injected into SiO2, which causes the deterioration of threshold voltage, leakage current and operation life of the device, however, with the reduction of the channel size of the semiconductor device, the short channel effect and the influence of hot carrier injection effect on the device characteristics are more deepened due to the shortening of the distribution space of PN junction energy bits.
Fig. 3 is a schematic diagram of a tunneling Breakdown current path, and as shown in fig. 3, a Breakdown current flowing from the source to the drain is generated at the boundary of the depletion region, and as the size of the device channel is reduced, the tunneling Breakdown (Punch-Through Breakdown) voltage is more easily reduced.
In order to reduce the series resistance of the device during conduction and improve the capability of driving current, high-concentration ion implantation is required in a source/drain region in the front-end process of the semiconductor device. Despite the LDD structure, after the high concentration ion implantation of the source/drain region, after the subsequent high temperature annealing, the high doped element of the source/drain region tends to laterally diffuse into the channel region, so that the distance between the source and drain regions at two ends below the silicon surface channel is shortened (as shown in fig. 1), which causes the instability of the operation process of the device due to the short channel effect of the threshold voltage, increases the maximum electric field strength when the drain and the silicon substrate are reversely biased, causes the severe hot carrier effect, and causes the increase of the leakage current and the decrease of the tunneling voltage.
Based on the above, how to design the LDD optimization to effectively suppress the large reduction of the threshold voltage, reduce the leakage current, and increase the breakdown voltage caused by the short channel and hot carrier injection effects is of great significance to the improvement of the performance of the semiconductor device.
The present disclosure provides a lightly doped drain region with a modulated concentration without increasing the number of masks to suppress the increase of process cost, so as to effectively increase the distance between the source/drain regions at two ends under the silicon surface channel, reduce the maximum electric field strength when the drain and the silicon substrate are reversely biased, thereby improving the short channel effect of the MOSFET, the hot carrier injection effect, the leakage current and the breakdown voltage.
The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 4 is a schematic diagram of a semiconductor device in an embodiment of the disclosure.
As shown in fig. 4, the present disclosure provides a semiconductor device including: the semiconductor device comprises a semiconductor substrate 401, wherein the semiconductor substrate 401 comprises a first doped region 403, a second doped region 404, a lightly doped region and a conductive channel, the first doped region 403 is located at a first side of the conductive channel, and the second doped region 404 is located at a second side of the conductive channel. A lightly doped region is located between the first doped region 403 and the conductive channel and between the second doped region 404 and the conductive channel, and the concentration and distribution area of the doped ions in the lightly doped region vary with the depth of the conductive channel.
As shown in fig. 4, the lightly doped region in this embodiment includes a first lightly doped region 405 and a second lightly doped region 406, the first lightly doped region 405 is located between the first doped region 403 and the conductive channel; a second lightly doped region 406 is located between the second doped region 404 and the conductive channel.
Based on the semiconductor device provided by the embodiment of the disclosure, the doping concentration and the distribution area of the lightly doped region between the conductive channel and the source/drain electrode region are controlled to form the lightly doped region with modulation concentration, and meanwhile, the length of the conductive channel is increased along with the increase of the depth of the conductive channel, so that the distance between the source/drain regions at two ends below the silicon surface channel can be effectively increased, the maximum electric field intensity when the drain and the silicon substrate are reversely biased is reduced, and the short channel effect and the hot carrier injection effect of the MOSFET (metal oxide semiconductor field effect transistor) are improved, the leakage current is reduced, and the breakdown voltage is increased.
Taking the semiconductor device shown in fig. 4 as an example, in the semiconductor device, a conductive channel and a doped region may be specifically located in a well 402 formed by doping a semiconductor substrate 401, and a concentration of doping ions in a lightly doped region varies with the conductive channel, while a length of the conductive channel increases with an increase in depth of the conductive channel.
In an exemplary embodiment of the present disclosure, the concentration of the dopant ions in the lightly doped region varies with the conductive channel specifically as follows: the concentration of doping ions in the lightly doped region decreases with increasing depth of the conductive channel, and the length of the conductive channel increases with increasing depth of the conductive channel.
In an exemplary embodiment of the present disclosure, since the lightly doped region includes a first lightly doped region 405 and a second lightly doped region 406, a concentration of doping ions in the first lightly doped region 405 and the second lightly doped region 406 decreases as a depth of the conductive channel increases, and a length of the conductive channel increases as the depth increases. As shown in fig. 4, the boundary of the first lightly doped region 405 located at a first side (left side as viewed in fig. 4) of the conductive channel and the conductive channel is gradually inclined in a direction away from the conductive channel along the increase of the depth of the conductive channel, and conversely, the boundary of the second lightly doped region 406 located at a second side (right side as viewed in fig. 4) of the conductive channel and the conductive channel is gradually inclined in a direction away from the conductive channel along the increase of the depth of the conductive channel.
In an exemplary embodiment of the present disclosure, a boundary of the lightly doped region farthest from the first doped region and/or the second doped region is defined by a position of the spacer layer adjacent to the spacer layer on the sidewall of the gate structure, and a boundary of the lightly doped region nearest to the first doped region and/or the second doped region is defined by a position of the spacer layer away from the spacer layer on the sidewall of the gate structure.
In an exemplary embodiment of the present disclosure, as shown in fig. 4, in addition to the above structure, the semiconductor device further includes: a gate oxide layer 407, a gate electrode 410 and a gate protection layer 415, wherein the gate structure is located above the conductive channel, and the gate oxide layer 407 is formed on the surface of the semiconductor substrate 401.
In addition, the semiconductor device further includes: and the spacer layer covers the side wall of the gate structure, wherein the spacer layer is composed of at least 2 layers of spacer side walls. Specifically, the spacers include a first spacer 408 on a surface of a first sidewall (e.g., the left sidewall in fig. 4) of the gate structure and a second spacer 409 on a surface of a second sidewall (e.g., the right sidewall in fig. 4) of the gate structure. In an exemplary embodiment, the first spacer layer 408 and the second spacer layer 409 are comprised of at least 2 spacer sidewalls. In particular, the composition of the spacer sidewalls may be the same or different or partially different. In an example embodiment, the spacer sidewalls are comprised of a first spacer sidewall and a second spacer sidewall, the first spacer sidewall being silicon nitride and the second spacer sidewall being silicon oxide. In another example embodiment, the spacer sidewalls are both silicon nitride or silicon oxide. The thickness of the interval side walls is the same or different or partially different, in an example embodiment, the thickness of the interval side walls is the same and is 2nm, the distribution of the lightly doped regions formed by the interval side walls and the boundary of the conductive channel are linearly changed, and the length of the conductive channel is linearly increased along with the change of the depth. In another exemplary embodiment, the thicknesses of the spacer sidewalls are different or partially different, taking a first spacer sidewall and a second spacer sidewall as an example, the thickness of the first spacer sidewall is 2nm, the thickness of the second spacer sidewall is 3nm, the distribution of the lightly doped region formed by using the spacer sidewalls and the boundary of the conductive channel are nonlinearly changed, and the length of the conductive channel monotonically increases with the change of the depth.
In an exemplary embodiment of the present disclosure, the first doped region 403 may be a source region 403, and the second doped region 404 may be a drain region 404, and thus a source 412 formed corresponding to the source region 403 and a drain 411 formed corresponding to the drain region 404 are further included on the semiconductor substrate 401. In addition, a gate contact 413 is further formed on the gate electrode 410, and the gate contact 413 and the source 412 and the drain 411 may be formed as metal electrodes at different positions respectively by performing the same metal etching.
It is further noted that ohmic contact regions 414 are formed between the source 412 and source regions 403, between the drain 411 and drain region 404, and between the gate electrode 410 and the gate contact 413. In which only one ohmic contact region, i.e. the ohmic contact region corresponding to the drain region 404, is marked in fig. 4, while in practice an ohmic contact region is present both above the corresponding source region 403 and above the gate electrode 410. The ohmic contact means that the resistance value of a contact surface when metal is in contact with a semiconductor is far smaller than the resistance of the semiconductor, so that most of voltage is dropped in an active region but not on the contact surface when a semiconductor device is operated, and the main measure for realizing the ohmic contact is to perform high doping on a semiconductor surface layer or introduce a large number of recombination centers.
In an exemplary embodiment of the present disclosure, the lightly doped regions (the first lightly doped region and the second lightly doped region) are formed by performing a plurality of times of ion implantation with different concentrations. The concentration and energy of the ion implantation performed for multiple times are also different, wherein the ion concentration is the largest in the first ion implantation, and the energy of the ion implantation is the smallest, so that the doping concentration formed in the lightly doped region by the first ion implantation is determined to be the largest, and the doping depth is the shallowest, that is, the closest to the surface of the semiconductor substrate 401. Then, the ion concentration is gradually reduced and the ion implantation energy is increased each time of ion implantation, that is, the doped ion concentration is higher at a position closer to the surface of the semiconductor substrate 401 and is lower at a position farther from the surface of the semiconductor substrate 401, thereby forming a lightly doped region in which the ion concentration is gradually changed. In an exemplary embodiment, the first ion implantation has an ion energy of 1KeV and a concentration of 5E14 per square centimeter, and the second ion implantation has an ion energy of 6KeV and a concentration of 5E13 per square centimeter. In another exemplary embodiment, the ion energies and concentrations may also be set in a proportional relationship, the ion energy of the first ion implantation is 1KeV, and the concentration is 5E14 per square centimeter, the ion energy of the second ion implantation is 1.5 times the ion energy of the first ion implantation, i.e., 1.5KeV, the ion implantation concentration of the second ion implantation is 0.8 times the ion energy of the first ion implantation, i.e., 4E14 per square centimeter, and so on, the ion implantation energy and concentration of the third ion implantation, the ion implantation energy and concentration of the fourth ion implantation, and the ion implantation energy and concentration of the fifth ion implantation are … …, thereby forming the linearly modulated lightly doped region. When ion implantation is performed a plurality of times, the ion implantation is of the same kind or different kinds or partially different kinds. In an exemplary embodiment, the P-type ion implants are all phosphorous ions. In another exemplary embodiment, the P-type ion implantation is phosphorous ion and arsenic ion, and specifically, taking three ion implantations as an example, the first ion implantation is phosphorous ion, the second ion implantation is arsenic ion, and the third ion implantation is phosphorous ion.
It should be noted that, in use, the gate of the semiconductor device is connected to a scanning signal line so as to input a gate voltage Vg to the gate of the MOS field effect transistor. The drain is connected to the data line so as to input the data voltage Vd to the drain of the MOS field effect transistor.
In summary, in the semiconductor device provided in the embodiment of the present disclosure, due to the LDD region for modulating the ion concentration distribution, the lateral length of the conductive channel in the silicon substrate (semiconductor substrate 401) is gradually increased from the silicon surface to the inside of the silicon substrate to avoid the short channel effect, and at the same time, the tunneling breakdown is avoided, or the tunneling breakdown voltage is raised.
For the above semiconductor device, taking an NMOS transistor As an example, the semiconductor substrate 401 may be an N-type substrate, a P well 402 formed by doping P-type ions (for example, + 3-valent ions such As boron B) is disposed on the N-type substrate 401, and the types of ions doped in the first doping region 403, the second doping region 404, the first lightly doped region 405, and the second lightly doped region 406 are also N-type ions, for example, + 5-valent ions such As phosphorus P or arsenic As. Similarly, if the PMOS transistor is used, the type of the doped ions needs to be adjusted accordingly, and the details are not repeated here.
Fig. 5 is a flowchart of a method for fabricating a semiconductor device in an embodiment of the disclosure, including the steps of:
as shown in fig. 5, in step S501, a semiconductor substrate is provided. Specifically, the semiconductor substrate is one of a silicon substrate, gallium nitride, gallium arsenide and a silicon-on-insulator substrate, and the semiconductor substrate may be a P-type substrate or an N-type substrate directly, or may be a P-well formed on the N-type substrate or an N-well formed on the P-type substrate.
As shown in fig. 5, in step S502, a gate structure is formed on the semiconductor substrate, and a conductive channel is formed in the semiconductor substrate under the gate structure.
As shown in fig. 5, in step S503, a first spacer sidewall is formed on the sidewall of the gate structure, and a first lightly doped ion implantation region is defined through the first spacer sidewall.
As shown in fig. 5, in step S504, a first ion implantation is performed according to the first lightly doped ion implantation region.
As shown in fig. 5, in step S505, a second spacer sidewall is formed on the surface of the first spacer sidewall, and a second lightly doped ion implantation region is defined through the second spacer sidewall, wherein the second lightly doped ion implantation region is smaller than the first lightly doped ion implantation region.
As shown in fig. 5, in step S506, a second ion implantation is performed according to the second lightly doped ion implantation region.
As shown in fig. 5, in step S507, the first ion implantation region and the second ion implantation region constitute a lightly doped region.
As shown in fig. 5, in step S508, a first doped region and a second doped region are respectively formed at two sides of the conductive channel, and the lightly doped region is located between the first doped region and the conductive channel and between the second doped region and the conductive channel.
It should be noted that, in this example, at least 2 times of forming the spacer sidewalls and 2 times of ion implantation are required, that is, the step S505 of patterning process is repeated multiple times to form the spacer sidewalls and the step S506 of ion implantation process is repeated multiple times. In particular, the composition of the spacer sidewalls may be the same or different or partially different. In an example embodiment, the spacer sidewalls are comprised of a first spacer sidewall and a second spacer sidewall, the first spacer sidewall being silicon nitride and the second spacer sidewall being silicon oxide. In another example embodiment, the spacer sidewalls are both silicon nitride or silicon oxide. The thickness of the interval side walls is the same or different or partially different, in an example embodiment, the thickness of the interval side walls is the same and is 2nm, the distribution of the lightly doped regions formed by the interval side walls and the boundary of the conductive channel are in linear distribution, and the length of the conductive channel is increased linearly along with the change of the depth. In another exemplary embodiment, the thicknesses of the spacer sidewalls are different or partially different, taking a first spacer sidewall and a second spacer sidewall as an example, the thickness of the first spacer sidewall is 2nm, the thickness of the second spacer sidewall is 3nm, the distribution of the lightly doped region formed by using the spacer sidewalls and the boundary of the conductive channel are nonlinearly changed, and the length of the conductive channel monotonically increases with the change of the depth.
In an exemplary embodiment of the present disclosure, the energy of the second ion implantation is greater than the energy of the first ion implantation, so that the depth of the implanted ions in the lightly doped region is gradually deepened. The concentration of the second ion implantation is less than that of the first ion implantation, so that the concentration of the implanted ions in the lightly doped region is gradually reduced along with the increase of the depth. In the ion implantation for at least more than 2 times, the ion implantation concentration of the next time is less than that of the previous time, and the ion implantation depth of the next time is greater than that of the previous time. In an exemplary embodiment, the first ion implantation has an ion energy of 1KeV and a concentration of 5E14 per square centimeter, and the second ion implantation has an ion energy of 6KeV and a concentration of 5E13 per square centimeter. In another exemplary embodiment, the ion energies and concentrations may also be set in a proportional relationship, the ion energy of the first ion implantation is 1KeV, and the concentration is 5E14 per square centimeter, the ion energy of the second ion implantation is 1.5 times the ion energy of the first ion implantation, i.e., 1.5KeV, the ion implantation concentration of the second ion implantation is 0.8 times the ion energy of the first ion implantation, i.e., 4E14 per square centimeter, and so on, the ion implantation energy and concentration of the third ion implantation, the ion implantation energy and concentration of the fourth ion implantation, and the ion implantation energy and concentration of the fifth ion implantation are … …, thereby forming the linearly modulated lightly doped region. When ion implantation is performed a plurality of times, the ion implantation is of the same kind or different kinds or partially different kinds. In an exemplary embodiment, the P-type ion implants are all phosphorous ions. In another exemplary embodiment, the P-type ion implantation is phosphorous ion and arsenic ion, and specifically, taking three ion implantations as an example, the first ion implantation is phosphorous ion, the second ion implantation is arsenic ion, and the third ion implantation is phosphorous ion.
In an exemplary embodiment of the present disclosure, before the first ion implantation, the method further includes: halo ion implantation is performed.
Fig. 6 below describes a method for manufacturing the semiconductor device, which includes the following steps:
step S601, depositing an oxide on the semiconductor substrate. Fig. 7 shows a schematic cross-sectional view after step S601 is completed, i.e., an oxide 702 is formed on the semiconductor substrate 701. The type of the semiconductor substrate 701 may be N-type or P-type, and in this embodiment, an NMOS transistor is taken as an example, which may be an N-type semiconductor substrate.
In step S602, well region ion implantation is performed to form a well 703 in a region of a certain depth above the semiconductor substrate 701. Fig. 8 shows a schematic cross-sectional view after step S602 is completed, i.e., a well 703 is formed in a semiconductor substrate 701. Still taking the NMOS transistor as an example, a P-well is formed on the N-type semiconductor substrate by ion implantation, whereas if the NMOS transistor is a PMOS transistor, the N-well is formed on the P-type semiconductor substrate by ion implantation.
In step S603, the threshold voltage is adjusted by ion implantation. Fig. 9 shows a schematic cross-sectional view after step S603 is completed. In this embodiment, impurity ions such as boron ions (causing positive shift of threshold voltage) or phosphorus ions (causing negative shift of threshold voltage) are implanted at the surface of the semiconductor substrate, and the impurity concentration at the surface of the semiconductor substrate is adjusted by precisely controlling the energy and concentration of the implanted ions, so as to achieve the purpose of adjusting the threshold voltage.
Step S604, annealing and removing the oxide. Fig. 10 shows a schematic cross-sectional view after step S604 is completed. Annealing is carried out after ion implantation, the implanted silicon wafer can be heated, a protective film is generated by oxidation, the crystal lattice damage is repaired, ion redistribution can be realized, the impurity concentration difference is reduced, impurity atoms are moved to crystal lattice points, and the implanted impurities are activated. After annealing, the oxide 702 also needs to be removed, for example, the oxide can be removed by dry etching.
In step S605, a gate oxide layer is formed. Fig. 11 shows a cross-sectional view after step S605 is completed, and a gate oxide layer 704 is formed on the well 703.
Step S606, a gate material is formed, wherein the gate material may be polysilicon and formed by ion implantation. Fig. 12 is a schematic cross-sectional view of the completed step S606, in which a polysilicon material is deposited on the gate oxide layer 704, and then ion implantation is performed, if the NMOS transistor is used, the ion implantation type in this step is N-type ions such as phosphorus; if the transistor is a PMOS transistor, the ion type of the ion implantation in the step is P-type ions such as boron.
Step S607, annealing the ion implanted polysilicon gate material. Fig. 13 is a schematic cross-sectional view of the completed step S607, in which annealing is performed in the same manner as the annealing in step S604, a protective film is formed by oxidation, lattice damage is repaired, ion redistribution can be realized, an impurity concentration difference is reduced, impurity atoms are moved to lattice points, and implantation of impurities is activated, so that a gate electrode 705 is formed on the gate oxide layer 704. In addition, a protective layer 706 is further deposited over the gate electrode 705 after annealing.
In step S608, an active region channel is defined by an etching process. Fig. 14 shows a schematic cross-sectional view after step S608 is completed, and a portion of the gate oxide layer 704, the gate electrode 705 and the protection layer 706 are left after the etching process. The starting process in this embodiment may be implemented by selecting a wet etching method or a dry etching method as needed, and details are not described here.
In step S609, a first spacer layer is deposited and etched to define a first LDD ion implantation region. Fig. 15 is a schematic cross-sectional view after step S609 is completed, a SiN/SiO deposition is performed on the structure shown in fig. 14 to form a first spacer sidewall layer (the first spacer sidewall layer and a second spacer sidewall layer formed in a later step are both indicated by 707), and then an etching process is performed to etch away an excess portion, so that only a portion covering the sidewalls of the gate oxide layer 704, the gate electrode 705 and the protection layer 706 is remained, i.e., a first LDD ion implantation region is defined, as shown in fig. 15.
In step S610, Halo implant (Halo implant) is performed. Fig. 16 shows a cross-sectional view after step S610 is completed, and as shown in fig. 16, halo ion implantation is performed on the defined first LDD ion implantation region, so that a halo region is formed at a position of the conductive channel region close to the doped region. The ion type of the implanted halo region is opposite to that of the lightly doped region, the ion energy of the implanted halo region is larger than that of the lightly doped region, the ion concentration of the implanted halo region is smaller than that of the lightly doped region, the HCI effect is improved through halo ion implantation, the tunneling breakdown effect is avoided, and the step can be selectively added in the whole manufacturing process according to needs. Taking NMOS fabrication as an example, the ion type implanted into the lightly doped region is N type, the ion type implanted into the halo region is P type, the ion energy implanted into the halo region in this embodiment is 10-60 KeV, and the concentration is 5E 12-5E 13 per square centimeter.
In step S611, a first LDD ion implantation is performed. Fig. 17 is a schematic cross-sectional view of the completed step S611, in which the first ion implantation has the highest concentration, the lowest energy, and the shallowest depth, and is close to the surface of the silicon substrate. The first implant into the lightly doped region in this embodiment has an ion energy of 1KeV and a concentration of 5E14 per square centimeter.
In step S612, a second spacer layer is deposited and etched to define a second LDD ion implantation region. Fig. 18 shows a schematic cross-sectional view after step S612 is completed, and the principle and the processing procedure are the same as those of step S609, which is not described herein again. As shown in fig. 18, this step is continued on the basis of the above-described step, and the second spacer sidewall is formed on the surface of the first spacer sidewall (the first spacer sidewall and the second spacer sidewall are formed only in divided portions, and the material and the deposition manner thereof are the same, and thus both are indicated by 707).
In step S613, a second LDD ion implantation is performed. Fig. 19 is a schematic cross-sectional view of the completed step S613, in which the second ion implantation has a concentration lower than that of the previous ion implantation and has a higher energy than that of the first ion implantation, so that the depth of the ion implantation is deeper than that of the previous ion implantation and is further from the surface of the silicon substrate. And then, by analogy, completing the deposition etching of the spacer layer and the LDD ion implantation for N times. The ion energy of the second implantation into the lightly doped region in this embodiment is 2KeV and the concentration is 3E14 per square centimeter.
In step S614, the last LDD ion implantation is performed. Fig. 20 shows a cross-sectional view after step S614 is completed, in which the concentration of the last ion implantation is the minimum, the energy is the maximum, and the depth of the ion implantation is the deepest, so as to complete the LDD doping implantation process. The ion energy of the last implantation into the lightly doped region in this embodiment is 6KeV, and the concentration is 5E13 per square centimeter.
In step S615, a source/drain region is defined by depositing and etching a source/drain sidewall (Side Wall) dielectric layer. Fig. 21 shows a cross-sectional view after step S615 is completed, i.e., the dielectric layer (the first spacer sidewall layer and the second spacer sidewall layer 707) is formed to define the source and drain regions on both sides of the well 703.
In step S616, source/drain region ion implantation is performed. Fig. 22 shows a schematic cross-sectional view after step S616 is completed, and two regions 708 'and 709' are formed in the well, respectively.
In step S617, annealing is performed. Fig. 23 shows a cross-sectional view after step S617 is completed, in which the annealing synchronization step S604 and the annealing synchronization step S607 are performed by the same annealing principle and process, and a source region 708 and a drain region 709 are formed in the well, and a lightly doped region 710 is formed between the source region 708 and the conductive channel and between the drain region 709 and the conductive channel, respectively. The doped region 710 is formed by a first ion implantation region and a second ion implantation region.
The step is followed by etching through a mask to define an electrode contact window region (i.e., an ohmic contact region), and performing ion implantation and annealing to reduce contact resistance. For example, three ohmic contact regions are formed in the windows corresponding to the gate structures and the windows corresponding to the source and drain regions, respectively. Then, metal electrode deposition and etching are performed to complete the MOSFET device, and finally the device as shown in fig. 4 is obtained, and by etching the deposited metal layer, a gate contact can be formed on the gate structure, a source electrode can be formed on the source region, and a drain electrode can be formed on the drain region.
Based on the steps S601 to S617, it can be seen from the cross-sectional views shown in fig. 7 to fig. 23 that, after the halo ion implantation is completed, the LDD doping element ion implantation and the spacer deposition etching process are performed repeatedly, wherein the implantation concentration of the doping ions decreases sequentially with the increase of the implantation times, and the implantation energy increases sequentially with the implantation times, so as to complete the LDD regions with decreasing concentration distribution.
In summary, by using the method for manufacturing a semiconductor device provided in this embodiment, since the LDD region and the ion concentration decrease with the increase of the depth of the conductive channel, the lateral length of the conductive channel in the silicon substrate will gradually increase from the silicon surface to the inside of the silicon substrate to avoid the short channel effect, and at the same time, tunnel breakdown can be avoided, or tunnel breakdown voltage can be raised.
As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or program product. Thus, various aspects of the invention may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.
Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (10)

1. A semiconductor device, comprising:
a semiconductor substrate comprising a conductive channel;
a first doped region located on a first side of the conductive channel;
a second doped region located on a second side of the conductive channel;
and the lightly doped region is positioned between the first doped region and the conductive channel and between the second doped region and the conductive channel, and the concentration and distribution area of doped ions in the lightly doped region are changed along with the change of the depth of the conductive channel.
2. The semiconductor device of claim 1, wherein a length of the conductive channel increases as a depth of the conductive channel increases.
3. The semiconductor device of claim 1, wherein a concentration of dopant ions in the first lightly doped region and the second lightly doped region decreases as a depth of the conductive channel increases.
4. The semiconductor device according to claim 1, further comprising:
a gate structure located over the conductive channel;
the spacing layer is coated on the side wall of the grid structure and consists of at least 2 layers of spacing side walls;
wherein a boundary of the lightly doped region and the conductive channel is defined by a thickness of the spacer sidewall.
5. The semiconductor device of claim 4, wherein the lightly doped region is formed by performing a plurality of ion implantations of different concentrations.
6. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate, and forming a conductive channel in the semiconductor substrate below the gate structure;
forming a first interval side wall on the side wall of the surface of the grid structure, and defining a first-time lightly doped ion implantation area through the first interval side wall;
carrying out first ion implantation according to the first lightly doped ion implantation region;
forming a second interval side wall on the surface of the first interval side wall, and defining a second lightly doped ion implantation area through the second interval side wall;
performing second ion implantation according to the second lightly doped ion implantation region;
the first ion implantation area and the second ion implantation area form a lightly doped area;
and respectively forming a first doping area and a second doping area on two sides of the conductive channel, wherein the lightly doped area is positioned between the first doping area and the conductive channel and between the second doping area and the conductive channel.
7. The method of claim 6, wherein at least 2 spacer sidewall formations and 2 ion implantations are performed.
8. The method of manufacturing a semiconductor device according to claim 6, wherein the second ion implantation concentration is smaller than the first ion implantation concentration, and wherein the second ion implantation depth is greater than the first ion implantation depth.
9. The method of manufacturing a semiconductor device according to claim 7, wherein in the plurality of ion implantations, the concentration of ions implanted in the next time is smaller than that implanted in the previous time, and the depth of ion implantation in the next time is greater than that implanted in the previous time.
10. The method for manufacturing a semiconductor device according to claim 6, further comprising: halo ion implantation is performed prior to the first ion implantation.
CN201811278696.9A 2018-10-30 2018-10-30 Semiconductor device and method for manufacturing the same Pending CN111129107A (en)

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