CN211700293U

CN211700293U - Semiconductor device with a plurality of transistors

Info

Publication number: CN211700293U
Application number: CN201821565690.5U
Authority: CN
Inventors: 冯鹏; 陈面国
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-09-25
Filing date: 2018-09-25
Publication date: 2020-10-16
Anticipated expiration: 2028-09-25

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor substrate, wherein the semiconductor substrate comprises a conductive channel therein; and a gate structure located over the conductive channel; and a counter-doped region is arranged in the conductive channel corresponding to the gate structure, wherein the length of the counter-doped region is smaller than that of the conductive channel. According to the semiconductor device, the doping in the conducting channel of the semiconductor device is controlled to form an asymmetric structure, the width of the conducting channel on one side of the drain electrode can be widened, and the electric field on one side of the drain electrode is far away from the side surface of the drain electrode, so that the hot carrier injection phenomenon is reduced.

Description

Semiconductor device with a plurality of transistors

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device.

Background

After a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device in an integrated circuit works for a period of time, the electrical properties of the device gradually change.

With the reduction of the size of the semiconductor device, the supply voltage and the operating voltage of the semiconductor device are not reduced much, and the corresponding electric field strength is increased, so that the movement rate of electrons is increased. When the energy of the electrons is high enough, the electrons become hot carriers, leave the silicon substrate, tunnel into the gate oxide layer, and therefore the electrical performance of the transistor changes, including not only threshold voltage (Vt) drift, but also transconductance (Gm) reduction, saturation current (Idsat) reduction and the like, and finally the semiconductor device cannot work normally. This variation is due to the Hot Carrier Injection (HCI) effect in MOSFET devices. Therefore, there is a need to improve the hot carrier injection effect in MOSFET devices.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

An object of the present disclosure is to provide a semiconductor device for overcoming, at least to some extent, the problem of the semiconductor device not operating properly due to hot carriers resulting from the limitations and disadvantages of the related art.

According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor device including:

a semiconductor substrate, wherein the semiconductor substrate comprises a conductive channel therein; and

and the grid structure is positioned on the conductive channel, wherein a counter-state doped region is arranged in the conductive channel corresponding to the grid structure, and the length of the counter-state doped region is smaller than that of the conductive channel.

In an exemplary embodiment of the present disclosure, the semiconductor substrate further includes a first doped region and a second doped region located at two sides of the conductive channel, and the counter doped region is of the same type as the doped ions in the first doped region and/or the second doped region.

In an exemplary embodiment of the present disclosure, the semiconductor substrate further includes:

the first lightly doped region is positioned at one side close to the first doped region; and

and the second lightly doped region is positioned at one side close to the second doped region.

In an exemplary embodiment of the present disclosure, the counter-doped region is the same type of dopant ions as in the first lightly doped region and/or the second lightly doped region.

In an exemplary embodiment of the present disclosure, a ratio of a length of the counter-doped region to a length of the conductive channel is 0.5 to 0.8.

According to the semiconductor device provided by the embodiment of the disclosure, on one hand, the width of the conductive channel at one side of the drain electrode can be widened by controlling the doping in the conductive channel of the semiconductor device to form an asymmetric structure, so that the electric field at one side of the drain electrode is far away from the side surface of the drain electrode, thereby reducing the hot carrier injection phenomenon, reducing the HCI degree of electrons in the drain electrode-gate region (namely the region of the conductive channel close to the drain electrode), and improving the electrical performance of the semiconductor device.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic diagram of a semiconductor device in the related art.

Fig. 2 is a schematic diagram of a semiconductor device in an embodiment of the disclosure.

Fig. 3 shows a schematic diagram of an NMOS fet provided in an embodiment of the present disclosure.

Fig. 4 is a flow chart of a method of fabricating a semiconductor device in an embodiment of the disclosure.

FIG. 5 is a flow chart of the steps for fabricating an NMOS transistor.

Fig. 6 is a schematic diagram of performing step S502 to perform the first ion implantation.

Fig. 7 is a schematic diagram of performing step S503 to perform a second ion implantation.

Fig. 8 is a schematic cross-sectional view after step S504 is completed.

Fig. 9 is a schematic cross-sectional view after step S505 is completed.

Fig. 10 is a schematic cross-sectional view after step S506 is completed.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

Fig. 1 is a schematic diagram of a semiconductor device in the related art.

In a related embodiment of the present disclosure, as shown in fig. 1, taking an NMOS field effect transistor as an example for description, wherein a conductive channel adopts a symmetrical structure, the semiconductor device 100 includes a substrate 101, a P-well 102, two N-type regions (i.e., a first doped region 103 and a second doped region 104) formed by N-type ion doping, a conductive channel 105 formed between the two N-type regions, a gate oxide layer 106, a polysilicon gate layer 107 and a gate metal 108 generally covering the conductive channel 105, a source metal 109 formed corresponding to the first doped region 103, and a drain metal 110 formed corresponding to the second doped region 104. The P-well 102 is a P-type silicon substrate with a low doping concentration, and the first doping region 103 and the second doping region 104 are two N + regions with high doping concentrations.

The conductive channel 105 of FIG. 1 includes a P-type doped region 1051 doped with boron B ions (10-15 KeV energy, 2E 12-5.5E 12 per square centimeter). In addition, As shown in fig. 1, lightly doped

regions

1052 and 1053 are also provided in the portions of the conductive channel 105 adjacent to the two heavily doped N + regions, into which phosphorus P or arsenic As plasma is implanted. The polysilicon gate layer 107 is polysilicon formed by N-type ion doping, and the gate metal 108 is connected to a gate control line so as to input a gate voltage Vg to the gate of the MOS fet. The drain metal 110 is connected to a data line so as to input a data voltage Vd to the drain of the MOS field effect transistor.

As shown in fig. 1, the generation of hot carrier effect is mainly influenced by the electric field strength in the horizontal direction, where the electric field strength is the largest, i.e. where the conductive channel 105 is located near the drain, i.e. where a strong electric field region is formed in the drain-gate region. The generation of hot carrier effects is mainly influenced by the electric field strength in the horizontal direction, where the electric field strength is greatest, i.e. where the conducting channel is close to the drain, and HCI therefore usually occurs on the drain side.

The conventional solution to HCI may be to add a gate oxide or use a Light Doped Drain (LDD) technique. The addition of the gate oxide layer mainly improves the quality of gate oxide, and for example, the methods of reducing H and H2O at the Si — SiO2 interface, reducing plasma damage to the oxide layer in Reactive Ion Etching (RIE) process such as metal corrosion, and the like, or using silicon oxynitride to replace the original SiO2 as gate oxide, and the like, may be used. The LDD is a structure that a low-doped drain region is arranged in the channel close to the drain electrode, and the low-doped drain region also bears partial voltage, so that the hot electron degradation effect can be prevented.

The embodiment of the present disclosure provides a semiconductor device with an asymmetric structure, in which P-type ions in a P-type doped region 1051 in a conductive channel 105 in fig. 1 are changed into N-type ions in an inverted state, and an N-type ion implantation region is defined as a position near a drain end channel, and the following describes in detail an exemplary embodiment of the present disclosure with reference to the drawings.

As shown in fig. 2, the present disclosure provides a semiconductor device 200 including: the semiconductor device comprises a semiconductor substrate 201, wherein the semiconductor substrate 201 comprises a conductive channel 202, a first doped region 203 and a second doped region 204 which are positioned on two sides of the conductive channel, and a gate structure 208 which is positioned above the conductive channel 202.

A counter doped region 205 is disposed in the conductive channel 202 corresponding to the gate structure 208, and a length of the counter doped region 205 is smaller than a length of the conductive channel 202.

In an exemplary embodiment of the present disclosure, the counter-doped region 205 is the same type of doping ions as the first doped region and/or the second doped region.

In an exemplary embodiment of the present disclosure, the semiconductor substrate 201 further includes:

a first lightly doped region 206 located at a side close to the first doped region 203; and

and a second lightly doped region 207 located at a side close to the second doped region 204.

In an exemplary embodiment of the present disclosure, the counter-doped region 205 is the same type of doping ions as the first lightly doped region 206 and/or the second lightly doped region 207.

In an exemplary embodiment of the present disclosure, a ratio of the length of the counter-doped region 205 to the length of the conductive channel 202 is 0.5-0.8.

According to the semiconductor device provided by the embodiment of the disclosure, on one hand, the asymmetric structure is formed by controlling the doping in the conductive channel of the semiconductor device, the width of the conductive channel on one side of the drain electrode can be widened, and the electric field intensity on the side surface of the drain electrode is weakened, so that the hot carrier injection phenomenon is reduced. On the other hand, due to the reduction of the hot carrier injection phenomenon, the HCI degree of electrons in a drain-gate region (namely a region of a conductive channel close to a drain) is reduced, and the electrical performance of the semiconductor device is improved.

In some embodiments of the present disclosure, a structure of a semiconductor device of the present disclosure is described by taking an NMOS field effect transistor as an example, specifically as follows:

In an embodiment of the present disclosure, if the semiconductor substrate is an N-type substrate, a P-well needs to be formed by doping P-type ions, so as to form a conductive channel in the P-well, and the like to form an NMOS; if the substrate is a P-type substrate, a conductive channel can be directly formed on the P-type substrate to form an NMOS.

As shown in fig. 3, in the present embodiment, an N-type substrate 301 is used, and in the semiconductor device 300, a P well 302 formed by doping P-type ions (for example, + 3-valent ions such as boron B) is provided on the N-type substrate 301. The P-well 302 comprises a conductive channel 305, a first doped region 303 at a first side of the conductive channel 305 and a second doped region 304 at a second side of the conductive channel 305. The first doped region 303 and the second doped region 304 are both doped with N-type ions (such As phosphorus P or arsenic As) +5 valent ions, wherein the first doped region 303 may be a source doped region in the semiconductor device, and the second doped region 304 may be a drain doped region in the semiconductor device.

As shown in fig. 3, the conductive channel 305 includes an asymmetric structure formed by disposing a counter-doped region 306, and the counter-doped region 306 is disposed on a side of the conductive channel 305 close to the first doped region 303 or close to the second doped region 304. Taking the NMOS transistor shown in this embodiment as an example, the counter doped region 306 is disposed on a side close to the second doped region (i.e., the drain doped region) 304, and the counter doped region 306 is not disposed on a side of the conductive channel 305 close to the first doped region 303 (i.e., the source doped region) 303.

As shown in fig. 3, the conductive channel 305 further includes a first lightly doped region 307 and a second lightly doped region 308, the first lightly doped region 307 is located at a side close to the first doped region 303; a second lightly doped region 308 is located adjacent to a side of the second doped region 304. The first Lightly Doped region 307 and the second Lightly Doped region 308 are the same As the Lightly Doped region (e.g., Lightly Doped Drain, LDD) of the conventional NMOS transistor, wherein the Lightly Doped region and the N-type Doped region are the same type of ions, i.e., the type of ions Doped in the first Lightly Doped region 307 and the second Lightly Doped region 308 is also N-type ions, such As +5 valence ions, e.g., phosphorous P or arsenic As.

Based on the above, the counter-doped region 306, the first lightly doped region 307, and the second lightly doped region 308 are all formed in the P-well 302, but since the counter-doped region 306 is only disposed at one side (i.e., the second lightly doped region 308) close to the drain doped region 304, an asymmetric structure is formed in the conductive channel 305, and an anti-N + ion diffusion region is formed in the P-well of the NMOS transistor by an asymmetric ion implantation, so as to reduce the electric field strength at the drain side, and this asymmetric structure is simple and effective to reduce the HCI degree, and improve the electrical performance of the semiconductor device.

Taking this embodiment as an example, the counter doped region 306 is close to the second doped region 304, the type of the doped ions in the counter doped region 306 is N-type, wherein the type of the doped ions in the second doped region 304 is also N-type.

It should be noted that, although the types of ions doped in the counter-doped region 306 and the second doped region 304 (or the first doped region 303) are the same, they may be different elements, for example, the ions doped in the counter-doped region 306 are As (arsenic), and the ions doped in the first doped region 303 and the second doped region 304 are P (phosphorus).

In the present embodiment, the type of the doped ions in the counter-doped region 306 is N-type, and the types of the doped ions in the first doped region 303, the second doped region 304, the first lightly doped region 307 and the second lightly doped region 308 are all N-type, i.e., the type of the doped ions in the counter-doped region 306 is the same as that in the first doped region 303, the second doped region 304, the first lightly doped region 307 and the second lightly doped region 308, and is only different from that in the P-well 302.

In the present embodiment, the ratio of the length of the counter-doped region 306 to the overall length of the conductive channel 305 is in the range of 0.5 to 0.8, wherein preferably, the ratio of the length of the counter-doped region 306 to the overall length of the conductive channel 305 is in the range of 0.5 (i.e., the counter-doped region 306 occupies half of the conductive channel 305 near the second doped region 304). That is, the dopant doped with the inversion type ions occupies at least half of the region of the conductive channel near the second doped region 304, and the inversion doped region 306 of the inversion type is not disposed at the position of the channel near the source, i.e., an asymmetric structure is formed, so as to enlarge the width of the conductive channel at the drain side, reduce the electric field strength at the drain side, and reduce the occurrence of hot carrier injection.

As shown in fig. 3, a gate oxide layer 309, a polysilicon gate layer 310 and a gate metal 311 are also disposed over the conductive channel 305, as well as a source metal 312 disposed over the first doped region 303 and a drain metal 313 disposed over the second doped region 304. The polysilicon gate layer 310 is polysilicon formed by N-type ion doping, and the gate metal 311 is connected to a gate control line so as to input a gate voltage Vg to the gate of the MOS fet. The drain metal 313 is connected to a data line so as to input a data voltage Vd to the drain of the MOS field effect transistor.

It should be noted that, since the concentration of the ion implantation affects the length of the conductive channel, the concentration and the energy of the implanted ions need to be reasonably controlled during the process of forming the counter-state doped region (i.e., during the process of performing the counter-state N-type ion implantation) to form the asymmetric structure, and the specific manufacturing process refers to the description of the following embodiments.

In summary, in the semiconductor device with the asymmetric structure provided in the embodiments of the present disclosure, on one hand, the doping in the conductive channel of the semiconductor device is controlled to form the asymmetric structure in the conductive channel of the semiconductor device, so that the width of the conductive channel on the drain side can be widened, and the electric field strength on the drain side is reduced, thereby reducing the occurrence of hot carrier injection, reducing the HCI generation degree of electrons in the drain-gate region (i.e., the region of the conductive channel close to the drain), and improving the electrical performance of the semiconductor device.

Based on the above embodiments, if the semiconductor device is a PMOS transistor, the conducting channel and the asymmetric structure therein are formed in an N-well on an N-type substrate or a P-type substrate. In addition, the first doping region and the second doping region in the PMOS transistor are both P-type, the counter doping region disposed in the conductive channel and close to one of the first doping region and the second doping region is also P-type, the first lightly doped region and the second lightly doped region disposed in the conductive channel and close to both the first doping region and the second doping region are also P-type, and the ratio of the length of the counter doping region to the overall length of the conductive channel is also 0.5-0.8, so that the technical effects can be achieved even when an asymmetric structure is formed in an N-type substrate or an N-well, the structure and principle are similar to those of the above-mentioned embodiments, and are not repeated here.

Fig. 4 is a flowchart of a method for manufacturing a semiconductor device in an embodiment of the present disclosure, including the steps of:

as shown in fig. 4, in step S401, a semiconductor substrate is provided.

Specifically, a P-type substrate or an N-type substrate may be directly used in the semiconductor substrate, or a P-well formed on the N-type substrate or an N-well formed on the P-type substrate, and the conductive channel is located in the P-well or the N-well.

As shown in fig. 4, in step S402, a first ion implantation is performed on the semiconductor substrate to form an anti-doped region.

As shown in fig. 4, in step S403, a second ion implantation is performed on the semiconductor substrate having the counter-doped region to form a well.

Wherein the counter-doping in step S402 is to dope the ions with the opposite doping type to the doping type in the well formed in the subsequent step S403 by ion implantation, i.e. the ion implantation in the first time is opposite to the ion implantation in the second time.

In the following, a method for manufacturing a semiconductor device by taking an NMOS transistor as an example is still described, specifically as follows:

FIG. 5 is a flow chart of the steps for fabricating an NMOS transistor.

As shown in fig. 5, in step S501, a semiconductor substrate is provided.

Wherein the semiconductor substrate may be a P-type substrate, a P-type substrate 601 is provided in this step.

As shown in fig. 5, in step S502, a first ion implantation is performed on the semiconductor substrate to form a counter-doped region.

Fig. 6 is a schematic diagram of performing a first ion implantation in step S502, and As shown in fig. 6, the ion implantation is performed at a specific position (e.g., a specific position is defined by a photolithography process) in the P-type substrate 601, and since the ion implantation in this step is counter-doped, the type of the ion implanted at the specific position in the first ion implantation process should be N-type ions such As phosphorus P or arsenic As, which is opposite to the type of the ion implanted in the conventional NMOS transistor.

In this embodiment, the ion implantation is performed in this step not for the entire conductive channel, but for the side of the conductive channel near the doped drain region. The specific position is a predetermined position in the subsequently formed conductive channel, specifically, a position in the conductive channel near one side of the second doped region (i.e., the drain doped region).

In an exemplary embodiment of the present disclosure, the first ion implantation is performed at an energy of 30 to 35KeV and an ion concentration of 1.5E12 to 1.9E12 per square centimeter. And the ratio of the length of the counter-state doped region formed by the first ion implantation to the length of the conductive channel is 0.5-0.8, so that an asymmetric counter-state N-type structure is formed.

As an example, the first ion implantation to form the counter doped region further includes an annealing process, and the annealing process is used to repair damage to the semiconductor substrate and control diffusion of implanted ions.

For example, in this embodiment, the energy of the first ion implantation is 32KeV, and the ion concentration is 1.7E12 per square centimeter, so as to form the ratio of the length of the counter doped region to the length of the conductive channel to be 0.5, such that the length of the counter doped region is exactly half of the conductive channel, i.e. the specific position is half of the position of the conductive channel near the drain doped region.

It should be noted that, after the ion implantation process, the lattice of the crystal must be damaged by high temperature annealing to recover the integrity of the lattice, and the high temperature annealing causes further diffusion of the ions, so that the range of the ion implanted region is slightly smaller than the range of the desired counter-doped region, so that the abnormal-state doped region formed after the high temperature annealing just meets the requirement.

As shown in fig. 5, in step S503, a second ion implantation is performed on the semiconductor substrate having the counter-doped region to form a well.

Fig. 7 is a schematic diagram of performing step S503 to perform a second ion implantation, which is performed to form a P well 602 in the P-type substrate 601 in fig. 6, as shown in fig. 7.

In an exemplary embodiment of the present disclosure, the ion type of the second ion implantation is P-type ions, for example, +3 valent ions such as B ions. The energy of the second ion implantation is 130-160 KeV, and the ion concentration is 1.5E 13-3E 13 per square centimeter.

For example, in this embodiment, the energy of the second ion implantation may be selected to be 150KeV, and the ion concentration may be selected to be 2E13 per square centimeter.

As shown in fig. 5, in step S504, a gate structure is formed on the counter-doped region of the semiconductor substrate.

Specifically, a gate oxide layer and a polysilicon gate layer (i.e., a gate structure) are formed over the conductive channel.

Fig. 8 is a cross-sectional view of the conductive channel after step S504 is completed, and a gate oxide layer 608 and a polysilicon gate layer 609 are formed on the conductive channel by deposition and etching. In the step, polycrystalline silicon is formed on the conductive channel, specifically amorphous silicon is formed through PECVD reaction, and then the polycrystalline silicon is prepared through excimer laser annealing. Wherein the polysilicon may be N doped, i.e., N + Poly.

As shown in fig. 5, in step S505, a third ion implantation is performed on two sides of the conductive channel to form a first lightly doped region and a second lightly doped region, respectively.

Fig. 9 is a cross-sectional view after step S505 is completed, and as shown in fig. 9, in addition to forming the anti-state doped region 607 in the conductive channel, ion implantation is performed on both sides of the conductive channel to form a first lightly doped region 605 and a second lightly doped region 606, respectively. In the step, the energy of the third ion implantation is 15-35 KeV, and the ion concentration is 5E 13-2E 14 per square centimeter. As shown in fig. 9, the ion depth in the counter-doped region 607 is deeper than the ion depths in the first lightly doped region 605 and the second lightly doped region 606, and the counter-doped region 607 exists only at one side, so that the conductive channel 620 of an asymmetric structure can be formed.

As shown in fig. 5, in step S506, a fourth ion implantation is performed in the conductive channel near the first lightly doped region and the second lightly doped region to form a first doped region and a second doped region, respectively.

Fig. 10 is a cross-sectional view after step S506 is completed, and as shown in fig. 10, a first doped region 603 (i.e., a source doped region) and a second doped region 604 (i.e., a drain doped region) are respectively formed on two sides of a conductive channel 620 (specifically, near the first lightly doped region 605 and the second lightly doped region 606) in the P-well 602 through an ion implantation process. Wherein the first lightly doped region 605 is close to one side of the first doped region 603, and the second lightly doped region 606 is close to one side of the second doped region 604.

The ion type implanted in the fourth ion implantation in the step is also N-type ions such As P or As. Wherein the counter doped region 607 in the asymmetric structure is located on a side of the conductive channel 620 near the drain doped region 604. When the fourth ion implantation is performed to form the source/drain doped region, the energy of the ion implantation is 15 to 25KeV, and the ion concentration is 5E13 to 5E15 per square centimeter.

As shown in fig. 5, in step S507, a gate metal, a source metal, and a drain metal are formed through a patterning process.

This step forms a gate metal over the polysilicon gate layer 609, a source metal over the source doped region 603, and a drain metal over the drain doped region 604, resulting in the semiconductor device shown in fig. 3.

In the ion implantation step, a predetermined mask is used for masking, so as to form a desired structure on the substrate.

In an exemplary embodiment of the present disclosure, the first ion implantation and the second ion implantation are of opposite ion types, and the first ion implantation and the third ion implantation are of the same ion type.

Finally, the gate metal is connected to the gate control line to input the gate signal Vg to the gate, and the drain metal is connected to the data line to input the data signal Vd to the drain, as shown in fig. 3.

Based on the manufacturing method, on one hand, the width of the conductive channel at one side of the drain electrode can be widened by controlling the doping in the conductive channel of the semiconductor device to form an asymmetric structure, so that the electric field at one side of the drain electrode is reduced, the hot carrier injection phenomenon is reduced, the HCI degree of electrons in a drain electrode-grid electrode area (namely the area of the conductive channel close to the drain electrode) is reduced, and the electrical performance of the semiconductor device is improved.

Those skilled in the art will appreciate that the above-described figures are merely illustrative of the processes involved in a method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A semiconductor device, comprising:

the semiconductor device comprises a semiconductor substrate, a first substrate and a second substrate, wherein the semiconductor substrate comprises a conductive channel and a first doped region and a second doped region which are positioned on two sides of the conductive channel; and

the gate structure is located above the conductive channel, an asymmetric structure formed by a counter-state doped region is arranged in the conductive channel corresponding to the gate structure, the counter-state doped region is arranged on one side, close to the first doped region, of the conductive channel or on one side, close to the second doped region, of the conductive channel, the length of the counter-state doped region is smaller than that of the conductive channel, and the counter-state doped region is the same as the type of doped ions in the first doped region and/or the second doped region.

2. The semiconductor device according to claim 1, further comprising in the semiconductor substrate:

3. The semiconductor device of claim 2, wherein the counter-doped region is of the same type as the dopant ions in the first lightly doped region and/or the second lightly doped region.

4. The semiconductor device of claim 1, wherein a ratio of a length of the counter-doped region to a length of the conductive channel is 0.5 to 0.8.