CN102543742A - Injection method for controlling volume of tidal (VT) of metal oxide semiconductor (MOS) device - Google Patents
Injection method for controlling volume of tidal (VT) of metal oxide semiconductor (MOS) device Download PDFInfo
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Abstract
The invention provides an injection method for controlling volume of tidal (VT) of a metal oxide semiconductor (MOS) device. According to the injection method, doping is performed in an active region once or more times with different types of doping energy; a first doped layer and a second doped layer are formed at different depth positions respectively in a substrate below a grid; and therefore, the drain induced barrier lowering (DIBL) effect can be reduced, and the performance of the MOS device can be improved.
Description
Technical field
The present invention relates to a kind of semiconductor making method, particularly a kind of method for implanting of controlling MOS device VT.
Background technology
At present; Mos field effect transistor (MOSFET) device architecture comprises: as shown in Figure 1; Be positioned at the gate oxide 102 on substrate 101 surfaces, the grid 103 of gate oxide 102 tops; The conducting channel 104 that the substrate surface of gate oxide below forms lays respectively at source electrode 106 and drain electrode 107 in the grid 103 both sides substrates, and nitrogen oxide (silica and the silicon nitride) side wall 105 (Spacer) that is looped around gate lateral wall.Nitrogen oxide side wall 105 can be protected grid 103 on the one hand, source, the drain electrode that can prevent to form source electrode 106 and drain electrode 107 on the other hand inject with conducting channel 104 too near and produce leakage current even the source electrode 106 and the conducting between 107 that drains.Some is overlapping for conducting channel 104 and drain electrode 107, and behind grid 103 making alives, the interface between drain electrode 107 and substrate 101 forms PN junction, forms conducting channel 104 in the substrate of grid below.According to the difference of carrier type in the conducting channel 104, MOS is divided into cavity type mos field effect transistor (PMOS) and electron type mos field effect transistor (NMOS) again.
Along with the grid size of MOS device constantly reduces; The length of the conducting channel of grid below also constantly reduces; Can cause short-channel effect when the length of conducting channel narrows down to certain limit, comprise that drain electrode causes potential barrier and reduces (DIBL) and source-drain electrode break-through (punch through).Generally adopt in the prior art lightly doped drain (Lightly doped drain LDD) reduces junction depth and the DIBL effect of PN junction with banded doped-drain (pocket implant drain) technology, raising MOS device performance, still.Only can not satisfy the demand of MOS device performance with LDD and pocket implant drain technology.To this problem, people propose to control on the conducting channel surface injection technique of MOS device threshold voltage (VT), are used to regulate threshold voltage.The injection technology of influence control MOS device VT comprises two very important parameters: the implantation dosage and the injection degree of depth.From being with angle; When the injection degree of depth is more shallow; Adopt Fermi level that lower implantation dosage can make source electrode and drain electrode the closer to the centre, the degree of crook of Fermi level is more little, and the DIBL effect also can weaken; But because the conducting channel surface concentration reduces, the MOS device performance but descends inevitably to some extent.
When the injection degree of depth is dark, adopt bigger implantation dosage, make that the surface concentration of conducting channel is big more; Majority carrier concentration is big more, and corresponding minority carrier concentration is more little, so leakage current also reduces; The operating current of MOS device is big more, and the MOS device performance is good more.But, because the increase of conducting channel surface concentration has strengthened the DIBL effect.Therefore concerning the injection of once controlling MOS device VT, be difficult to satisfy simultaneously the requirement that reduces the DIBL effect and improve the MOS device performance.
Summary of the invention
In view of this, the technical problem that the present invention solves is: in the MOS device, to the injection of once controlling MOS device VT that carry out on the conducting channel surface of grid below, be difficult to satisfy simultaneously reduction DIBL effect and the requirement that improves the MOS device performance.
For addressing the above problem, technical scheme of the present invention specifically is achieved in that
A kind of method for implanting of controlling MOS device VT provides the wafer with substrate, is isolated in the said substrate by the shallow trench that completes in the said substrate and defines active area, and this method comprises:
Be mask with the photoengraving pattern that exposes gate window after the photoetching; Said active area is carried out first respectively to mix and second doping; Dosage that wherein once mixes and energy be all less than the dosage and the energy of another time doping, forms first doped layer and second doped layer in the different depth position of active area.
The ratio of the dosage of said twice doping is 1.5 to 2.5 times.
The less dosage range that once mixes of said dopant dose is that 2E11 atom/square centimeter arrives 2E12 atom/square centimeter, and the dosage range that once mixes that said dopant dose is bigger is that 1E12 atom/square centimeter is to 4E12 atom/square centimeter; Ion injection method is adopted in said twice doping, and the scope of the ion beam that said ion injects and the normal angulation of wafer device side is 2 to spend to 15 and spend; The scope that said ion injects wafer marked line and ion implantor stylobate directrix angulation is 0 to spend to 45 and spend.
The impurity of said first, second doping is boron or boron fluoride.
The impurity of said first, second doping is arsenic or phosphorus.
Said first dosage that mixes and energy all less than the dosage of second dosage that mixes and energy or said first doping and energy all greater than the dosage and the energy of second doping.
The dosage of said first doping is less than the dosage of second doping; The energy range of said first doped with boron is that 2 kilo electron volts are to 5 kilo electron volts; The energy range of the said first doping boron fluoride is that 6 kilo electron volts are to 20 kilo electron volts; The energy range of said second doped with boron is that 6 kilo electron volts are to 12 kilo electron volts; The energy range of the said second doping boron fluoride is that 21 kilo electron volts are to 35 kilo electron volts.
Said first dosage that mixes is all less than second dosage that mixes; The energy range of said first arsenic doped is that 10 kilo electron volts are to 30 kilo electron volts; The energy range of said second Doping Phosphorus is that 3 kilo electron volts are to 10 kilo electron volts; The energy range of said first arsenic doped is that 40 kilo electron volts are to 90 kilo electron volts; The energy range of said second Doping Phosphorus is that 11 kilo electron volts are to 28 kilo electron volts.
A kind of method for implanting of controlling MOS device VT, this method further comprises: before said first mixes or after second doping, in said active area, carry out trap injection and conducting channel and inject.
Visible by above-mentioned technical scheme; The method for implanting of the control MOS device VT that the present invention proposes; Doping more than in active area, carrying out once with different implant energies; In the substrate below grid, form the more than one doped layer of different depth position respectively, can when reducing the DIBL effect, improve the performance of MOS device.
Description of drawings
Fig. 1 is the cross-sectional view of MOS device in the prior art;
Fig. 2 controls the method for implanting flow chart of nmos device VT for the present invention;
Each cross-sectional view of the injection of nmos device VT is controlled for pressing Fig. 2 flow process in Fig. 3～4;
Fig. 5 controls the method for implanting flow chart of PMOS device VT for the present invention;
Each cross-sectional view of the injection of PMOS device VT is controlled for pressing Fig. 5 flow process in Fig. 6～7.
Embodiment
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
A kind of method for implanting of controlling MOS device VT, this method can reduce the DIBL effect when improving the MOS device performance.
Specific embodiment one
Be example with wafer (Wafer) below,, specify the injection process that the present invention shown in Fig. 2 controls nmos device VT in conjunction with Fig. 3～4 with substrate.Substrate of the prior art can be that doping type is the n type substrate of electron type or the p type substrate that doping type is cavity type.Have shallow trench isolation in the substrate and leave, shallow trench isolation is from being separated into some active areas with substrate, and the step of controlling nmos device VT injection in the active area is following:
In this step, said substrate 300 can be monocrystalline silicon, polysilicon or amorphous silicon; Said substrate 300 also can be silicon, germanium, GaAs or silicon Germanium compound; This substrate 300 can also have epitaxial loayer or insulating barrier silicon structure; Said substrate 300 can also be other semi-conducting materials, enumerates no longer one by one here.
In addition, can also have the P trap in the said substrate 300, said P trap can use the method for those skilled in the art institute convention to form, and for example, on substrate 300, defines the zone of P trap earlier through photoetching process, carries out ion then and injects, and forms the P trap;
In this step; Photoetching is meant; Surface-coated one deck photoresist in wafer device side; As required mask plate pattern makes public and develops then, makes the photoresist patterning form photoengraving pattern, the gate window that forms on the photoengraving pattern defined follow-up will manufacturing grid, the position of gate oxide and conducting channel; First to mix 302 be mask with the photoengraving pattern, and the substrate 300 of method below grid that adopts ion to inject forms first doped layer 303, and for nmos device, first mix 302 the impurity is boron (B) or boron fluoride (BF
2), be example with the doped with boron, the scope of first doping, 302 energy is that 2 kilo electron volts (KeV) arrive 5KeV, for example, 2KeV, 4KeV and 5KeV; The scope of first doping, 302 dosage is that 2E11 atom/square centimeter arrives 2E12 atom/square centimeter, for example, and 2E11 atom/square centimeter, 1E12 atom/square centimeter and 2E12 atom/square centimeter; Ion beam and wafer device side normal angulation that ion injects are called implant angle, and the implant angle scope is 2 to spend to 15 degree, and for example 2 degree, 5 degree and 15 are spent; Wafer marked line (notch) and ion implantor stylobate directrix angulation are called wafer initial rotation angle degree, and wafer initial rotation angle degree scope is 0 to spend to 45 degree, for example 0 degree, 30 degree and 45 degree.With the doping boron fluoride is example, first mix 302 energy scope be 6KeV to 30KeV, for example, 6KeV, 10KeV and 30KeV; The scope of first doping, 302 dosage is that 2E11 atom/square centimeter arrives 2E12 atom/square centimeter, for example, and 2E11 atom/square centimeter, 1E12 atom/square centimeter and 2E12 atom/square centimeter; The implant angle scope be 2 spend to 15 the degree, for example 2 the degree, 5 the degree and 15 the degree; Wafer initial rotation angle degree scope be 0 spend to 45 the degree, for example 0 the degree, 30 the degree and 45 the degree.
It should be noted that in order to reduce the doping content on conducting channel surface, require first of this step to mix 302 dosage less than mix 304 dosage of second in the subsequent step 202; Particularly, under the situation of identical impurity of mixing, second mix 304 the dosage is first mix 1.5 to 2.5 times of 302 dosage, for example, 1.5 times, 2 times and 2.5 times.In order to guarantee in the zone of active area different depth, to form first doped layer 303 and second doped layer 305 respectively; Under the situation of identical impurity of mixing; Require the energy of first doping, 302 energy, could realize the degree of depth of the degree of depth of first doped layer 303 less than second doped layer 305 less than second doping 304.
In addition; Before the wafer device side photoetching; Can also be earlier at substrate 300 surfaces deposition of silica layer successively and silicon nitride layer (not drawing among the figure), after the wafer device side photoetching, be mask then with the photoengraving pattern, etch silicon nitride layer and silicon dioxide layer successively; Up to exposing substrate 300, form gate window jointly by photoengraving pattern, silicon nitride layer and silicon dioxide layer.
In this step, second to mix 304 be mask with the photoengraving pattern, and the substrate 300 of method below grid that adopts ion to inject forms second doped layer 305, and for nmos device, second mix 304 the impurity is B or BF
2, be example with doping B, second mix 304 energy scope be 6KeV to 12KeV, for example, 6KeV, 10KeV and 12KeV; The scope of second doping, 304 dosage is that 1E12 atom/square centimeter arrives 4E12 atom/square centimeter, for example, and 1E12 atom/square centimeter, 3E12 atom/square centimeter and 4E12 atom/square centimeter; The implant angle scope be 2 spend to 15 the degree, for example 2 the degree, 5 the degree and 15 the degree; Wafer initial rotation angle degree scope be 0 spend to 45 the degree, for example 0 the degree, 30 the degree and 45 the degree.With doping BF
2Be example, second mix 304 energy scope be 21KeV to 35KeV, for example, 21KeV, 30KeV and 35KeV; The scope of second doping, 304 dosage is that 1E12 atom/square centimeter arrives 4E12 atom/square centimeter, for example, and 1E12 atom/square centimeter, 3E12 atom/square centimeter and 4E12 atom/square centimeter; The implant angle scope be 2 spend to 15 the degree, for example 2 the degree, 5 the degree and 15 the degree; Wafer initial rotation angle degree scope be 0 spend to 45 the degree, for example 0 the degree, 30 the degree and 45 the degree.
It should be noted that first in the step 201 mixed and the order of second doping of step 202 can be changed, the difference of execution sequence can not influence the performance of nmos device.
In addition, can also in active area, carry out the technology of nmos devices such as trap injection and conducting channel injection before first mixes or after second doping, it is a prior art, repeats no more.
Specific embodiment two
Be example with Wafer below,, specify the injection process that the present invention shown in Fig. 5 controls PMOS device VT in conjunction with Fig. 6～7 with substrate 600.Substrate 600 of the prior art can be that doping type is that the n type substrate 600 or the doping type of electron type is the p type substrate 600 of cavity type.Have shallow trench isolation in the substrate 600 and leave, shallow trench isolation is from being separated into some active areas with substrate 600, and the step of controlling PMOS device VT injection in the active area is following:
In this step, said substrate 600 can be monocrystalline silicon, polysilicon or amorphous silicon; Said substrate 600 also can be silicon, germanium, GaAs or silicon Germanium compound; This substrate 600 can also have epitaxial loayer or insulating barrier silicon structure; Said substrate 600 can also be other semi-conducting materials, enumerates no longer one by one here.
In addition, can also have the N trap in the said substrate 600, said N trap can use the method for those skilled in the art institute convention to form, and for example, on substrate 600, defines the zone of N trap earlier through photoetching process, carries out ion then and injects, and forms the N trap;
In this step; Photoetching is meant, at surface-coated one deck photoresist of wafer device side, as required mask plate pattern makes public and develops then; Make the photoresist patterning form photoengraving pattern, the gate window on the photoengraving pattern is corresponding to zone that will manufacturing grid; First to mix 602 be mask with the photoengraving pattern; The substrate 600 of method below grid that adopts ion to inject forms first doped layer 603, and for the PMOS device, the impurity of first doping 602 is arsenic (As) or phosphorus (P); With the arsenic doped is example; The scope of first doping, 602 energy is that 10 kilo electron volts (KeV) arrive 60KeV, for example, and 10KeV, 20KeV and 60KeV; The scope of first doping, 602 dosage is that 2E11 atom/square centimeter arrives 2E12 atom/square centimeter, for example, and 2E11 atom/square centimeter, 1E12 atom/square centimeter and 2E12 atom/square centimeter; The implant angle scope be 2 spend to 15 the degree, for example 2 the degree, 5 the degree and 15 the degree; Wafer initial rotation angle degree scope be 0 spend to 45 the degree, for example 0 the degree, 60 the degree and 45 the degree.With the Doping Phosphorus is example, first mix 602 energy scope be 3KeV to 10KeV, for example, 3KeV, 5KeV and 10KeV; The scope of first doping, 602 dosage is that 2E11 atom/square centimeter arrives 2E12 atom/square centimeter, for example, and 2E11 atom/square centimeter, 1E12 atom/square centimeter and 2E12 atom/square centimeter; The implant angle scope be 2 spend to 15 the degree, for example 2 the degree, 5 the degree and 15 the degree; Wafer initial rotation angle degree scope be 0 spend to 45 the degree, for example 0 the degree, 30 the degree and 45 the degree.
It should be noted that in order to reduce the doping content on conducting channel surface, require first of this step to mix 602 dosage less than mix 604 dosage of second in the subsequent step 502; Particularly, under the situation of identical impurity of mixing, second mix 604 the dosage is first mix 1.5 to 2.5 times of 602 dosage, for example, 1.5 times, 2 times and 2.5 times.In order to guarantee in the zone of active area different depth, to form first doped layer 603 and second doped layer 605 respectively; Under the situation of identical impurity of mixing; Require the energy of first doping, 602 energy, could realize the degree of depth of the degree of depth of first doped layer 603 less than second doped layer 605 less than second doping 604.
In addition; Before the wafer device side photoetching; Can also be earlier at substrate 600 surfaces deposition of silica layer successively and silicon nitride layer (not drawing among the figure), after the wafer device side photoetching, be mask then with the photoengraving pattern, etch silicon nitride layer and silicon dioxide layer successively; Up to exposing substrate 600, form gate window jointly by photoengraving pattern, silicon nitride layer and silicon dioxide layer.
Step 502, as shown in Figure 7 mixes 604 to substrate 600 second, below first doped layer 603, forms second doped layer 605;
In this step, second to mix 604 be mask with the photoengraving pattern, and the substrate 600 of method below grid that adopts ion to inject forms second doped layer 605; For the PMOS device; The impurity of second doping 604 is As or P, is example with doping As, and the scope of second doping, 604 energy is that 40KeV is to 90KeV; For example, 40KeV, 70KeV and 90KeV; The scope of second doping, 604 dosage is that 1E12 atom/square centimeter arrives 4E12 atom/square centimeter, for example, and 1E12 atom/square centimeter, 3E12 atom/square centimeter and 4E12 atom/square centimeter; The implant angle scope be 2 spend to 15 the degree, for example 2 the degree, 5 the degree and 15 the degree; Wafer initial rotation angle degree scope be 0 spend to 45 the degree, for example 0 the degree, 60 the degree and 45 the degree.With doping P is example, second mix 604 energy scope be 11KeV to 28KeV, for example, 11KeV, 20KeV and 28KeV; The scope of second doping, 604 dosage is that 1E12 atom/square centimeter arrives 4E12 atom/square centimeter, for example, and 1E12 atom/square centimeter, 3E12 atom/square centimeter and 4E12 atom/square centimeter; The implant angle scope be 2 spend to 15 the degree, for example 2 the degree, 5 the degree and 15 the degree; Wafer initial rotation angle degree scope be 0 spend to 45 the degree, for example 0 the degree, 30 the degree and 45 the degree.
It should be noted that first in the step 501 mixed and the order of second doping of step 502 can be changed, the difference of execution sequence can not influence the performance of PMOS device.
In addition, can also in active area, carry out PMOS device making technics such as trap injection and conducting channel injection before first mixes or after second doping, it is a prior art, repeats no more.
Specific embodiment one is respectively the VT method for implanting to control nmos device and PMOS device with specific embodiment two; This method is through twice conductive doped raceway groove; Wherein once mix and adopt less implantation dosage and inject energy; Form the lower doped layer of doping content on the conducting channel surface, improve the DIBL effect of MOS device; Another time mixed and adopted bigger implantation dosage and inject energy; Put the higher doped layer of formation doping content at conducting channel than deep-seated; Majority carrier concentration is big more in the conducting channel, and corresponding minority carrier concentration is more little, and leakage current also reduces; The operating current of MOS device is big more, and the MOS device performance is good more.Effectively improved the MOS device performance, both influence each other at effect, have satisfied simultaneously and have reduced DIBL effect and the requirement that improves the MOS device performance.
The method for implanting of the control MOS device VT that the present invention proposes; Doping more than in active area, carrying out once with different implant energies; In the substrate below grid; Form first doped layer and second doped layer of different depth position respectively, can when reducing the DIBL effect, improve the performance of MOS device.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.
Claims (9)
1. a method for implanting of controlling MOS device VT provides the wafer with substrate, is isolated in the said substrate by the shallow trench that completes in the said substrate and defines active area, it is characterized in that this method comprises:
Be mask with the photoengraving pattern that exposes gate window after the photoetching; Said active area is carried out first respectively to mix and second doping; Dosage that wherein once mixes and energy be all less than the dosage and the energy of another time doping, forms first doped layer and second doped layer in the different depth position of active area.
2. method according to claim 1 is characterized in that, the ratio of the dosage of said twice doping is 1.5 to 2.5 times.
3. method according to claim 1 and 2; It is characterized in that; The less dosage range that once mixes of said dopant dose is that 2E11 atom/square centimeter arrives 2E12 atom/square centimeter, and the dosage range that once mixes that said dopant dose is bigger is that 1E12 atom/square centimeter is to 4E12 atom/square centimeter; Ion injection method is adopted in said twice doping, and the scope of the ion beam that said ion injects and the normal angulation of wafer device side is 2 to spend to 15 and spend; The scope that said ion injects wafer marked line and ion implantor stylobate directrix angulation is 0 to spend to 45 and spend.
4. method according to claim 1 and 2 is characterized in that, the impurity of said first, second doping is boron or boron fluoride.
5. method according to claim 1 and 2 is characterized in that, the impurity of said first, second doping is arsenic or phosphorus.
6. method according to claim 1 and 2 is characterized in that, said first dosage that mixes and energy all less than the dosage of second dosage that mixes and energy or said first doping and energy all greater than the dosage and the energy of second doping.
7. method according to claim 4 is characterized in that, the dosage of said first doping is less than the dosage of second doping; The energy range of said first doped with boron is that 2 kilo electron volts are to 5 kilo electron volts; The energy range of the said first doping boron fluoride is that 6 kilo electron volts are to 20 kilo electron volts; The energy range of said second doped with boron is that 6 kilo electron volts are to 12 kilo electron volts; The energy range of the said second doping boron fluoride is that 21 kilo electron volts are to 35 kilo electron volts.
8. method according to claim 5 is characterized in that, the dosage of said first doping is less than the dosage of second doping; The energy range of said first arsenic doped is that 10 kilo electron volts are to 30 kilo electron volts; The energy range of said first Doping Phosphorus is that 3 kilo electron volts are to 10 kilo electron volts; The energy range of said second arsenic doped is that 40 kilo electron volts are to 90 kilo electron volts; The energy range of said second Doping Phosphorus is that 11 kilo electron volts are to 28 kilo electron volts.
9. the method for implanting of control MOS device VT according to claim 1 and 2 is characterized in that this method further comprises: before said first mixes or after second doping, in said active area, carry out trap injection and conducting channel and inject.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102779759A (en) * | 2012-07-31 | 2012-11-14 | 杭州士兰集成电路有限公司 | Manufacture method of depletion mode metal-oxide-semiconductor field effect transistor (MOSFET) |
| CN104916545A (en) * | 2015-04-30 | 2015-09-16 | 上海华力微电子有限公司 | Semiconductor device manufacturing method |
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| US6506640B1 (en) * | 1999-09-24 | 2003-01-14 | Advanced Micro Devices, Inc. | Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through |
| CN101752254A (en) * | 2008-12-22 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation zone forming method, MOS transistor and manufacture method thereof |
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| US5719081A (en) * | 1995-11-03 | 1998-02-17 | Motorola, Inc. | Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant |
| US6506640B1 (en) * | 1999-09-24 | 2003-01-14 | Advanced Micro Devices, Inc. | Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through |
| CN101752254A (en) * | 2008-12-22 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation zone forming method, MOS transistor and manufacture method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102779759A (en) * | 2012-07-31 | 2012-11-14 | 杭州士兰集成电路有限公司 | Manufacture method of depletion mode metal-oxide-semiconductor field effect transistor (MOSFET) |
| CN104916545A (en) * | 2015-04-30 | 2015-09-16 | 上海华力微电子有限公司 | Semiconductor device manufacturing method |
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