JP3425883B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor having an improved operating speed and reduced power consumption, and a method for manufacturing the same.

[0002]

2. Description of the Related Art As the demand for higher performance of semiconductor devices increases, MOSFETs forming semiconductor devices are required to have higher operating speed and lower power consumption. In order to improve the operating speed, it is effective to increase the drain saturation current (hereinafter referred to as "on-current"). on the other hand,
In order to reduce the power consumption, it is effective to reduce the current (hereinafter, referred to as “off current”) flowing between the source and the drain when the gate voltage is not applied.

Various studies have heretofore been made to increase the on-current. JP-A-7-16985
Japanese Unexamined Patent Publication No. 8 discloses a technique of increasing the on-current of a transistor by making the source / drain regions of the LDD structure asymmetrical. Also, Japanese Patent Laid-Open No. 10-1287
In JP-A-0-gazette, by providing a high-concentration layer inside the low-concentration layer in the source / drain region of the LDD structure,
There is disclosed a technique for improving the on-current while maintaining the electric field relaxation effect by.

However, these methods change the source / drain structure, which complicates the process and adds certain restrictions to the source / drain structure.

By the way, the adoption of the source / drain extension structure is becoming mainstream as the miniaturization of the device progresses and the gate oxide film becomes thinner. The source / drain extension structure is a structure in which the high-concentration impurity layers 5 and 6 project to a region directly below the gate electrode as shown in FIG. 11 (note that if the high-concentration impurity layers 5 and 6 are replaced with low-concentration impurity layers). LDD structure). With the extension structure as described above, it is possible to reduce the on-resistance and achieve high-speed operation of the element. The extension structure has conventionally been considered to have a problem of poor hot carrier resistance. However, when the gate oxide film becomes thin due to the miniaturization of the element, and the thickness becomes, for example, 3 nm or less, the effect of hot carriers is significantly reduced, and the merit of increasing the operation speed of the element increases.

Under these circumstances, the source / drain extension structure is preferably used in a device having a gate length of 0.2 μm or less and a gate insulating film of 3 nm or less.

However, the technique described in the above publication is not limited to LDD.
Since it is based on the structure, it was difficult to apply it to the source / drain extension structure.

Although the reduction of the on-current has been described above, the reduction of the off-current is also important. The off current is a drain current in a state where the gate voltage is not applied and the transistor is not driven. Therefore, by reducing the off current, standby power consumption can be reduced. However, the above-mentioned conventional technique is not always sufficient in reducing the off-current.

[0009]

In view of the above circumstances, the present invention improves the on-current or reduces the off-current without restricting the source / drain structure, thereby improving the operating speed or consuming the transistor. The purpose is to reduce power consumption.

[0010]

According to the present invention, a step of introducing an impurity of one conductivity type into an element region of a silicon substrate and a step of forming a gate electrode on the element region via a gate insulating film. A step of forming a source region and a drain region of a conductivity type opposite to that of the impurity so as to sandwich the gate electrode; a step of ion-implanting the source region to generate interstitial silicon; and a heat treatment for the interstitial silicon. And a step of diffusing the impurities into the channel region, there is provided a method for manufacturing a semiconductor device.

[0011]

That is, according to the present invention, the step of introducing an impurity of one conductivity type into the element region of the silicon substrate, the step of forming a gate electrode on the element region via a gate insulating film, and the impurity Forming a source region and a drain region of opposite conductivity type so as to sandwich the gate electrode; forming an interstitial silicon by implanting ions into the source region; and heat treating the impurities together with the interstitial silicon by heat treatment. And a step of diffusing into a channel region.

[0013]

Further, according to the present invention, the following method for manufacturing an N-channel MOSFET and a P-channel MOSFET is provided.

That is, according to the present invention, a step of introducing a p-type impurity into the element region of the silicon substrate, a step of forming a gate electrode on the element region via a gate insulating film, and a step of forming the gate electrode in the element region A step of forming an n-type source region and a drain region so as to sandwich the gate electrode, a step of ion-implanting Si, Ge, or a group V element into the source region, and a step of performing heat treatment at 600 to 800 ° C. A method for manufacturing a semiconductor device is provided.

[0016]

Further, according to the present invention, a step of introducing an n-type impurity into the element region of the silicon substrate, a step of forming a gate electrode on the element region via a gate insulating film, and a step of forming the gate electrode in the element region A step of forming a p-type source region and a drain region so as to sandwich the gate electrode, a step of ion-implanting Si, Ge, or a group III element into the source region, and a step of performing heat treatment at 600 to 800 ° C. There is provided a method for manufacturing a semiconductor device, comprising:

[0018]

The semiconductor device of the present invention aims to solve the problem by making the impurity concentration of the channel region non-uniform. In the conventional MOSFET, the impurity concentration of the channel region is substantially uniform. On the other hand, in the present invention, the source side channel impurity concentration is set higher than the drain side channel impurity concentration. This can improve the on-current when the threshold voltage is constant.
Further, it is possible to reduce the off current when the on current is constant.

Since the source side channel impurity concentration of the semiconductor device of the present invention is higher than the drain side channel impurity concentration, the on-current can be improved without changing the threshold voltage Vth of the MOSFET. This point will be described with reference to FIG. The graph in the figure is
MOSFET of the present invention and MOSFE of the prior art
The impurity concentration distribution near the surface of the T channel region 15 is shown. In this example, boron is used as the impurity.
Both have the same impurity concentration n _A at the source side end. Since the threshold voltage is a voltage at which the inversion layer is formed on the source side, its value is determined by n _A. Therefore, the threshold voltages of both MOSFETs having a common n _A coincide with each other. On the other hand, the impurity concentration n _B at the drain side end is lower in the present invention than in the prior art. The on-current value is dominated by the voltage at which pinch-off occurs, and this is dominated by the impurity concentration n _B on the drain side. Therefore, in the MOSFET of the present invention, the pinch-off voltage rises, and as a result, the on-current increases as compared with the conventional technique in which the impurity concentration of the channel region 15 is uniform.

The effect of reducing the on-current according to the present invention has been described above. However, the off-current can be reduced by increasing the threshold voltage while keeping the on-current constant compared with the conventional MOSFET. This point will be described below with reference to FIG.

The on-current value is controlled by the voltage at which pinch-off occurs, and this is controlled by the impurity concentration n _B on the drain side. Therefore, as shown in FIG.
By making T and the MOSFET of the present invention have the same impurity concentration on the drain side, the ON current values of both can be made equal. On the other hand, the threshold voltage is controlled by the impurity concentration n _A on the source side. In the present invention, n _A is higher than that of the conventional one, which raises the threshold voltage and consequently the off current.

As described above, the semiconductor device of the present invention has n _A
Since> n _B , the on-current can be improved or the off-current can be reduced. When the on-current is improved, the operating speed can be improved and the power consumption can be reduced. On the other hand, when the off current is reduced, standby power consumption, that is, power consumption when the transistor is not driven can be reduced. The desired effect can be obtained by appropriately adjusting the absolute value of n _A according to the purpose.

Next, a method of manufacturing the semiconductor device of the present invention will be described. In the conventional manufacturing method, the threshold voltage is controlled by the amount of impurities introduced in the step of introducing the impurities. On the other hand, in the present invention, the threshold voltage is controlled by the sum of the amount of impurities introduced in the above process and the amount of impurities diffused into the source region together with the interstitial silicon. That is, in the present invention, (source-side impurity concentration n _A ) = (impurity introduction amount) + (impurity diffusion amount) (drain-side impurity concentration n _B ) = (impurity introduction amount), and the state of n _A > n _B is simplified. Can be formed into Moreover, since the diffusion amount of the impurities can be easily controlled by setting the heat treatment conditions, n _A can be accurately controlled, and the desired impurity distribution can be easily realized.

In the method of manufacturing a semiconductor device of the present invention,
Either the source / drain region forming step or the step of forming interstitial silicon may be performed first. If interstitial silicon is generated before the source / drain region forming step, annealing for diffusion of interstitial silicon and annealing for forming the source / drain regions can be performed at the same time, which improves process efficiency. it can. On the other hand, when the interstitial silicon is generated after the source / drain region forming step, the interstitial silicon generation efficiency is good and the controllability of the source side impurity concentration n _A is good. Which order to use
The P-channel MO is selected as appropriate depending on the application of T, etc.
In the case of SFET, it is preferable to generate interstitial silicon after the source / drain region forming step. When the source / drain regions are activated by heat treatment after the formation of interstitial silicon, the interstitial silicon and the channel forming impurities are diffused at this time. Here, since the heat treatment for activating the source / drain regions is usually performed at a high temperature for a short time by RTA or the like, it is difficult to control the diffusion amount of impurities by this heat treatment. Therefore, even if an annealing step for impurity diffusion is separately provided thereafter, the source side impurity concentration n _A should be well controlled because a certain amount of interstitial silicon and channel forming impurities have already diffused. Is not always easy. This tendency is P
Since it is remarkable in the case of the channel MOSFET, it is preferable to generate interstitial silicon after the source / drain region forming step in the case of the P-channel MOSFET.

In the case of an NMOSFET using boron as an impurity in the channel region, the interstitial silicon / boron diffusion diffuses in silicon at an extremely fast rate. Therefore, even in this case, if interstitial silicon is generated before forming the source / drain regions, controllability of the source-side impurity concentration n _A tends to be difficult. Therefore, the NMO using boron as an impurity in the channel region
When the controllability of n _A is prioritized in the SFET, it is preferable to generate interstitial silicon after forming the source / drain regions.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, n _A > 10 × n _B
It is preferable that As a result, the degree of improvement of on-current or reduction of off-current becomes remarkable.

The present invention is an N-channel MOSFET and a P
Although it can be applied to any of the channel MOSFETs, particularly when applied to the N-channel MOSFET, a remarkable effect can be obtained. That is, a remarkable effect is obtained when the conductivity type of the impurities is p-type and the conductivity types of the source region and the drain region are n-type. It is particularly effective to use boron as the impurity in the channel region. Boron easily combines with interstitial silicon and moves in silicon at a high diffusion rate. Therefore, when boron is used as an impurity, the difference between n _A and n _B can be easily increased, and the on-current is improved or the off-current is significantly reduced. P-channel MOSF
In ET, it is preferable that the impurity introduced into the channel region is arsenic. As a result, the difference between n _A and n _B can be easily made relatively large, and the degree of improvement of the on-current or reduction of the off-current becomes remarkable.

In the present invention, the values of n _A and n _B are appropriately set according to the purpose, but are set as follows, for example. That is, for n _A , preferably 1 × 10 ¹⁷ cm ⁻³ to
1 × 10 ¹⁹ cm ⁻³ , more preferably 5 × 10 ¹⁷ cm ⁻³
˜1 × 10 ¹⁸ cm ⁻³ . On the other hand, n _B is preferably 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , and more preferably 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . In this way, for example, the degree of improvement of the ON current becomes remarkable.

In the present invention, the source region and the drain region preferably have an extension structure. Thereby, the driving speed of the MOSFET can be further increased. As shown in FIG. 11, the extension structure is a structure in which the ends of the source / drain regions are projected to a region below the gate electrode and a high concentration of impurities is introduced into the projected portions.

In the method of manufacturing a semiconductor device of the present invention,
It is preferable that interstitial silicon is not substantially generated when the source / drain regions are formed. If interstitial silicon is generated during the formation of the source / drain regions, the impurities may segregate on the drain region side of the channel region, and it may be difficult to form a good impurity distribution in the channel region. is there. Therefore, it is desirable that the source / drain regions be formed by ion implantation with an acceleration voltage of 8 keV or less. Generation of interstitial silicon can be suppressed by implanting ions at such a low acceleration voltage.

In the method of manufacturing a semiconductor device of the present invention,
The ion species for generating interstitial silicon is preferably Si, Ge, or a group V element in the case of an N-channel MOSFET, and Si, Ge, or a group III element in the case of a P-channel MOSFET. preferable. Here, the group V element is preferably P or As, and the group III element is preferably In. Interstitial silicon can be effectively generated by using the ionic species as described above. The accelerating voltage for ion implantation is appropriately set depending on the type of ion implanted, and is, for example, 5 to 30 k.
It is set in the range of eV. 5 to 15 keV for phosphorus
Is preferable, and in the case of arsenic, 20 to 30 keV is preferable. By doing so, it is possible to effectively generate interstitial silicon while suppressing damage to the substrate.
If it is lower than the above range, interstitial silicon is less likely to be generated, and if it is higher than the above range, problems such as a short channel effect may occur.

The present invention can also be applied to a power MOSFET. In the power MOSFET, it is desired to improve the noise resistance by improving the threshold voltage, but according to the present invention, the impurity concentration on the source side can be increased by the action of interstitial silicon. Therefore, the threshold voltage can be improved and excellent noise resistance can be realized.

[0034]

Embodiment 1 This embodiment shows an example in which the present invention is applied to an NMOS. Hereinafter, description will be made with reference to FIG.

First, STI is formed on the p-type silicon substrate 1.
After forming the element isolation film 2 by (Shallow Trench Isolation), boron ion implantation was performed. This ion implantation is intended to adjust the threshold voltage, and the ion implantation conditions are an acceleration voltage of 80 keV and a dose amount of 6 × 10 ¹² c.
m ^-2 (Fig. 3 (a)). In this embodiment, the threshold voltage is designed to be 0.2V. When such a threshold voltage is used, the dose amount is about 1 × 10 ¹³ cm ^{−2 in} the conventional technique, but in the present embodiment, the dose amount is lower than this.

Subsequently, pyrogenic oxidation was performed at 850 ° C., and a gate oxide film 3 having a thickness of 3 nm was formed on the surface of the active region.
Then, a polysilicon film having a thickness of 150 nm was deposited thereon and patterned by selective etching to form the gate electrode 4 (FIG. 3B). The gate length is 0.
It was set to 18 μm.

Next, ion implantation for forming an extension structure was performed. Ion species is As and acceleration voltage is 5k
The eV and dose amount were set to 5 × 10 ¹⁴ cm ⁻² . Thereby, high impurity concentration layers 5 and 6 were formed (FIG. 3C).

Next, a side wall is formed on the side wall of the gate electrode 4.
After forming the rule 7, ion implantation was performed on the entire surface. ion
The seed is As, the acceleration voltage is 8 keV, and the dose amount is 3 × 10.¹⁵
cm ^-2And As a result, As is injected into the gate electrode.
And As implantation into the source / drain region formation location at the same time
To be done. After As injection, at 1050 ° C under nitrogen atmosphere
When heat treatment is performed to activate As in the gate electrode,
The source region 8 and the drain region 9 are formed in
(FIG. 4 (a)).

Next, a resist mask 11 having an opening in the source region was formed, and P (phosphorus) was ion-implanted in the source region 8. Here, the acceleration voltage was 10 keV and the dose amount was 3 × 10 ¹⁴ cm ⁻² . As a result, the phosphorus-implanted region 12 is formed so as to overlap the source region 6 (FIG. 4B). By performing this ion implantation,
Interstitial silicon is generated. The interstitial silicon tends to be distributed particularly in the peripheral portion of the source region 8 and easily bonds with boron already introduced into the substrate. Hereinafter, a combination of interstitial silicon and boron is referred to as a BI pair.

After phosphorus injection, heat treatment was performed at 700.degree. The behavior of the BI pair 14 at this time is shown in FIG.
It shows in (b). Since the BI pair 14 has a high diffusion rate in silicon, the BI pair 14 easily diffuses in the silicon substrate 1 by the heat treatment. In addition, BI pair 14 is Si
Since it has the property of being easily segregated at the interface between different materials such as O ₂ and Si, it is distributed particularly in the vicinity of the gate insulating film. Therefore, the BI pair 1 can be obtained by performing the above heat treatment.
4 moves to the channel region 15 just below the gate electrode. After the heat treatment, the boron concentration on the source region 8 side becomes higher than the boron concentration on the drain region 9 side (FIG. 5B).

FIG. 6 is a conceptual diagram of the boron concentration distribution after the heat treatment.
Shown in. Although the figure shows the boron concentration in the vicinity of the surface of the channel region 15, the boron concentration n _A at the end of the channel region 15 on the source region 8 side is the same as the drain region 9.
It is higher than the boron concentration n _B at the side end. Although the threshold voltage is determined by the boron concentration n _A , in the present embodiment, the threshold voltage is adjusted to 0.2 V by setting the phosphorus implantation conditions and the subsequent heat treatment conditions as described above. That is, the sum of the amount of boron introduced and the amount of boron diffused in the source region together with the interstitial silicon is adjusted so as to realize the threshold voltage of 0.2V.

On the other hand, the drain region 7 of the channel region 12
Since the boron concentration is low at the side end portion, the on-current is increased as compared with the conventional case where the impurity concentration in the channel region is uniform.

Comparative Example 1 For comparison, a MOSFET was manufactured by a conventional method.
That is, phosphorus ion implantation is not performed, and FIG.
A MOSFET was manufactured in the same manner as in Example 1 except that the dose amount of boron implantation in 1 was set to 1 × 10 ¹³ cm ^-2 .

The N-chi produced in Example 1 and Comparative Example 1
The electrical characteristics of the channel MOSFET were evaluated.
The MOSFET of Example 1 has a threshold voltage of 0.2 V and an on-current.
Is V _G= 600 V / μm at 1.5 V.
On the other hand, in the MOSFET of Comparative Example 1, the threshold voltage is the same.
Yes, the on-current is V_G= 540μA / when 1.5V
was μm. The off current is 2 nA / μm in all cases.
Met. As a result, the on-current improvement according to the present invention
The effect of was confirmed.

[0045] Example 2 FIG. 3 the dose of boron implanted in (a) 1 × 10 ¹³
MOSF in the same manner as in Example 1 except that cm ⁻² was used.
ET was made. The manufactured MOSFET had a threshold voltage of 0.25 V, an off current of 550 pA / μm, and an on current of 540 μA / μm when V _G = 1.5 V. In the conventional MOSFET, the threshold voltage was 0.2 V and the off-current was 2 nA / μm at the same on-current, so that the effect of reducing the off-current according to the present invention was confirmed.

Embodiment 3 This embodiment shows an example in which the present invention is applied to a PMOS. Hereinafter, description will be given with reference to FIG. 7.

First, on a p-type silicon substrate, STI (Sh
After forming the element isolation film 2 by allow trench isolation, phosphorus was implanted into the entire surface to form the well region 20. Next, arsenic ion implantation was performed on the surface of the element region. This ion implantation was intended to adjust the threshold voltage, and the ion implantation conditions were an acceleration voltage of 100 keV and a dose amount of 5 × 10 ¹² cm ^-2 (FIG. 7A). In this embodiment, the threshold voltage is designed to be 0.3V. When such a threshold voltage is used, in the conventional technique, the dose amount is 2 × 10.
^{Although the} dose is about ¹² cm ^{-2, the} dose amount is lower than that in this embodiment. Subsequently, pyrogenic oxidation is performed at 850 ° C. to form a gate oxide film 3 having a thickness of 4 nm on the surface of the active region, and then a polysilicon film 15 is formed thereon.
0 nm was deposited and patterned by selective etching to form the gate electrode 4 (FIG. 7B). The gate length was 0.18 μm.

Next, a pattern for forming the extension structure is formed.
ON injection was performed. The ion species is BF ₂And accelerating voltage 5
keV, dose 1 × 10¹⁴cm^-2And This
High impurity concentration layers 5 and 6 were formed (FIG. 7C).

Next, after forming the side wall 7 on the side wall of the gate electrode 4, ion implantation is performed on the entire surface. The ion species is boron, the acceleration voltage is 2 keV, and the dose is 5 × 10.
^{It was set to 15} cm ^-2 . As a result, the boron implantation to the gate electrode and the boron implantation to the source / drain region formation location are simultaneously performed. After boron injection, 10 in nitrogen atmosphere
A heat treatment at 50 ° C. was performed to activate boron in the gate electrode and form the source region 8 and the drain region 9 (FIG. 8A). In this embodiment, boron is used as the p-type impurity, but this suppresses the occurrence of boron penetration as compared with the case of using BF ₂ .

Next, a resist mask 11 having an opening in the source region was formed, and silicon was ion-implanted into the source region 8. Here, the acceleration voltage was 10 keV and the dose amount was 3 × 10 ¹⁴ cm ⁻² . As a result, the silicon implantation region 21 is formed so as to overlap the source region 6 (FIG. 8B). Interstitial silicon is generated by performing this ion implantation. The interstitial silicon is distributed especially in the peripheral portion of the source region 8.

After implanting silicon, heat treatment was performed at 700.degree. At this time, due to the action of interstitial silicon,
Arsenic 22 moves to the channel region just below the gate electrode (FIGS. 9A and 9B). After the heat treatment, the arsenic concentration on the source region 8 side becomes higher than the arsenic concentration on the drain region 9 side (FIG. 9B).

A conceptual diagram of the arsenic concentration distribution after heat treatment is shown in FIG.
Shown in. Although the figure shows the arsenic concentration near the surface of the channel region 15, the arsenic concentration n _A at the end of the channel region 15 on the source region 8 side is higher than the arsenic concentration n _B at the end of the drain region 9 side. There is. The threshold voltage is determined by the arsenic concentration n _A, but in this embodiment, the threshold voltage is adjusted to 0.2 V by setting the phosphorus implantation conditions and the subsequent heat treatment conditions as described above. . That is, the sum of the amount of arsenic introduced and the amount of arsenic diffused in the source region together with interstitial silicon is
It is adjusted to achieve a threshold voltage of 0.2V.

On the other hand, the drain region 7 of the channel region 12
The arsenic concentration is low at the side end portion, and the on-current is increased as compared with the conventional case where the impurity concentration in the channel region is uniform.

Comparative Example 2 For comparison, a MOSFET was manufactured by a conventional method.
That is, without performing ion implantation of silicon,
The dose of arsenic implantation in (a) is 8 × 10 ¹² cm ^-2
A MOSFET was produced in the same manner as in Example 3 except that the above was adopted.

N-chi produced in Example 3 and Comparative Example 2
The electrical characteristics of the channel MOSFET were evaluated.
The MOSFET of Example 3 has a threshold voltage of 0.2 V and an on-current.
Is V _G= 210μA / μm at -1.5V
It was On the other hand, the MOSFET of Comparative Example 2 has the same threshold voltage.
The on-current was 180 μA / μm. Note that off current
Was 2.5 nA / μm in each case. According to this result
Therefore, the effect of improving the on-current according to the present invention was confirmed.

[0056]

As described above, according to the present invention, since the channel impurity concentration n _A on the source region side is made higher than the channel impurity concentration n _B on the drain region side, the on-current is improved or the off-current is reduced. It can be reduced.
When the on-current is improved, the operating speed can be improved and the power consumption can be reduced. On the other hand, when the off current is reduced, standby power consumption, that is, power consumption when the transistor is not driven can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a structure of a semiconductor device of the present invention.

FIG. 2 is a diagram for explaining the structure of the semiconductor device of the present invention.

FIG. 3 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 8 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a diagram showing a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a diagram showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a diagram showing a form of a source / drain region having an extension structure.

[Explanation of symbols]

1 Silicon substrate 2 element isolation film 3 Gate oxide film 4 gate electrode 5 Impurity high concentration layer 6 Impurity high concentration layer 7 Sidewall 8 Source area 9 drain region 11 Resist mask 12 Phosphorus implantation area 14 BI pair 15 channel area 20 well area 21 Silicon introduction area 22 Arsenic

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/265 H01L 21/336

Claims (11)

(57) [Claims] 1. A step of introducing an impurity of one conductivity type into an element region of a silicon substrate, a step of forming a gate electrode on the element region via a gate insulating film, and a source of an opposite conductivity type to the impurity. Regions and drain regions sandwiching the gate electrode, ion implantation into the source regions to generate interstitial silicon, and heat treatment to diffuse the impurities together with the interstitial silicon into the channel region. A method of manufacturing a semiconductor device, comprising: 2. The acceleration voltage for ion implantation is 5 to 30 k.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed as eV. 3. The conductivity type of the impurity is a p-type, the manufacture of a semiconductor device according to claim 1 or 2, characterized in that the conductivity type of the source and drain regions are n-type Method. 4. The method of manufacturing a semiconductor device according to claim 3 , wherein the impurity is boron. 5. A step of introducing a p-type impurity into an element region of a silicon substrate, a step of forming a gate electrode on the element region via a gate insulating film, and sandwiching the gate electrode in the element region. Forming an n-type source region and a drain region in the source region, and Si, G in the source region.
e or ion implantation of a group V element, and 600 to
And a step of performing heat treatment at 800 ° C., the method for manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 5 , wherein the group V element is P or As. 7. The acceleration voltage for ion implantation is 5 to 30 k.
claim 5 or and performs as eV, the method of manufacturing a semiconductor device according to any have <br/> deviation of 6. 8. A process of introducing an n-type impurity into a device region of a silicon substrate, a process of forming a gate electrode on the device region via a gate insulating film, and a process of sandwiching the gate electrode in the device region. Forming a p-type source region and a drain region on the substrate, and Si, G
e or ion implantation of a Group III element, 600
A step of performing heat treatment at ˜800 ° C. 9. The method of manufacturing a semiconductor device according to claim 8 , wherein the group III element is In. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the n-type impurity is arsenic. 11. The ion implantation is performed at an acceleration voltage of 5 to 30.
The method for manufacturing a semiconductor device according to claim 8 , wherein the method is performed as keV.