JPH1012870A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep the suppression effect for channel field intensity in a micro MOS type transistor with conventional LDD(lightly doped drain) structure or LATID(large-angle-tilt implanted drain) structure and to increase drain saturation current. SOLUTION: A gate electrode 3 is formed on the main surface of a P type silicon substrate 1 with a gate insulation film 2 in between, and an N type lightly doped layer 4 is formed through large-angle-tilted ion implantation of arcenic in a manner that it may overlap both end parts of the gate electrode 3 sufficiently. Next, an N type first heavily doped layer 5 is formed through small-angle-tilt ion implantation of arcenic in a manner that it may be more shallow than the layer 4 and overlap both end parts of the electrode 3 slightly. Then, after a gate side-wall insulation film 6 is formed, a N type second heavily doped layer 7 constituting the main part of the source/drain area is formed through small-angle-tilted ion implantation of arcenic in a manner that it may be deeper than the layer 4 and may not overlap the electrode 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a MIS transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, demands for higher integration and higher performance of semiconductor devices by miniaturization of elements have been increasing. However, when a MOS transistor is miniaturized with a constant power supply voltage, an inconvenient phenomenon called a short channel effect or a hot carrier effect occurs due to a decrease in a gate length (channel length), and a serious obstacle occurs in transistor characteristics. It is known. That is, as the gate electric field intensity increases near the drain end in accordance with the decrease in the gate length, the threshold voltage fluctuates. Also, an increase in the channel electric field intensity near the drain end generates hot carriers. Hot carriers tend to be trapped in the gate oxide film near the drain end. As a result, variations in the threshold voltage and transconductance of the transistor are caused.

As one of measures to reduce the short channel effect and the hot carrier effect, an LDD (Lightly Doped Drain) is used.
The structure is known. FIG. 6 shows a conventional N-channel MOS transistor having an LDD structure. According to FIG. 6, a gate insulating film (oxide film) 2 is formed on a main surface of a P-type silicon (Si) substrate 1, and a gate electrode 3 made of polysilicon is formed on the gate insulating film 2. You. Then, a portion of the source / drain region is overlapped with both ends of the gate electrode 3 via the gate insulating film 2 by ion implantation of phosphorus (P) into the main surface of the substrate using the gate electrode 3 as a mask. N-type low concentration layer 4 constituting
Is formed. Next, the entire wafer is covered with an insulating film (oxide film) formed at a low temperature, and the insulating film is subjected to anisotropic dry etching, so that the gate sidewall insulating film (side surface) is formed on both sides of the gate electrode 3 on the main surface of the substrate. Wall spacer) 6
Is formed. Then, the arsenic (As) ions are implanted into the main surface of the substrate using the gate electrode 3 and the gate sidewall insulating film 6 as masks, so that the source is deeper than the low concentration layer 4 and does not overlap with the gate electrode 3. An N-type high concentration layer 7 that forms a main part of the drain region is formed. In other words, the drain region of the transistor of FIG. 6 is formed so as to overlap with both ends of the gate electrode 3 via the gate insulating film 2 so as not to overlap with the gate electrode 3. High concentration layer 7
And has a gentle slope of the impurity concentration formed.
Therefore, even if the gate length is reduced, the channel electric field intensity near the drain end is reduced, so that the short channel effect and the hot carrier effect are reduced.

Japanese Patent Application Laid-Open No. 6-13401 discloses LA
M with TID (Large-Angle-Tilt Implanted Drain) structure
An OS transistor is disclosed. According to the LATID structure, a low-concentration layer is formed so as to sufficiently overlap both ends of the gate electrode via the gate insulating film by ion implantation of the impurity using the gate electrode as a mask. Then, after forming the thin gate sidewall insulating film,
High-density ion implantation of impurities using the gate electrode and the gate sidewall insulating film as a mask, so as to be deeper than the low-concentration layer and to slightly overlap both ends of the gate electrode via the gate insulating film. A layer is formed. Also in this case, the presence of the low concentration layer reduces the channel electric field intensity.

[0005]

The above-mentioned LDD structure and LA
The TID structure has a problem that a high drain saturation current cannot be obtained because a low concentration layer for relaxing the channel electric field strength near the drain end is inserted as a parasitic resistance between the source and the drain.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having improved current drivability while maintaining a moderating effect of channel electric field intensity, and a method of manufacturing the same.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an ion implantation step for forming each of a low concentration layer and a high concentration layer. By adopting the process, it is shallower than the low concentration layer,
In addition, an additional high-concentration layer is formed at both ends of the gate electrode so as to overlap smaller than the low-concentration layer. Specifically, a semiconductor device according to the present invention includes a gate insulating film formed on a main surface of a first conductivity type semiconductor, a gate electrode formed on the gate insulating film, and a mask that masks the gate electrode. A low-concentration layer of the second conductivity type semiconductor formed so as to sufficiently overlap both ends of the gate electrode by the large-angle ion implantation, and a low-concentration layer formed by the small-angle ion implantation using the gate electrode as a mask. And a second shallow portion formed at both ends of the gate electrode so as to be smaller than the low-concentration layer.
A first high-concentration layer of a conductive type semiconductor, a gate sidewall insulating film formed on both sides of the gate electrode, and a deeper ion implantation using the gate electrode and the gate sidewall insulating film as masks; In addition, a configuration having a second high-concentration layer of a second conductivity type semiconductor formed so as not to overlap with the gate electrode is adopted.

According to the semiconductor device of the present invention, the low-concentration layer reduces the channel electric field intensity near the drain end. In addition, since the parasitic resistance between the source and the drain due to the low concentration layer is reduced by the first high concentration layer (additional high concentration layer), a high drain saturation current can be obtained.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, specific examples of the present invention will be described.
This will be described with reference to the drawings.

FIG. 1 shows an example of a method of manufacturing a semiconductor device according to the present invention in the order of steps. First, as shown in FIG. 1A, a 9-mm thick P-type silicon (Si) substrate
A gate insulating film (oxide film) 2 of nm is formed, and a gate electrode 3 made of polysilicon is formed on the gate insulating film 2. Then, the source / drain regions are sufficiently overlapped with both ends of the gate electrode 3 via the gate insulating film 2 by the large-angle ion implantation of the N-type impurity into the main surface of the substrate using the gate electrode 3 as a mask. Is formed, forming an N-type low concentration layer 4 which constitutes a part of. For example, the ion species is arsenic (As), the implantation energy is 80 keV, and P
The implantation tilt angle with respect to the normal direction of the main surface of the silicon substrate 1 is 25 °, and the implantation dose is 8.8 × 10 ¹² cm ⁻² (4
Direction). By such a large-tilt ion implantation of arsenic (As), the low-concentration layer 4 can be sufficiently overlapped with both ends of the gate electrode 3 via the gate insulating film 2 without a thermal diffusion step.

Subsequently, as shown in FIG. 1B, the gate electrode 3 is used as a mask to implant N-type impurities into the main surface of the substrate at a small inclination angle (10 ° or less) so as to be shallower than the low concentration layer 4. And an N-type first high-concentration layer 5 constituting another part of the source / drain region so as to overlap both ends of the gate electrode 3 via the gate insulating film 2 so as to be smaller than the low-concentration layer 4. To form For example, the ion species is arsenic (As), the implantation energy is 50 keV, and the first
The impurity concentration of the high concentration layer 5 is set to 5 × 10 ¹⁸ cm ⁻³ or more.

Next, as shown in FIG. 1C, a gate sidewall insulating film (sidewall spacer) 6 having a width of about 150 nm is formed on the main surface of the substrate on both sides of the gate electrode 3, and then the gate electrode 3 is formed. By implanting a small tilt angle (10 ° or less) of an N-type impurity into the main surface of the substrate using the mask 3 and the gate sidewall insulating film 6 as a mask, the N-type impurity is deeper than the low concentration layer 4 and does not overlap with the gate electrode 3. ,Source·
An N-type second high-concentration layer 7 constituting a main part of the drain region is formed. In forming the gate sidewall insulating film 6, the entire wafer is covered with an insulating film (oxide film or nitride film) formed at a low temperature, and the insulating film is subjected to anisotropic dry etching. At this time, TEOS [S
_{i (OC 2 H 5) 4} ] can be adopted SiO ₂ film was used. The ion species at the time of forming the second high concentration layer 7 is, for example, arsenic (As). The depth of the second high concentration layer 7 is, for example, 1
It is about 50 nm.

Through the above steps, an N-channel MOS transistor having a structure as shown in FIG. 2 is obtained. As shown in FIG. 3, the first high concentration layer 5 may have an impurity peak concentration at a deep position in the low concentration layer 4. In the above example, the low concentration layer 4 and the first high concentration layer 5
And the ion species of the N-type impurity implantation with the second high concentration layer 7 are as follows:
All are arsenic (As). A plurality of ionic species having no interdiffusion such as arsenic (As) and phosphorus (P) may be used.

According to the N-channel MOS transistors shown in FIGS. 2 and 3, even if the gate length is reduced, the channel electric field intensity near the drain end is reduced by the low concentration layer 4, resulting in a short channel effect and a hot carrier effect. Is reduced. In addition, since the parasitic resistance between the source and the drain due to the low concentration layer 4 is reduced by the first high concentration layer 5, a high drain saturation current can be obtained.

In the above example, an N-channel MOS transistor is formed on the main surface of the P-type silicon substrate 1, but a similar N-channel MOS transistor is formed on the P well.
A transistor may be formed. A similar process can be employed when forming a P-channel MOS transistor on the main surface of an N-type silicon substrate or on an N-well.
In the case of a CMOS semiconductor device, an N-channel MO
The width of the gate sidewall insulating film 6 for the S transistor and the width of the gate sidewall insulating film for the P-channel MOS transistor may be set to the same width. Arsenic (As) introduced as an impurity into an N-channel MOS transistor;
Although there is a difference in the diffusion rate between boron (B) introduced as an impurity in the P-channel MOS transistor, according to the above process, the diffusion rate between arsenic (As) and boron (B) is low. The difference does not cause a problem. Further, a substrate 1, a gate insulating film 2, a gate electrode 3
The material and dimensions of each of the gate sidewall insulating films 6 are not limited to the above examples. That is, the present invention is applicable to any MIS transistor.

FIG. 4 shows the threshold voltage with respect to the gate length of the N-channel MOS transistor when the dose of the small angle ion implantation (As additional implantation) for forming the first high concentration layer 5 is changed. Dependencies are shown. Here, in the large-angle ion implantation for forming the low concentration layer 4,
The ion species is arsenic (As) and the implantation energy is 80k
7. eV, the implantation tilt angle is 25 °, and the implantation dose is 8.
0 × 10 ¹² cm ⁻² (4 directions). In the small-angle ion implantation for forming the first high-concentration layer 5, the ion species is arsenic (As), the implantation energy is 50 keV,
The injection tilt angle was 7 °. The threshold voltage was measured under the condition that the gate width was 10 μm and the drain voltage was 3.3 V.
FIG. 4 shows that the dose of the additional As implantation is 0 to 2.5 × 10
^It can be seen that the gate length dependence of the threshold voltage does not change at all even if it changes in the range of ¹³ cm ^-2 (4 directions). That is, the first high-concentration layer 5 does not inhibit the reduction of the short channel effect by the low-concentration layer 4.

FIG. 5 shows the dependency of the drain saturation current of the N-channel MOS transistor on the dose of the small tilt ion implantation (As additional implantation) for forming the first high concentration layer 5. Here, in the large-angle ion implantation for forming the low-concentration layer 4, the ion species is arsenic (As), the implantation energy is 80 keV, and the implantation angle is 25.
° and an implantation dose of 8.8 × 10 ¹² cm ⁻² (4 directions). In the small-angle tilt ion implantation for forming the first high-concentration layer 5, the ion species was arsenic (As), the implantation energy was 50 keV, and the implantation tilt angle was 7 °.
The drain width was 10 μm, the gate length was 0.4 μm, and the drain saturation current was measured under the conditions of a drain voltage of 3.3 V and a gate voltage of 3.3 V. From FIG. 5, the dose amount is 1.4 ×
If the first high-concentration layer 5 is formed at 10 ¹³ cm ⁻² , the drain saturation current becomes 1 compared with the case where the first high-concentration layer 5 is not formed.
It turns out that it increases by 2%.

According to the present invention, the formation of the first high-concentration layer 5 can be carried out immediately after the formation of the low-concentration layer 4, so that the process is simplified and the increase in the process cost is minimized. . The impurity peak concentration of the first high concentration layer 5 may be set to 1 × 10 ¹⁹ cm ⁻³ or more. The dose of the small tilt ion implantation for forming the first high concentration layer 5 is:
It may be set to 1.0 × 10 ¹³ cm ⁻² or more.

[0019]

As described above, according to the present invention, in addition to the conventional ion implantation process for forming each of the low-concentration layer and the high-concentration layer, the gate electrode is shallower than the low-concentration layer and the gate electrode. An ion implantation process for forming an additional high-concentration layer is added to both ends of the layer so as to overlap smaller than the low-concentration layer, so that the effect of reducing the channel electric field strength by the low-concentration layer is maintained. Meanwhile, the current driving capability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a process chart showing an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration example of a semiconductor device according to the present invention.

FIG. 3 is a sectional view showing another configuration example of the semiconductor device according to the present invention.

FIG. 4 is a diagram showing that the first high-concentration layer does not inhibit reduction of the short-channel effect of the transistor in the semiconductor device according to the present invention.

FIG. 5 is a diagram showing that the first high-concentration layer increases the drain saturation current of the transistor in the semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view illustrating an example of a conventional semiconductor device having an LDD structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Gate insulating film 3 Gate electrode 4 N-type low concentration layer 5 N-type first high concentration layer 6 Gate side wall insulating film 7 N-type second high concentration layer

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Akio Miyajima 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Inventor Yoshiaki Kato 1-1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Inside the corporation

Claims (6)

[Claims] A gate insulating film formed on the main surface of the first conductivity type semiconductor; a gate electrode formed on the gate insulating film; and impurities on the main surface using the gate electrode as a mask. A low-concentration layer of the second conductivity type semiconductor formed so as to sufficiently overlap both ends of the gate electrode via the gate insulating film by the large-angle ion implantation, and using the gate electrode as a mask It is formed so as to be shallower than the low-concentration layer and to overlap with both ends of the gate electrode via the gate insulating film so as to be smaller than the low-concentration layer by small-angle ion implantation of impurities into the main surface. A first high-concentration layer of a second conductivity type semiconductor, a gate sidewall insulating film formed on the main surface on both sides of the gate electrode, and a gate electrode and the gate sidewall insulating film. And the small angle ion implantation of impurities into the main surface of the said low concentration deeper than layer, and the gate electrode and the second second conductivity type semiconductor formed so as not to overlap
A semiconductor device comprising a high concentration layer. 2. The semiconductor device according to claim 1, wherein a low concentration layer of the second conductivity type semiconductor, a first high concentration layer,
A semiconductor device, wherein the ion species of the impurity implantation for the second high concentration layer is the same as that of the second high concentration layer. 3. The semiconductor device according to claim 1, wherein said first conductivity type semiconductor is a P-type semiconductor, said second conductivity type semiconductor is an N-type semiconductor, and said second conductivity type semiconductor has a low concentration. A semiconductor device, wherein the ion species for impurity implantation of the layer, the first high-concentration layer, and the second high-concentration layer are all arsenic. 4. A step of forming a gate insulating film on the main surface of the first conductivity type semiconductor and forming a gate electrode on the gate insulating film, and forming the gate electrode on the main surface using the gate electrode as a mask. Forming a low-concentration layer of a second conductivity-type semiconductor so as to sufficiently overlap both ends of the gate electrode via the gate insulating film by ion implantation of a large angle of impurities; and The low-concentration ion implantation of impurities into the main surface is shallower than the low-concentration layer, and overlaps both ends of the gate electrode via the gate insulating film so as to be smaller than the low-concentration layer. Forming a first high-concentration layer of a two-conductivity type semiconductor; forming gate sidewall insulating films on the main surface on both sides of the gate electrode; the gate electrode and the gate sidewall The second high-concentration layer of the second conductivity type semiconductor is deeper than the low-concentration layer and is not overlapped with the gate electrode by small-angle ion implantation of impurities into the main surface using the edge film as a mask. Forming a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 4, wherein: a low concentration layer of the second conductivity type semiconductor; a first high concentration layer;
A method of manufacturing a semiconductor device, wherein the ion species of impurity implantation for the second high concentration layer is the same. 6. The method of manufacturing a semiconductor device according to claim 4, wherein said first conductivity type semiconductor is a P-type semiconductor, said second conductivity type semiconductor is an N-type semiconductor, and said second conductivity type semiconductor. A method of manufacturing a semiconductor device, wherein the ion species for impurity implantation of the low concentration layer, the first high concentration layer, and the second high concentration layer are all arsenic.