JP2507981B2 - Manufacturing method of complementary MIS transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a complementary MIS transistor. 2. Description of the Related Art At present, as miniaturization of MIS transistors progresses, it becomes more and more necessary to consider short channel effects and hot carrier effects. The short channel effect means, in particular, in a P-type channel MIS transistor,
Since the source and the drain become closer to each other as the device becomes finer, the potential of the channel part is affected by the drain voltage, and the threshold voltage and punch-through voltage are lowered. N-type channel MI
In the S-transistor, there are a phenomenon in which electrons flowing in the channel are scattered and injected in the direction of the gate, and a phenomenon in which electrons and holes generated due to weak yielding are injected.
The higher the drain voltage, the more likely it is to occur, and the maximum voltage that can be applied for a long time in a submicron device is determined by this hot carrier withstand voltage. Conventionally, regarding the hot carrier effect of both of the above, a low impurity density drain (hereinafter referred to as "LDD") structure as shown in FIG. 6 is adopted. In the figure, a P ⁻ type well region 2 formed in a semiconductor substrate 1 is shown.
The gate electrode 6 is formed on the surface of b via the gate insulating film 5, and the field insulating film 7 is formed in the element isolation region. Then, the gate electrode 6 and the field insulating film 7 are formed.
Is used as a mask to form an N ⁻ type diffusion layer 8 having a low impurity concentration, spacers 9 are provided on both sides (side walls) of the gate electrode 6, and the gate electrode 6, the spacer 9 and the field insulating film 7 are formed. Is used as a mask to perform ion implantation, and the impurity concentration is high and the bottom is N
N ⁺ type diffusion layer 10 diffusing deeper than the bottom of the ⁻ type diffusion layer 8.
To form. However, although the influence of the hot carrier effect in the N-type channel MIS transistor can be reduced in the above LDD structure, the spacer 9 is formed to form the N ⁺ -type diffusion layer 10. Since it is necessary to provide the spacers 9, it is technically difficult to control the formation of the spacers 9 and the number of manufacturing steps is increased. Furthermore, a P-channel MIS transistor and a N-channel MIS transistor such as CMOS are formed. When it is adopted as a complementary MIS transistor having the dual function, another consideration is required to reduce the influence of the short channel effect in the P-type channel MIS transistor. It is designed with a large area. Therefore, the present invention has been made in view of the above problems. In the complementary MIS transistor, a short channel effect can be obtained by simply increasing the number of manufacturing steps as compared with the conventional one without forming any spacer or the like. And hot
An object of the present invention is to provide a method of manufacturing a complementary MIS transistor that can reduce the influence of carrier effect at the same time. In order to achieve the above object, the present invention provides a step of forming an N type well region and a P type well region in a semiconductor substrate, the N type well region and the P type well region. Forming a first and a second gate electrode on each of the well regions via an insulating film; and implanting an impurity by using the first and second gate electrodes as a mask to form the first gate A first N-type diffusion layer, which has a higher concentration than the impurity concentration of the N-type well region, is formed on both ends of the electrode.
Simultaneously forming a second N-type diffusion layer having a concentration higher than that of the P-type well region at both ends of the gate electrode, and implanting impurities using the first gate electrode as a mask, Forming a P-type source / drain layer so as to be covered with the first N-type diffusion layer;
Impurities are implanted using the gate electrode of
And a step of forming N-type source / drain layers so as to be covered with the N-type diffusion layer. In the complementary MIS transistor formed as described above, in the P-type channel MIS transistor, the N-type diffusion layers of low impurity concentration are formed adjacent to the source / drain layers. Therefore, the carrier concentration on the surface of the N-type diffusion layer is increased by the voltage applied to the gate electrode, and the increase of parasitic resistance in the N-type diffusion layer is suppressed. Particularly when the gate voltage is higher than the drain voltage, the electric field from the gate electrode to the semiconductor substrate increases the carrier concentration on the surface of the N-type diffusion layer due to charge accumulation,
The parasitic resistance in the layer is reduced and the P-type channel MIS is reduced.
The current drive capability of the transistor is improved compared to the conventional LDD structure (FIG. 6) in which the N-type diffusion layer extends outside the gate. Further, since the end portions of the source / drain layer are formed below the gate electrode, carriers are generated by impact ionization in the drain portion to which a high electric field is applied, not at the bottom of the spacer of the conventional LDD structure, but at the gate. It will happen underneath the electrode. Therefore, in the conventional structure, the surface of the low impurity concentration layer is depleted by the carriers injected and trapped in the spacer to increase the parasitic resistance, but in the present invention, the gate insulation above the N-type impurity layer is increased. Even if carriers are trapped in the film, the N-type diffusion layer is less likely to be depleted by the electric field from the gate electrode, so that the parasitic resistance does not increase and the current driving capability of the transistor does not easily deteriorate. Since the N-type diffusion layer is formed at a concentration lower than the impurity concentration of the N-type diffusion layer, like the conventional LDD structure, the lateral spreading electric field between the source and the drain during voltage application is relaxed. can do. Furthermore, in the N-type channel MIS transistor, the N-type diffusion layer having an impurity concentration higher than that of the P-type well region is formed in the channel region near the edges of the source / drain layers.
It is considered to have a high concentration and acts to increase the absolute value of the threshold voltage. In addition, the elongation that occurs in the drain part can be reduced,
The punch through effect can be suppressed. Then, an N-type well is formed on the semiconductor substrate.
Since both P-type wells are formed, P-type channel
Required for a dual and N-type channel MIS transistor
The concentration of the N-type diffusion layer can be set within the same range. Yo
Thus, the N-type diffusion layer in the N-type channel MIS transistor is the N-type diffusion layer formed in the P-type channel MIS transistor.
It can be formed in the same process as the mold diffusion layer.
Ri, step by formation of the N-type diffusion layer in the N-type channel MIS transistor is not increased. The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 shows a cross-sectional view of an MIS transistor of one embodiment of the present invention. In the figure, a P-type channel MIS transistor (a) (hereinafter referred to as "P-MIS") and an N-type channel MIS transistor (b) (hereinafter referred to as "N-MIS") are shown, for example, complementary type such as CMOS. A circuit is available. In the figure, in a semiconductor substrate 1 made of Si or the like, an N ^- type well region 2a in which an N-type impurity such as phosphorus is deeply diffused is formed in a P-MIS, and a P-type impurity such as boron is deeply diffused in an N-MIS. The P ⁻ type well region 2b is formed. Polycrystalline Si is formed on the main surface of the P-MIS and N-MIS semiconductor substrate 1 via a gate insulating film 5 made of a Si oxide film, a Si nitride film, or a combination thereof.
The gate electrode 6 made of a conductive layer such as Ti or Mo is partially formed. Further, a field insulating film 7 which is an element isolation region made of a Si oxide film or the like is formed in a region where each MIS transistor is isolated on the surface of the semiconductor substrate 1. still,
The element isolation region may be formed by etching the surface of the semiconductor substrate 1 to form a groove and then burying a Si oxide film, polycrystalline Si, or the like. [0012] Then, P-MIS and N-MIS
At the same time, using the gate electrode 6 and the field insulating film 7 as a mask, N-type impurities such as phosphorus are added in the concentration C in this embodiment.
_N is ion-implanted in a range of 3 to 30 times the impurity concentration C _N ⁻ and C _P ⁻ of the N ⁻ type well region 2a and the P ⁻ type well region 2b, and then an appropriate heat treatment is performed to obtain N. The type diffusion layer 4 is formed on each. At this time, the N-type diffusion layer 4 is formed so as to be covered with the gate electrode 6 in consideration of miniaturization of the element. Thereafter, the gate electrode 6 and the field insulating film 7 are formed in the same manner as the N-type diffusion layer 4 by a normal CMOS manufacturing process.
Using as a mask, P-MIS is ion-implanted with a P-type impurity such as boron, and the first P ⁺ -type diffusion layer 3a is electrically connected to the source electrode in each N-type diffusion layer 4 on both sides of the gate electrode 6. ₁ and a second P ⁺ electrically connected to the drain electrode
The type diffusion layers 3a ₂ are formed respectively. Further, N-MIS is ion-implanted with N-type impurities such as phosphorus and arsenic, and similarly, first N ⁺ -type diffusions are electrically connected to the source electrodes in the respective N-type diffusion layers 4 on both sides of the gate electrode 6. A second N ⁺ type diffusion layer 3b ₂ is formed, which is electrically connected to the layer 3b ₁ and the drain electrode. Here, the impurity concentration of the P ⁺ type diffusion layer 3a and the N ⁺ type diffusion layer 3b is higher than that of the N type diffusion layer 4, and both of them diffuse shallower than the N type diffusion layer 4, and thus N The width is narrower than that of the mold diffusion layer 4.
Furthermore, the P ⁺ -type diffusion layer 3a, the N ⁺ -type diffusion layer 3b, and the N-type diffusion layer 4 may be formed in the reverse order to the above. Next, it will be described that the characteristics of the MIS transistor are improved by the above configuration. First, P-MIS
In the above, since the N-type diffusion layer 4 increases the impurity concentration of the channel region aa near the edge of the P ⁺ -type diffusion layer 3a, the threshold voltage V of the MIS transistor is increased.
The absolute value of the _T | V _T | acts to enhance. This action increases the absolute value | V _T | for devices having shorter gate lengths. On the other hand, the absolute value | V _T | decreases as the gate length becomes shorter due to the short channel effect.
V _T | can be made almost constant without being influenced by the gate length, and the influence of the short channel effect can be reduced. This situation will be described with reference to the relationship diagram between the gate length and the threshold voltage V _T shown in FIG. In the figure, the solid line c is the N-type diffusion layer 4
There is no characteristic, and the solid line d is the characteristic of this embodiment. According to the present embodiment, the threshold voltage V _T is substantially constant at a gate length of 0.8 μm or more, and it can be seen that it can be effectively used in a MIS transistor having a short gate length, that is, a miniaturized MIS transistor. .
In the present invention, if the impurity concentration C _N of the N type diffusion layer 4 is higher than the impurity concentration C _N ⁻ of the N ⁻ type well region 2a, the effect can be obtained to some extent.
If the range is doubled, the effect can be clearly obtained.
Excellent characteristics are obtained in the range of 5 to 20 times, and the above-mentioned solid line d is in this range. The dotted lines e and f show the characteristics when the impurity concentration C _N is less than 3 times and more than 30 times the impurity concentration C _N ⁻ , respectively. 3 times and 30 times that in FIG. 3 are the solid line c shown in FIG. 3, that is, the fluctuation rate is smaller than the threshold fluctuation rate with respect to the gate length change in the conventional structure in which the N-type diffusion layer 4 does not exist. It shows the range. Therefore, if it is within this range, it can be suppressed to be smaller than the threshold variation in the conventional structure, so that the short channel effect can be suppressed even in the case where the N-type diffusion layer 4 exists under the gate electrode 6. In addition, it is possible to provide a P-type channel MIS transistor having a high yield even with respect to process variations in gate length. Further, as shown in the impurity concentration distribution diagram of the AA sectional view in FIG. 1 of FIG. 3, the junction depth Xj due to the N-type diffusion layer 4 is the junction depth Xj even though there is no N-type diffusion layer 4.
Effectively shallower than j '. Therefore, the gate length can be effectively lengthened, and the influence of the short channel effect can be reduced. Further, as another effect, the depletion layer generated between the N-type diffusion layer 4 and the P ⁺ -type diffusion layer 3a can be suppressed from spreading because the N-type diffusion layer 4 has a relatively high concentration. Furthermore, the punch-through breakdown voltage can be improved. Next, in the N-MIS, as shown in the impurity concentration distribution diagram of the B-B sectional view in FIG. 1 of FIG.
By forming the N-type diffusion layer 4 between the N ⁺ -type diffusion layer 3b and the P ⁻ -type well region 2b, the impurity concentration distribution in the drain portion becomes gentler as compared with that without the N-type diffusion layer 4. Become. As a result, the electric field concentration at the drain portion is alleviated, and the hot carrier effect can be reduced. In addition, PM
On the contrary, in IS, hot carriers slightly increase, but P-
MIS originally has a few orders of magnitude smaller hot carrier generation than N-MIS, so there is no problem at all. FIG. 5 shows a sectional view of another embodiment of the present invention. The figure shows a higher breakdown voltage N-MIS, and other N-MIS and P-MIS may be the same as those in the above-mentioned embodiment, and they are formed at the same time as the N-MIS in this embodiment. In the figure, the structure up to the N-type diffusion layer 4 is the same as that of the above-mentioned embodiment, and the same components are designated by the same reference numerals and the description thereof is omitted. In this embodiment, the side of the gate electrode 6 on the drain region or both the source and drain regions (the latter in the figure) is covered with photoresist or the like and then N of arsenic or the like is applied.
Type impurities are ion-implanted under the same conditions as in the above embodiment,
The N ⁺ type diffusion layer 3b ₁ and the second N ⁺ type diffusion layer 3b ₂ are formed. According to this embodiment, N in the channel region
Since the width of the type diffusion layer 4 becomes wider, the N-MIS has a higher breakdown voltage.
Can be provided. As described above, according to the present invention, the semiconductor
By forming both wells on the body substrate, a P-type channel
And required for N-channel MIS transistor
Since the concentration of the N-type diffusion layer can be set within the same range,
The N-type diffusion layer can be formed in the source / drain regions of P-MIS and N-MIS in the same step.
Therefore , the manufacturing method is increased by one step compared to the conventional complementary MIS transistor, and the influence of the short channel effect and the hot carrier effect, which is very problematic in the miniaturization of the element without forming any spacer or the like. At the same time
It has an excellent effect that a complementary MIS transistor that can be reliably reduced can be manufactured.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a MIS transistor of an embodiment of the present invention. FIG. 2 is a relationship diagram between a gate length and a threshold voltage V _T. FIG. 3 is an impurity concentration distribution diagram of the AA cross-sectional view in FIG. FIG. 4 is an impurity concentration distribution diagram of a B-B cross-sectional view in FIG. 1. FIG. 5 is a cross-sectional view of a MIS transistor of another embodiment of the present invention. FIG. 6 is a cross-sectional view of a prior art LDD structure. [Description of Reference Signs] 1 semiconductor substrate 2a N ⁻ type well region 2b P ⁻ type well region 3a P ⁺ type diffusion layer 3b N ⁺ type diffusion layer 4 N type diffusion layer 5 gate insulating film 6 gate electrode

   ────────────────────────────────────────────────── ─── Continued front page    (56) References JP-A-57-192063 (JP, A)                 JP-A-56-26471 (JP, A)                 JP-A-60-124965 (JP, A)

Claims (1)

(57) [Claims] (1) A step of forming an N-type well region and a P-type well region in a semiconductor substrate, and an insulating film on each of the N-type well region and the P-type well region. Forming first and second gate electrodes, and implanting impurities using the first and second gate electrodes as a mask to remove impurities in the N-type well region at both ends of the first gate electrode. A first N-type diffusion layer having a higher concentration than that of the second gate electrode and a second N-type diffusion layer having a higher concentration than the impurity concentration of the P-type well region are simultaneously formed on both ends of the second gate electrode. And a step of implanting impurities using the first gate electrode as a mask ,
Forming a P-type source / drain layer so as to be covered with the first N-type diffusion layer , and implanting an impurity using the second gate electrode as a mask ,
And a step of forming an N-type source / drain layer so as to be covered with the second N-type diffusion layer , the method of manufacturing a complementary MIS transistor. (2) The complementary MIS according to claim 1, wherein the first and second N-type diffusion layers are formed with a concentration 3 to 30 times higher than the impurity concentration of the N-type well region. Manufacturing method of transistor. (3) The complementary MIS according to claim 1, wherein the first and second N-type diffusion layers are formed with a concentration 15 to 20 times higher than an impurity concentration of the N-type well region. Manufacturing method of transistor.