JPH0234936A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0234936A JPH0234936A JP18371788A JP18371788A JPH0234936A JP H0234936 A JPH0234936 A JP H0234936A JP 18371788 A JP18371788 A JP 18371788A JP 18371788 A JP18371788 A JP 18371788A JP H0234936 A JPH0234936 A JP H0234936A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- drain
- semiconductor substrate
- source
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 230000007423 decrease Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000002513 implantation Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、高密度、高速化、高信頼性を備えた半導体装
置およびその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device with high density, high speed, and high reliability, and a method for manufacturing the same.
（従来の技術）
半導体集積回路の高集積化に伴い、それを構成している
Ｍ ＯＳ （Ｍｅｔａｌ−Ｏｘｉｄｅ−３ｅｍｉｃｏｎ
ｄｕｃｔｏｒ） トランジスタの微細化が進められてい
る。しかし、電源電圧は、素子が微細化されても外部回
路との関係上、低電圧化されそうにない。電源電圧を下
げずに微細化したＭＯＳトランジスタでは、ゲート長、
ゲート酸化膜厚、ソース・ドレイン接合深さの縮小化と
、チャネル部分の不純物濃度の増大によって素子内部と
電界強度は上昇し、特にドレイン拡散層近傍に高電界領
域を形成する。この高電界領域に流れ込むチャネル電子
は、電界により高エネルギーを得、衝突電離を起こし、
多数の電子正孔対が生成される。この生成された高エネ
ルギーを持つホット・エレクトロンの一部は、ゲート酸
化膜中に注入され、その一部がゲート酸化膜中にトラッ
プされる。ＭＯＳトランジスタでゲート酸化膜中に負電
荷が蓄積されると、閾値電圧が相互コンダクタンスが変
化し、回路の安定動作を損ない、性能の低下を招く。(Prior Art) As semiconductor integrated circuits become more highly integrated, the MOS (Metal-Oxide-3emiconductor
(ductor) The miniaturization of transistors is progressing. However, even if the elements are miniaturized, the power supply voltage is unlikely to be lowered due to the relationship with external circuits. In MOS transistors that are miniaturized without lowering the power supply voltage, the gate length,
As the gate oxide film thickness and source/drain junction depth decrease, and the impurity concentration in the channel portion increases, the electric field strength inside the device increases, forming a high electric field region especially near the drain diffusion layer. Channel electrons flowing into this high electric field region gain high energy due to the electric field and cause impact ionization.
A large number of electron-hole pairs are generated. Some of the generated hot electrons with high energy are injected into the gate oxide film, and some of them are trapped in the gate oxide film. When negative charges are accumulated in the gate oxide film of a MOS transistor, the threshold voltage and mutual conductance change, impairing the stable operation of the circuit and causing a decrease in performance.
このＭＯ３Ｉ−ランジスタのホット・キャリアに対する
欠点を緩和する方法として、ＬＤＤ（ＬｉＨｈｔｌｙ
Ｄｏｐｅｄ Ｄｒａｉｎ）と呼ばれる構造が検討されて
いる。この構造を有する半導体装置の断面図を第４図に
示す。同図において、２１はＳｉ基板、２２はゲート酸
化膜、２３はゲート電極、２４はＳｉＯ２膜、２５はゲ
ート電極２３をマスクとする不純物注入による低濃度不
純物領域、２６はゲート側壁Ｓｕｎ、、２７はゲート側
！２６を有するゲート電極をマスクとした不純物注入に
より形成される高濃度不純物領域で、ソース／ドレイン
である。このように、ドレイン２７の端部に低不純物濃
度領域２５を設け、ドレイン端部における不純物濃度を
緩やかにすることにより、ドレイン近傍での高電界の集
中を抑制する。As a method to alleviate the disadvantage of MO3I-transistors against hot carriers, LDD (LiHtly
A structure called a doped drain is being studied. A cross-sectional view of a semiconductor device having this structure is shown in FIG. In the figure, 21 is a Si substrate, 22 is a gate oxide film, 23 is a gate electrode, 24 is an SiO2 film, 25 is a low concentration impurity region formed by impurity implantation using the gate electrode 23 as a mask, 26 is a gate sidewall Sun, 27 is on the gate side! This is a high concentration impurity region formed by impurity implantation using the gate electrode 26 as a mask, and is a source/drain region. In this way, by providing the low impurity concentration region 25 at the end of the drain 27 and making the impurity concentration at the drain end moderate, concentration of a high electric field near the drain is suppressed.
このＬＤＤ構造とすることにより、ホット・キャリアの
問題点を緩和し、ドレイン耐圧に対する高信頼性が得ら
れる。By adopting this LDD structure, the problem of hot carriers can be alleviated and high reliability with respect to drain breakdown voltage can be obtained.
（発明が解決しようとする課題）
上記ＬＤＤ構造の半導体装置においては、低不純物濃度
領域の抵抗が高くなるため、トランジスタの相互コンダ
クタンスが低くなり、電流駆動能力および動作速度が低
下する欠点があった。(Problems to be Solved by the Invention) In the semiconductor device with the above-mentioned LDD structure, the resistance of the low impurity concentration region increases, so the mutual conductance of the transistor decreases, resulting in a decrease in current drive ability and operating speed. .
本発明の目的は、従来の欠点を解消し、短チャネルのＭ
ｏｓ＋〜ランジスタにおいても、相互コンダクタンス等
の基本特性をできるだけ損なわないで、ホット・キャリ
アに対する耐性を向上させることができるＭＯＳトラン
ジスタを提供することである。The object of the present invention is to overcome the drawbacks of the prior art and to
It is an object of the present invention to provide a MOS transistor that can improve resistance to hot carriers without impairing basic characteristics such as mutual conductance as much as possible even in os+ transistors.
（課題を解決するための手段）
本発明の半導体装置およびその製造方法は、半導体基板
表面に形成されたゲート絶縁膜上に、チャネル長方向に
対して両端に異なる仕事函数を有するゲート電極を形成
し、このゲート電極をマスクとして半導体基板にイオン
注入を行ない、ソースおよびドレインを形成するもので
ある。(Means for Solving the Problems) A semiconductor device and a method for manufacturing the same according to the present invention form gate electrodes having different work functions at both ends in the channel length direction on a gate insulating film formed on the surface of a semiconductor substrate. Then, using this gate electrode as a mask, ions are implanted into the semiconductor substrate to form a source and a drain.
（作 用）
本発明の構成により、ＬＤＤ構造において、高抵抗の低
不純物濃度領域をゲート電極の仕事函数を変えてやるこ
とにより１局所的に反転層を形成し易くすることができ
、相互コンダクタンスの低下を防ぐことができる。(Function) According to the configuration of the present invention, in the LDD structure, by changing the work function of the gate electrode in the high resistance low impurity concentration region, it is possible to easily form an inversion layer locally, and the mutual conductance can be reduced. can prevent a decline in
（実施例）
本発明の実施例を第１図ないし第３図に基づいて説明す
る。(Example) An example of the present invention will be described based on FIGS. 1 to 3.
第１図は本発明の実施例における半導体装置を示すもの
で、ｎチャネル型ＭＯＳトランジスタに関するものであ
る。第２図は、第１図の実施例の製造方法を説明するた
めの工程断面図である。FIG. 1 shows a semiconductor device according to an embodiment of the present invention, and relates to an n-channel MOS transistor. FIG. 2 is a process sectional view for explaining the manufacturing method of the embodiment shown in FIG.
まず、第２図（ａ）に示すように、ｐ型シリコン半導体
基板１にゲート絶縁膜２を形成したのち、ゲート電極３
を形成する。ここで、ゲート電極３はＷを用いる。First, as shown in FIG. 2(a), a gate insulating film 2 is formed on a p-type silicon semiconductor substrate 1, and then a gate electrode 3 is formed on a p-type silicon semiconductor substrate 1.
form. Here, W is used for the gate electrode 3.
次に、ｎ型ポリシリコン膜４を形成したのち〔第２図（
ｂ）〕、反応性イオンエツチング（ＲＩＥ）によりｎ型
ポリシリコン膜４を異方性エツチングし、平坦部に形成
されたｎ型ポリシリコン膜を除去する。この工程により
、ゲート電極３の周辺部のｎ型ポリシリコン膜だけが残
り、ｎ型ポリシリコン膜４の一部による側壁が形成され
る〔第２図（Ｃ）〕。Next, after forming an n-type polysilicon film 4 [Fig.
b)] The n-type polysilicon film 4 is anisotropically etched by reactive ion etching (RIE) to remove the n-type polysilicon film formed on the flat portion. Through this step, only the n-type polysilicon film at the peripheral portion of the gate electrode 3 remains, and a side wall is formed by a part of the n-type polysilicon film 4 [FIG. 2(C)].
次に、ゲート電極３をマスクとしてイオン注入を行ない
、第１のソース領域５ｓ、 ドレイン領域５ｄを形成す
る〔第２図（ｄ）〕。ここで、不純物として燐を用い、
打込みエネルギーを小さくし、ドース量も低濃度に抑え
である。Next, ion implantation is performed using the gate electrode 3 as a mask to form a first source region 5s and a drain region 5d [FIG. 2(d)]. Here, using phosphorus as an impurity,
The implantation energy can be reduced and the dose can be kept to a low concentration.
次に、ＣＶＤ ５１０２膜を形成したのち、ＲＩＥに
より前記ＣＶＤ ５１０２膜を異方性エツチングし、
平坦部に形成された前記ＣＶ Ｄ−３ｉｎ、膜を除去す
る。この工程により、ゲート電極３の周辺部のＣＶＤ−
３ｊ。０２膜だけが残す、ＣＶＤ ５ｉ０２Ｂ（１）
一部による絶縁膜側壁６が形成される〔第２図（ｅ）
〕。Next, after forming a CVD 5102 film, the CVD 5102 film is anisotropically etched by RIE,
The CV D-3in film formed on the flat portion is removed. Through this step, the CVD-
3j. Only 02 film remains, CVD 5i02B (1)
An insulating film side wall 6 is formed by a portion [FIG. 2(e)]
].
次に１本来のソースおよびドレイン領域を形成するため
に、砒素のイオン注入を行ない、第２のソース領域７ｓ
、ドレイン領域７ｄを形成する〔第２図（ｆ）〕。Next, in order to form the original source and drain regions, arsenic ions are implanted, and a second source region 7s is formed.
, to form a drain region 7d [FIG. 2(f)].
最後に、熱処理を行ない、第１図に示すようなＬＤＤ構
造で、かつゲート電極がソースおよびドレインの端部で
仕事函数が小さくなっているようなｎチャネル型ＭＯＳ
トランジスタを形成する。Finally, heat treatment is performed to create an n-channel MOS that has an LDD structure as shown in Figure 1, and in which the gate electrode has a small work function at the ends of the source and drain.
Form a transistor.
本実施例において、ゲート電極はＷとｎ０ポリシリコン
で構成されており、仕事函数はそれぞれ４．５５．３．
９５（ｅＶ）である。このため、ソース・ドレインの低
不純物濃度領域は、チャネル中央部より反転層が形成し
易くなっており、相互コンダクタンスの低下を防いでい
る。このような構造を形成する際に、新たなマスクを追
加する必要もなく、容易に形成することができる。In this example, the gate electrode is made of W and n0 polysilicon, and the work functions are 4.55.3.
95 (eV). Therefore, an inversion layer is more easily formed in the low impurity concentration regions of the source and drain than in the center of the channel, thereby preventing a decrease in mutual conductance. When forming such a structure, there is no need to add a new mask, and the structure can be easily formed.
第３図は、本発明の第２の実施例の製造方法を説明する
ための工程断面図である。FIG. 3 is a process sectional view for explaining the manufacturing method of the second embodiment of the present invention.
まず、第３図（ａ）に示すように、ｐ型シリコン半導体
基板１にゲート絶縁膜２を形成したのち、ゲート電極を
Ｗで形成する。First, as shown in FIG. 3(a), a gate insulating film 2 is formed on a p-type silicon semiconductor substrate 1, and then a gate electrode is formed of W.
次に、ゲート電極３をマスクとして燐を低濃度にイオン
注入し、第１のソース領域５ｓ、ドレイン領域５ｄを形
成する〔第３図（ｂ）〕。Next, using the gate electrode 3 as a mask, phosphorus is ion-implanted at a low concentration to form a first source region 5s and a drain region 5d [FIG. 3(b)].
次に、ｎ型ポリシリコン膜４を形成したのち〔第３図（
ｃ））、反応性イオンエツチング（ＲＩＥ）によりｎ型
ポリシリコン膜４を異方性エツチングし、平坦部に形成
されたｎ型ポリシリコン膜を除去し、ゲート電極３の周
辺部にｎ型ポリシリコン膜４の一部による絶縁膜側壁６
が形成される〔第３図（ｄ）〕。Next, after forming an n-type polysilicon film 4 [Fig.
c)) The n-type polysilicon film 4 is anisotropically etched by reactive ion etching (RIE), the n-type polysilicon film formed on the flat part is removed, and the n-type polysilicon film is etched around the gate electrode 3. Insulating film sidewall 6 formed by part of silicon film 4
is formed [Fig. 3(d)].
次に、本来のソースおよびドレイン領域を形成するため
に、ゲート電極３をマスクとして砒素のイオン注入を行
ない、第２のソース領域７ｓ、ドレイン領域７ｄを形成
する。Next, in order to form the original source and drain regions, arsenic ions are implanted using the gate electrode 3 as a mask to form the second source region 7s and drain region 7d.
最後に、熱処理を行ない、第１図に示すような構造のｎ
チャネル型ＭＯＳトランジスタを形成する。Finally, heat treatment is performed to form the structure shown in Figure 1.
A channel type MOS transistor is formed.
本実施例では、第１の実施例に比べて少ない工程で同様
の構造を得ることができる。In this embodiment, a similar structure can be obtained with fewer steps than in the first embodiment.
上記実施例においては、ゲート電極としてＷとｎ０ポリ
シリコンを用いたが、他の材料でもよい。In the above embodiment, W and n0 polysilicon were used as the gate electrode, but other materials may be used.
ｎチャネル型ＭＯＳトランジスタにおいては、ゲート電
極の仕事函数がチャネル中央部で高く、両端で低くなる
ように構成されていればよい。In an n-channel MOS transistor, the work function of the gate electrode may be high at the center of the channel and low at both ends.
（発明の効果）
本発明によれば、ゲート電極をチャネル長方向に対して
両端に異なる仕事函数を有して形成することにより、Ｍ
ＯＳトランジスタについて素子の性能を損なうことなく
、ホット・キャリアに対する耐性を向上させ、ドレイン
耐圧に対する高信頼性を得ることができる。また、ゲー
ト電極の形成においては、自己整合型にできるので容易
に作製することができ、その実用上の効果は大である。(Effects of the Invention) According to the present invention, by forming the gate electrode with different work functions at both ends in the channel length direction, M
With respect to an OS transistor, resistance to hot carriers can be improved and high reliability with respect to drain breakdown voltage can be obtained without impairing element performance. Furthermore, since the gate electrode can be formed in a self-aligned manner, it can be easily manufactured, and its practical effects are great.
第１図は本発明における第１の実施例の半導体装置の断
面図、第２図は同製造方法を示す工程図、第３図は本発
明の第２の実施例の半導体装置の製造方法を示す工程図
、第４図は従来の半導体装置の断面図である。
１・・・ｐ型シリコン半導体基板、 ２・・・ゲート絶
縁膜、 ３・・・ゲート電極、 ４・・・ｎ型ポリシリ
コン膜、 ５Ｓ・・・第１のソース領域、 ５ｄ、 ７
ｄ・・・ドレイン領域、 ６・・・絶縁膜側壁、 ７
ｓ・・・第２のソース領域。
第
図
３ゲート電越
第
図
第
図
第
図
第
図
第
図
２乙FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a process diagram showing the manufacturing method thereof, and FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The process diagram shown in FIG. 4 is a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon semiconductor substrate, 2... Gate insulating film, 3... Gate electrode, 4... N-type polysilicon film, 5S... First source region, 5d, 7
d...Drain region, 6...Insulating film side wall, 7
s...Second source area. Figure 3 Gate Electric Etsu Figure Figure 2
Claims (5)
る部分に形成されたゲート絶縁膜と、前記ゲート絶縁膜
の上にゲート電極を有し、前記ゲート電極は、チャネル
長方向に対して両端に異なる仕事函数を有して形成され
ていることを特徴とする半導体装置。(1) A gate insulating film formed on a portion of the surface of the semiconductor substrate that will become a MOS transistor region, and a gate electrode on the gate insulating film, the gate electrodes being different at both ends in the channel length direction. A semiconductor device characterized in that it is formed to have a work function.
低不純物濃度領域を有する請求項（１）記載の半導体装
置。(2) The semiconductor device according to claim (1), further comprising a low impurity concentration region at the channel side end of the source and drain regions.
る部分に形成されたゲート絶縁膜上に、チャネル長方向
に対して両端に異なる仕事函数を有するゲート電極を形
成する工程と、前記ゲート電極をマスクとして前記半導
体基板表面にイオン注入を行ない、ソースおよびドレイ
ン領域を形成する工程を含む請求項（１）記載の半導体
装置の製造方法。(3) Forming a gate electrode having a different work function at both ends in the channel length direction on the gate insulating film formed on the portion of the surface of the semiconductor substrate that will become the MOS transistor region, and masking the gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of implanting ions into the surface of the semiconductor substrate to form source and drain regions.
と、前記ゲート電極の周辺部に絶縁膜側壁を形成する工
程と、前記ゲート電極および前記絶縁膜側壁をマスクと
して前記半導体基板表面にイオン注入を行ない、第２の
ソースおよびドレインを形成する工程を含む請求項（１
）記載の半導体装置の製造方法。(4) forming a first source and drain region, forming an insulating film sidewall around the gate electrode, and implanting ions into the semiconductor substrate surface using the gate electrode and the insulating film sidewall as a mask; Claim 1, further comprising the step of forming a second source and a drain by forming a second source and a drain.
) A method for manufacturing a semiconductor device according to the method.
表面にイオン注入を行ない、第１のソースおよびドレイ
ンを形成する工程と、前記第１のゲート電極の周辺部側
壁に仕事函数の異なる第２のゲート電極を形成する工程
と、前記第１、第２のゲート電極をマスクとして前記半
導体基板表面にイオン注入を行ない、第２のソースおよ
びドレインを形成する工程を含む請求項（１）記載の半
導体装置の製造方法。(5) implanting ions into the surface of the semiconductor substrate using the first gate electrode as a mask to form a first source and drain; 2. The method according to claim 1, further comprising the step of forming a gate electrode, and performing ion implantation into the surface of the semiconductor substrate using the first and second gate electrodes as masks to form a second source and drain. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18371788A JPH0234936A (en) | 1988-07-25 | 1988-07-25 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18371788A JPH0234936A (en) | 1988-07-25 | 1988-07-25 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0234936A true JPH0234936A (en) | 1990-02-05 |
Family
ID=16140727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18371788A Pending JPH0234936A (en) | 1988-07-25 | 1988-07-25 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0234936A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59118737A (en) * | 1982-12-27 | 1984-07-09 | Sumitomo Chem Co Ltd | L-4-cyclopentenone ester |
| JPH02116171A (en) * | 1988-10-25 | 1990-04-27 | Nec Corp | Manufacture of mos transistor |
| US5306655A (en) * | 1990-07-24 | 1994-04-26 | Matsushita Electric Industrial Co., Ltd. | Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions |
| US5426327A (en) * | 1990-10-05 | 1995-06-20 | Nippon Steel Corporation | MOS semiconductor with LDD structure having gate electrode and side spacers of polysilicon with different impurity concentrations |
| US5466958A (en) * | 1992-10-30 | 1995-11-14 | Kabushiki Kaisha Toshiba | MOS-type semiconductor device having electrode structure capable of coping with short-channel effect and manufacturing method thereof |
| EP0856892A2 (en) * | 1997-01-30 | 1998-08-05 | Oki Electric Industry Co., Ltd. | MOSFET and manufacturing method thereof |
| WO2009063582A1 (en) * | 2007-11-15 | 2009-05-22 | Panasonic Corporation | Semiconductor device and method for manufacturing the same |
-
1988
- 1988-07-25 JP JP18371788A patent/JPH0234936A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59118737A (en) * | 1982-12-27 | 1984-07-09 | Sumitomo Chem Co Ltd | L-4-cyclopentenone ester |
| JPH02116171A (en) * | 1988-10-25 | 1990-04-27 | Nec Corp | Manufacture of mos transistor |
| US5306655A (en) * | 1990-07-24 | 1994-04-26 | Matsushita Electric Industrial Co., Ltd. | Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions |
| US5405787A (en) * | 1990-07-24 | 1995-04-11 | Matsushita Electric Industrial Co., Ltd. | Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions |
| US5426327A (en) * | 1990-10-05 | 1995-06-20 | Nippon Steel Corporation | MOS semiconductor with LDD structure having gate electrode and side spacers of polysilicon with different impurity concentrations |
| US5466958A (en) * | 1992-10-30 | 1995-11-14 | Kabushiki Kaisha Toshiba | MOS-type semiconductor device having electrode structure capable of coping with short-channel effect and manufacturing method thereof |
| US5756365A (en) * | 1992-10-30 | 1998-05-26 | Kabushiki Kaisha Toshiba | Method of manufacturing MOS-type semiconductor device having electrode structure capable of coping with short-channel effects |
| EP0856892A2 (en) * | 1997-01-30 | 1998-08-05 | Oki Electric Industry Co., Ltd. | MOSFET and manufacturing method thereof |
| EP0856892A3 (en) * | 1997-01-30 | 1999-07-14 | Oki Electric Industry Co., Ltd. | MOSFET and manufacturing method thereof |
| WO2009063582A1 (en) * | 2007-11-15 | 2009-05-22 | Panasonic Corporation | Semiconductor device and method for manufacturing the same |
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