JPH0234936A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH0234936A
JPH0234936A JP18371788A JP18371788A JPH0234936A JP H0234936 A JPH0234936 A JP H0234936A JP 18371788 A JP18371788 A JP 18371788A JP 18371788 A JP18371788 A JP 18371788A JP H0234936 A JPH0234936 A JP H0234936A
Authority
JP
Japan
Prior art keywords
gate electrode
drain
semiconductor substrate
source
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18371788A
Other languages
Japanese (ja)
Inventor
Yohei Ichikawa
洋平 市川
Masanori Fukumoto
正紀 福本
Mitsuo Yasuhira
光雄 安平
Toshiki Yabu
藪 俊樹
Yoshiyuki Iwata
岩田 栄之
Kazuhiro Matsuyama
和弘 松山
Takatoshi Yasui
安井 孝俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18371788A priority Critical patent/JPH0234936A/en
Publication of JPH0234936A publication Critical patent/JPH0234936A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To seek to improve the resistance to hot carriers without spoiling performance of an element respecting MOS transistor by so forming a gate electrode as to have different work functions at both ends to the longitudinal direction of a channel. CONSTITUTION:A gate electrode 3 having different work functions at both end to the longitudinal direction of a channel is formed on a gate insulating film 2 formed at the surface of a semiconductor substrate 1, and with this gate electrode 3 as a mask ions are implanted into the semiconductor substrate 1 so as to form sources 7s and 5s and drains 5d and 7d. In the Lightly Doped Drain(LDD) structure by this constitution, the low impurity concentration region with high resistance can be made easy to partially form an inversion layer by changing the work function of the gate electrode 3, and the lowering of mutual conductance can be prevented. Hereby, the resistance to hot carriers can be improved without spoiling the performance of an element respecting a MOS transistor.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、高密度、高速化、高信頼性を備えた半導体装
置およびその製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device with high density, high speed, and high reliability, and a method for manufacturing the same.

(従来の技術) 半導体集積回路の高集積化に伴い、それを構成している
M OS (Metal−Oxide−3emicon
ductor) トランジスタの微細化が進められてい
る。しかし、電源電圧は、素子が微細化されても外部回
路との関係上、低電圧化されそうにない。電源電圧を下
げずに微細化したMOSトランジスタでは、ゲート長、
ゲート酸化膜厚、ソース・ドレイン接合深さの縮小化と
、チャネル部分の不純物濃度の増大によって素子内部と
電界強度は上昇し、特にドレイン拡散層近傍に高電界領
域を形成する。この高電界領域に流れ込むチャネル電子
は、電界により高エネルギーを得、衝突電離を起こし、
多数の電子正孔対が生成される。この生成された高エネ
ルギーを持つホット・エレクトロンの一部は、ゲート酸
化膜中に注入され、その一部がゲート酸化膜中にトラッ
プされる。MOSトランジスタでゲート酸化膜中に負電
荷が蓄積されると、閾値電圧が相互コンダクタンスが変
化し、回路の安定動作を損ない、性能の低下を招く。
(Prior Art) As semiconductor integrated circuits become more highly integrated, the MOS (Metal-Oxide-3emiconductor
(ductor) The miniaturization of transistors is progressing. However, even if the elements are miniaturized, the power supply voltage is unlikely to be lowered due to the relationship with external circuits. In MOS transistors that are miniaturized without lowering the power supply voltage, the gate length,
As the gate oxide film thickness and source/drain junction depth decrease, and the impurity concentration in the channel portion increases, the electric field strength inside the device increases, forming a high electric field region especially near the drain diffusion layer. Channel electrons flowing into this high electric field region gain high energy due to the electric field and cause impact ionization.
A large number of electron-hole pairs are generated. Some of the generated hot electrons with high energy are injected into the gate oxide film, and some of them are trapped in the gate oxide film. When negative charges are accumulated in the gate oxide film of a MOS transistor, the threshold voltage and mutual conductance change, impairing the stable operation of the circuit and causing a decrease in performance.

このMO3I−ランジスタのホット・キャリアに対する
欠点を緩和する方法として、LDD(LiHhtly 
Doped Drain)と呼ばれる構造が検討されて
いる。この構造を有する半導体装置の断面図を第4図に
示す。同図において、21はSi基板、22はゲート酸
化膜、23はゲート電極、24はSiO2膜、25はゲ
ート電極23をマスクとする不純物注入による低濃度不
純物領域、26はゲート側壁Sun、、27はゲート側
!26を有するゲート電極をマスクとした不純物注入に
より形成される高濃度不純物領域で、ソース/ドレイン
である。このように、ドレイン27の端部に低不純物濃
度領域25を設け、ドレイン端部における不純物濃度を
緩やかにすることにより、ドレイン近傍での高電界の集
中を抑制する。
As a method to alleviate the disadvantage of MO3I-transistors against hot carriers, LDD (LiHtly
A structure called a doped drain is being studied. A cross-sectional view of a semiconductor device having this structure is shown in FIG. In the figure, 21 is a Si substrate, 22 is a gate oxide film, 23 is a gate electrode, 24 is an SiO2 film, 25 is a low concentration impurity region formed by impurity implantation using the gate electrode 23 as a mask, 26 is a gate sidewall Sun, 27 is on the gate side! This is a high concentration impurity region formed by impurity implantation using the gate electrode 26 as a mask, and is a source/drain region. In this way, by providing the low impurity concentration region 25 at the end of the drain 27 and making the impurity concentration at the drain end moderate, concentration of a high electric field near the drain is suppressed.

このLDD構造とすることにより、ホット・キャリアの
問題点を緩和し、ドレイン耐圧に対する高信頼性が得ら
れる。
By adopting this LDD structure, the problem of hot carriers can be alleviated and high reliability with respect to drain breakdown voltage can be obtained.

(発明が解決しようとする課題) 上記LDD構造の半導体装置においては、低不純物濃度
領域の抵抗が高くなるため、トランジスタの相互コンダ
クタンスが低くなり、電流駆動能力および動作速度が低
下する欠点があった。
(Problems to be Solved by the Invention) In the semiconductor device with the above-mentioned LDD structure, the resistance of the low impurity concentration region increases, so the mutual conductance of the transistor decreases, resulting in a decrease in current drive ability and operating speed. .

本発明の目的は、従来の欠点を解消し、短チャネルのM
os+〜ランジスタにおいても、相互コンダクタンス等
の基本特性をできるだけ損なわないで、ホット・キャリ
アに対する耐性を向上させることができるMOSトラン
ジスタを提供することである。
The object of the present invention is to overcome the drawbacks of the prior art and to
It is an object of the present invention to provide a MOS transistor that can improve resistance to hot carriers without impairing basic characteristics such as mutual conductance as much as possible even in os+ transistors.

(課題を解決するための手段) 本発明の半導体装置およびその製造方法は、半導体基板
表面に形成されたゲート絶縁膜上に、チャネル長方向に
対して両端に異なる仕事函数を有するゲート電極を形成
し、このゲート電極をマスクとして半導体基板にイオン
注入を行ない、ソースおよびドレインを形成するもので
ある。
(Means for Solving the Problems) A semiconductor device and a method for manufacturing the same according to the present invention form gate electrodes having different work functions at both ends in the channel length direction on a gate insulating film formed on the surface of a semiconductor substrate. Then, using this gate electrode as a mask, ions are implanted into the semiconductor substrate to form a source and a drain.

(作 用) 本発明の構成により、LDD構造において、高抵抗の低
不純物濃度領域をゲート電極の仕事函数を変えてやるこ
とにより1局所的に反転層を形成し易くすることができ
、相互コンダクタンスの低下を防ぐことができる。
(Function) According to the configuration of the present invention, in the LDD structure, by changing the work function of the gate electrode in the high resistance low impurity concentration region, it is possible to easily form an inversion layer locally, and the mutual conductance can be reduced. can prevent a decline in

(実施例) 本発明の実施例を第1図ないし第3図に基づいて説明す
る。
(Example) An example of the present invention will be described based on FIGS. 1 to 3.

第1図は本発明の実施例における半導体装置を示すもの
で、nチャネル型MOSトランジスタに関するものであ
る。第2図は、第1図の実施例の製造方法を説明するた
めの工程断面図である。
FIG. 1 shows a semiconductor device according to an embodiment of the present invention, and relates to an n-channel MOS transistor. FIG. 2 is a process sectional view for explaining the manufacturing method of the embodiment shown in FIG.

まず、第2図(a)に示すように、p型シリコン半導体
基板1にゲート絶縁膜2を形成したのち、ゲート電極3
を形成する。ここで、ゲート電極3はWを用いる。
First, as shown in FIG. 2(a), a gate insulating film 2 is formed on a p-type silicon semiconductor substrate 1, and then a gate electrode 3 is formed on a p-type silicon semiconductor substrate 1.
form. Here, W is used for the gate electrode 3.

次に、n型ポリシリコン膜4を形成したのち〔第2図(
b)〕、反応性イオンエツチング(RIE)によりn型
ポリシリコン膜4を異方性エツチングし、平坦部に形成
されたn型ポリシリコン膜を除去する。この工程により
、ゲート電極3の周辺部のn型ポリシリコン膜だけが残
り、n型ポリシリコン膜4の一部による側壁が形成され
る〔第2図(C)〕。
Next, after forming an n-type polysilicon film 4 [Fig.
b)] The n-type polysilicon film 4 is anisotropically etched by reactive ion etching (RIE) to remove the n-type polysilicon film formed on the flat portion. Through this step, only the n-type polysilicon film at the peripheral portion of the gate electrode 3 remains, and a side wall is formed by a part of the n-type polysilicon film 4 [FIG. 2(C)].

次に、ゲート電極3をマスクとしてイオン注入を行ない
、第1のソース領域5s、 ドレイン領域5dを形成す
る〔第2図(d)〕。ここで、不純物として燐を用い、
打込みエネルギーを小さくし、ドース量も低濃度に抑え
である。
Next, ion implantation is performed using the gate electrode 3 as a mask to form a first source region 5s and a drain region 5d [FIG. 2(d)]. Here, using phosphorus as an impurity,
The implantation energy can be reduced and the dose can be kept to a low concentration.

次に、CVD  5102膜を形成したのち、RIEに
より前記CVD  5102膜を異方性エツチングし、
平坦部に形成された前記CV D−3in、膜を除去す
る。この工程により、ゲート電極3の周辺部のCVD−
3j。02膜だけが残す、CVD  5i02B(1)
 一部による絶縁膜側壁6が形成される〔第2図(e)
〕。
Next, after forming a CVD 5102 film, the CVD 5102 film is anisotropically etched by RIE,
The CV D-3in film formed on the flat portion is removed. Through this step, the CVD-
3j. Only 02 film remains, CVD 5i02B (1)
An insulating film side wall 6 is formed by a portion [FIG. 2(e)]
].

次に1本来のソースおよびドレイン領域を形成するため
に、砒素のイオン注入を行ない、第2のソース領域7s
、ドレイン領域7dを形成する〔第2図(f)〕。
Next, in order to form the original source and drain regions, arsenic ions are implanted, and a second source region 7s is formed.
, to form a drain region 7d [FIG. 2(f)].

最後に、熱処理を行ない、第1図に示すようなLDD構
造で、かつゲート電極がソースおよびドレインの端部で
仕事函数が小さくなっているようなnチャネル型MOS
トランジスタを形成する。
Finally, heat treatment is performed to create an n-channel MOS that has an LDD structure as shown in Figure 1, and in which the gate electrode has a small work function at the ends of the source and drain.
Form a transistor.

本実施例において、ゲート電極はWとn0ポリシリコン
で構成されており、仕事函数はそれぞれ4.55.3.
95(eV)である。このため、ソース・ドレインの低
不純物濃度領域は、チャネル中央部より反転層が形成し
易くなっており、相互コンダクタンスの低下を防いでい
る。このような構造を形成する際に、新たなマスクを追
加する必要もなく、容易に形成することができる。
In this example, the gate electrode is made of W and n0 polysilicon, and the work functions are 4.55.3.
95 (eV). Therefore, an inversion layer is more easily formed in the low impurity concentration regions of the source and drain than in the center of the channel, thereby preventing a decrease in mutual conductance. When forming such a structure, there is no need to add a new mask, and the structure can be easily formed.

第3図は、本発明の第2の実施例の製造方法を説明する
ための工程断面図である。
FIG. 3 is a process sectional view for explaining the manufacturing method of the second embodiment of the present invention.

まず、第3図(a)に示すように、p型シリコン半導体
基板1にゲート絶縁膜2を形成したのち、ゲート電極を
Wで形成する。
First, as shown in FIG. 3(a), a gate insulating film 2 is formed on a p-type silicon semiconductor substrate 1, and then a gate electrode is formed of W.

次に、ゲート電極3をマスクとして燐を低濃度にイオン
注入し、第1のソース領域5s、ドレイン領域5dを形
成する〔第3図(b)〕。
Next, using the gate electrode 3 as a mask, phosphorus is ion-implanted at a low concentration to form a first source region 5s and a drain region 5d [FIG. 3(b)].

次に、n型ポリシリコン膜4を形成したのち〔第3図(
c))、反応性イオンエツチング(RIE)によりn型
ポリシリコン膜4を異方性エツチングし、平坦部に形成
されたn型ポリシリコン膜を除去し、ゲート電極3の周
辺部にn型ポリシリコン膜4の一部による絶縁膜側壁6
が形成される〔第3図(d)〕。
Next, after forming an n-type polysilicon film 4 [Fig.
c)) The n-type polysilicon film 4 is anisotropically etched by reactive ion etching (RIE), the n-type polysilicon film formed on the flat part is removed, and the n-type polysilicon film is etched around the gate electrode 3. Insulating film sidewall 6 formed by part of silicon film 4
is formed [Fig. 3(d)].

次に、本来のソースおよびドレイン領域を形成するため
に、ゲート電極3をマスクとして砒素のイオン注入を行
ない、第2のソース領域7s、ドレイン領域7dを形成
する。
Next, in order to form the original source and drain regions, arsenic ions are implanted using the gate electrode 3 as a mask to form the second source region 7s and drain region 7d.

最後に、熱処理を行ない、第1図に示すような構造のn
チャネル型MOSトランジスタを形成する。
Finally, heat treatment is performed to form the structure shown in Figure 1.
A channel type MOS transistor is formed.

本実施例では、第1の実施例に比べて少ない工程で同様
の構造を得ることができる。
In this embodiment, a similar structure can be obtained with fewer steps than in the first embodiment.

上記実施例においては、ゲート電極としてWとn0ポリ
シリコンを用いたが、他の材料でもよい。
In the above embodiment, W and n0 polysilicon were used as the gate electrode, but other materials may be used.

nチャネル型MOSトランジスタにおいては、ゲート電
極の仕事函数がチャネル中央部で高く、両端で低くなる
ように構成されていればよい。
In an n-channel MOS transistor, the work function of the gate electrode may be high at the center of the channel and low at both ends.

(発明の効果) 本発明によれば、ゲート電極をチャネル長方向に対して
両端に異なる仕事函数を有して形成することにより、M
OSトランジスタについて素子の性能を損なうことなく
、ホット・キャリアに対する耐性を向上させ、ドレイン
耐圧に対する高信頼性を得ることができる。また、ゲー
ト電極の形成においては、自己整合型にできるので容易
に作製することができ、その実用上の効果は大である。
(Effects of the Invention) According to the present invention, by forming the gate electrode with different work functions at both ends in the channel length direction, M
With respect to an OS transistor, resistance to hot carriers can be improved and high reliability with respect to drain breakdown voltage can be obtained without impairing element performance. Furthermore, since the gate electrode can be formed in a self-aligned manner, it can be easily manufactured, and its practical effects are great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明における第1の実施例の半導体装置の断
面図、第2図は同製造方法を示す工程図、第3図は本発
明の第2の実施例の半導体装置の製造方法を示す工程図
、第4図は従来の半導体装置の断面図である。 1・・・p型シリコン半導体基板、 2・・・ゲート絶
縁膜、 3・・・ゲート電極、 4・・・n型ポリシリ
コン膜、 5S・・・第1のソース領域、 5d、 7
d・・・ドレイン領域、  6・・・絶縁膜側壁、 7
s・・・第2のソース領域。 第 図 3ゲート電越 第 図 第 図 第 図 第 図 第 図 2乙
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a process diagram showing the manufacturing method thereof, and FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The process diagram shown in FIG. 4 is a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon semiconductor substrate, 2... Gate insulating film, 3... Gate electrode, 4... N-type polysilicon film, 5S... First source region, 5d, 7
d...Drain region, 6...Insulating film side wall, 7
s...Second source area. Figure 3 Gate Electric Etsu Figure Figure 2

Claims (5)

【特許請求の範囲】[Claims] (1)半導体基板表面のMOS型トランジスタ領域とな
る部分に形成されたゲート絶縁膜と、前記ゲート絶縁膜
の上にゲート電極を有し、前記ゲート電極は、チャネル
長方向に対して両端に異なる仕事函数を有して形成され
ていることを特徴とする半導体装置。
(1) A gate insulating film formed on a portion of the surface of the semiconductor substrate that will become a MOS transistor region, and a gate electrode on the gate insulating film, the gate electrodes being different at both ends in the channel length direction. A semiconductor device characterized in that it is formed to have a work function.
(2)ソースおよびドレイン領域のチャネル側の端部に
低不純物濃度領域を有する請求項(1)記載の半導体装
置。
(2) The semiconductor device according to claim (1), further comprising a low impurity concentration region at the channel side end of the source and drain regions.
(3)半導体基板表面のMOS型トランジスタ領域とな
る部分に形成されたゲート絶縁膜上に、チャネル長方向
に対して両端に異なる仕事函数を有するゲート電極を形
成する工程と、前記ゲート電極をマスクとして前記半導
体基板表面にイオン注入を行ない、ソースおよびドレイ
ン領域を形成する工程を含む請求項(1)記載の半導体
装置の製造方法。
(3) Forming a gate electrode having a different work function at both ends in the channel length direction on the gate insulating film formed on the portion of the surface of the semiconductor substrate that will become the MOS transistor region, and masking the gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of implanting ions into the surface of the semiconductor substrate to form source and drain regions.
(4)第1のソースおよびドレイン領域を形成する工程
と、前記ゲート電極の周辺部に絶縁膜側壁を形成する工
程と、前記ゲート電極および前記絶縁膜側壁をマスクと
して前記半導体基板表面にイオン注入を行ない、第2の
ソースおよびドレインを形成する工程を含む請求項(1
)記載の半導体装置の製造方法。
(4) forming a first source and drain region, forming an insulating film sidewall around the gate electrode, and implanting ions into the semiconductor substrate surface using the gate electrode and the insulating film sidewall as a mask; Claim 1, further comprising the step of forming a second source and a drain by forming a second source and a drain.
) A method for manufacturing a semiconductor device according to the method.
(5)第1のゲート電極をマスクとして前記半導体基板
表面にイオン注入を行ない、第1のソースおよびドレイ
ンを形成する工程と、前記第1のゲート電極の周辺部側
壁に仕事函数の異なる第2のゲート電極を形成する工程
と、前記第1、第2のゲート電極をマスクとして前記半
導体基板表面にイオン注入を行ない、第2のソースおよ
びドレインを形成する工程を含む請求項(1)記載の半
導体装置の製造方法。
(5) implanting ions into the surface of the semiconductor substrate using the first gate electrode as a mask to form a first source and drain; 2. The method according to claim 1, further comprising the step of forming a gate electrode, and performing ion implantation into the surface of the semiconductor substrate using the first and second gate electrodes as masks to form a second source and drain. A method for manufacturing a semiconductor device.
JP18371788A 1988-07-25 1988-07-25 Semiconductor device and its manufacture Pending JPH0234936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18371788A JPH0234936A (en) 1988-07-25 1988-07-25 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18371788A JPH0234936A (en) 1988-07-25 1988-07-25 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0234936A true JPH0234936A (en) 1990-02-05

Family

ID=16140727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18371788A Pending JPH0234936A (en) 1988-07-25 1988-07-25 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0234936A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59118737A (en) * 1982-12-27 1984-07-09 Sumitomo Chem Co Ltd L-4-cyclopentenone ester
JPH02116171A (en) * 1988-10-25 1990-04-27 Nec Corp Manufacture of mos transistor
US5306655A (en) * 1990-07-24 1994-04-26 Matsushita Electric Industrial Co., Ltd. Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions
US5426327A (en) * 1990-10-05 1995-06-20 Nippon Steel Corporation MOS semiconductor with LDD structure having gate electrode and side spacers of polysilicon with different impurity concentrations
US5466958A (en) * 1992-10-30 1995-11-14 Kabushiki Kaisha Toshiba MOS-type semiconductor device having electrode structure capable of coping with short-channel effect and manufacturing method thereof
EP0856892A2 (en) * 1997-01-30 1998-08-05 Oki Electric Industry Co., Ltd. MOSFET and manufacturing method thereof
WO2009063582A1 (en) * 2007-11-15 2009-05-22 Panasonic Corporation Semiconductor device and method for manufacturing the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59118737A (en) * 1982-12-27 1984-07-09 Sumitomo Chem Co Ltd L-4-cyclopentenone ester
JPH02116171A (en) * 1988-10-25 1990-04-27 Nec Corp Manufacture of mos transistor
US5306655A (en) * 1990-07-24 1994-04-26 Matsushita Electric Industrial Co., Ltd. Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions
US5405787A (en) * 1990-07-24 1995-04-11 Matsushita Electric Industrial Co., Ltd. Structure and method of manufacture for MOS field effect transistor having lightly doped drain and source diffusion regions
US5426327A (en) * 1990-10-05 1995-06-20 Nippon Steel Corporation MOS semiconductor with LDD structure having gate electrode and side spacers of polysilicon with different impurity concentrations
US5466958A (en) * 1992-10-30 1995-11-14 Kabushiki Kaisha Toshiba MOS-type semiconductor device having electrode structure capable of coping with short-channel effect and manufacturing method thereof
US5756365A (en) * 1992-10-30 1998-05-26 Kabushiki Kaisha Toshiba Method of manufacturing MOS-type semiconductor device having electrode structure capable of coping with short-channel effects
EP0856892A2 (en) * 1997-01-30 1998-08-05 Oki Electric Industry Co., Ltd. MOSFET and manufacturing method thereof
EP0856892A3 (en) * 1997-01-30 1999-07-14 Oki Electric Industry Co., Ltd. MOSFET and manufacturing method thereof
WO2009063582A1 (en) * 2007-11-15 2009-05-22 Panasonic Corporation Semiconductor device and method for manufacturing the same

Similar Documents

Publication Publication Date Title
US5510279A (en) Method of fabricating an asymmetric lightly doped drain transistor device
JP2835216B2 (en) Method for manufacturing semiconductor device
JPH0216020B2 (en)
JPH02250331A (en) Semiconductor device and its manufacture
JPS62188277A (en) Formation of low concentration doped structure
JPH09181307A (en) Semiconductor device and manufacturing method therefor
JPH01205470A (en) Semiconductor device and its manufacture
JPH06204469A (en) Field-effect transistor and manufacture thereof
US6548363B1 (en) Method to reduce the gate induced drain leakage current in CMOS devices
US5879995A (en) High-voltage transistor and manufacturing method therefor
JPH0234936A (en) Semiconductor device and its manufacture
JP2781918B2 (en) Method for manufacturing MOS type semiconductor device
JPH04259258A (en) Manufacture of mis field effect semiconductor device
JPH01259560A (en) Semiconductor integrated circuit device
JPH0656855B2 (en) Insulated gate type field effect transistor
JPH04212467A (en) Semiconductor device and manufacture thereof
JP2623902B2 (en) Semiconductor device and manufacturing method thereof
JP3063051B2 (en) Method for manufacturing semiconductor device
JP2757491B2 (en) Method for manufacturing semiconductor device
JPS62120082A (en) Semiconductor device and manufacture thereof
JP2591518B2 (en) Semiconductor device
JP2537649B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP2507981B2 (en) Manufacturing method of complementary MIS transistor
JP2848274B2 (en) Method for manufacturing semiconductor device
JPS6136973A (en) Semiconductor device