JPH02250331A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH02250331A JPH02250331A JP7062489A JP7062489A JPH02250331A JP H02250331 A JPH02250331 A JP H02250331A JP 7062489 A JP7062489 A JP 7062489A JP 7062489 A JP7062489 A JP 7062489A JP H02250331 A JPH02250331 A JP H02250331A
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate electrode
- concentration region
- concentration
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910008814 WSi2 Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置およびその製造技術、特に、MIS
FET、さらに詳細には、高性能、高信頼性の微細化さ
れたMISFETおよびその製造技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices and their manufacturing technology, particularly MIS
The present invention relates to FETs, and more specifically, to high-performance, highly reliable miniaturized MISFETs and their manufacturing technology.
半導体集積回路の微細化に伴い、動作時に発生するホッ
トキャリアによる信頼性の劣化が問題となってきており
、このため最近ではドレイン領域を低濃度領域と高濃度
領域により構成する、いわゆるLDD構造が使用される
ようになってきている。With the miniaturization of semiconductor integrated circuits, deterioration in reliability due to hot carriers generated during operation has become a problem, and for this reason, the so-called LDD structure in which the drain region is composed of a low concentration region and a high concentration region has recently been developed. It is starting to be used.
この種のLDD形構造の半導体デバイスについては、た
とえば、工業調査会発行、「電子材料」1985年6月
号、P64〜P73に記載されている。This kind of semiconductor device having an LDD type structure is described, for example, in "Electronic Materials", June 1985 issue, published by Kogyo Kenkyukai, pages 64 to 73.
ところで、従来のLDD構造は、低濃度領域によりホッ
トキャリア耐性を向上させるが、反面この低濃度領域が
寄生抵抗として働くため電流駆動能力すなわち性能が落
ちるというトレードオフがあり、微細化するにつれて、
このトレードオフが大きくなっている。By the way, in the conventional LDD structure, the hot carrier resistance is improved by the low concentration region, but on the other hand, there is a trade-off in that the current driving ability, that is, the performance decreases because this low concentration region acts as a parasitic resistance.
This trade-off is getting bigger.
本発明は、上記トレードオフを解決することにある。The present invention seeks to resolve the above trade-off.
すなわち、本発明の目的は、高信頼性の微細化されたM
ISFETの如き半導体装置を提供することにある。That is, an object of the present invention is to provide a highly reliable miniaturized M
An object of the present invention is to provide a semiconductor device such as an ISFET.
本発明の他の目的は、高速動作に好適な高駆動能力のM
ISFETの如き半導体装置を提供することにある。Another object of the present invention is to provide a high driving capacity M that is suitable for high-speed operation.
An object of the present invention is to provide a semiconductor device such as an ISFET.
本発明のさらに他の目的は、安定な特性を実現する半導
体装置の製造方法を提供することにある。Still another object of the present invention is to provide a method for manufacturing a semiconductor device that achieves stable characteristics.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、以下のとありである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明の半導体装置は、ドレイン領域を低濃
度領域と高濃度領域とによって構成し、低濃度領域をゲ
ート電極と安定な重なりを持ち、かつ、その表面濃度が
横方向でほぼ一定となるようにする。また、ゲート電極
をほぼ垂直形状とし、上記低濃度および高濃度のドレイ
ン領域はゲート電極により規定する。That is, in the semiconductor device of the present invention, the drain region is composed of a low concentration region and a high concentration region, the low concentration region has stable overlap with the gate electrode, and the surface concentration thereof is approximately constant in the lateral direction. do it like this. Further, the gate electrode has a substantially vertical shape, and the low-concentration and high-concentration drain regions are defined by the gate electrode.
また、本発明の半導体装置の製造方法は、低濃度領域は
、角度イオン打込みにより、ゲート電極の端部を透過し
て不純物を半導体基板の表面にドープし、高濃度領域は
、ほぼ垂直方向からイオン打込みを行うことによりなる
ものである。Further, in the method of manufacturing a semiconductor device of the present invention, impurities are doped into the surface of the semiconductor substrate by angular ion implantation in the low concentration region by penetrating the edge of the gate electrode, and in the high concentration region, impurities are doped from the substantially vertical direction. This is achieved by performing ion implantation.
低濃度ドレイン領域がゲート電極と安定な重なりを持ち
かつその重なり部の表面濃度が一定となっているため、
動作時の半導体基板表面の最大型「界が、低濃度の領域
内で、かつ表面より内部に位置するようになる。したが
って、表面でのホットキャリアの発生が抑えられるため
、ホットキャリア注入による劣化が小さい。また、発生
したホットキャリアは、主としてゲート電極下の低濃度
領域上のゲート絶縁膜中に注入されるため、動作時には
低濃度領域が変調を受けにくい。Since the low concentration drain region has a stable overlap with the gate electrode and the surface concentration at the overlap part is constant,
During operation, the largest field on the surface of the semiconductor substrate is located within the low concentration region and inside the surface. Therefore, the generation of hot carriers at the surface is suppressed, so deterioration due to hot carrier injection is suppressed. Furthermore, since the generated hot carriers are mainly injected into the gate insulating film on the low concentration region under the gate electrode, the low concentration region is not easily modulated during operation.
また、低濃度領域自体がゲート電極による電界効果が大
きいため、寄生抵抗としての悪影響はなく、高い駆動能
力を持つ。Furthermore, since the low concentration region itself has a large electric field effect due to the gate electrode, there is no adverse effect as a parasitic resistance, and the region has high driving ability.
さらに、上記低濃度領域は、イオン打込みの角度と打込
みエネルギー ドーズ量によって任意に決定でき、また
これらは非常に制御よく行われるため、特性のバラツキ
等の問題が発生することを阻止できる。Furthermore, the low concentration region can be arbitrarily determined by the angle of ion implantation, the implantation energy dose, and these are controlled very well, so that problems such as variations in characteristics can be prevented from occurring.
′JR1図は本発明の実施例1を示す断面図、第2図は
本発明の実施例2を示す断面図、第3図は本発明の実施
例3を示す断面図、第4図は本発明の横方向の不純物濃
度分布を示す図、第5図〜第7図は本発明による半導体
装置の製造方法を示す断面図である。'JR1 is a sectional view showing the first embodiment of the present invention, FIG. 2 is a sectional view showing the second embodiment of the present invention, FIG. 3 is a sectional view showing the third embodiment of the present invention, and FIG. 5 to 7 are cross-sectional views showing the method of manufacturing a semiconductor device according to the invention.
第1図において、P型半導体基板1に12nmのゲート
絶縁膜2が形成され、ゲート絶縁膜2上には、N型不純
物、たとえばリンがドープされた多結晶シリコン膜と金
属シリサイドたとえばWS12からなるゲート電極3が
形成されている。ゲれている。In FIG. 1, a 12 nm gate insulating film 2 is formed on a P-type semiconductor substrate 1, and the gate insulating film 2 is made of a polycrystalline silicon film doped with an N-type impurity, such as phosphorus, and a metal silicide, such as WS12. A gate electrode 3 is formed. I'm getting angry.
また、半導体基板1の表面には、1012〜103/
ctlのリンがドープされ深さ0.1μm程度の低濃度
のN−型半導体領域5と、5 X 10”/cdのヒ素
がドープされ深さ0.2μm程度の高濃度のN型半導体
領域6が形成されており、N−型半導体領域5とN+型
半導体領域6とによりLDD構造を構成している。N−
型半導体領域5は、ゲート電極3と0.1〜0.2μm
程度の安定な重なりをもって形成されている。Further, on the surface of the semiconductor substrate 1, 1012 to 103/
A low concentration N-type semiconductor region 5 doped with ctl phosphorus and having a depth of about 0.1 μm, and a high concentration N-type semiconductor region 6 doped with 5×10”/cd arsenic and having a depth of about 0.2 μm. The N- type semiconductor region 5 and the N+ type semiconductor region 6 constitute an LDD structure.N-
The type semiconductor region 5 is 0.1 to 0.2 μm thick with the gate electrode 3.
They are formed with a certain degree of stable overlap.
第2図の実施例2においては、N゛型半導体領域6は、
サイドウオールスペーサ7によす、ケート電極3から離
間して設けられている。他の構成は第1図と同じである
。In the second embodiment shown in FIG. 2, the N-type semiconductor region 6 is
A side wall spacer 7 is provided so as to be spaced apart from the gate electrode 3. The other configurations are the same as in FIG.
第3図の実施例3にふいては、N−型半導体領域5とN
゛型半導体領域6との間に中間濃度のN型半導体領域8
が形成されている。N型半導体領域8は1013〜10
14/CrIのヒ素がドープされ深さ、0.15μm程
度に形成されている。In the third embodiment shown in FIG.
An intermediate concentration N-type semiconductor region 8 is provided between the ゛-type semiconductor region 6 and
is formed. N-type semiconductor region 8 is 1013 to 10
It is doped with arsenic of 14/CrI and formed to a depth of about 0.15 μm.
第1図〜第3図に示すN−型半導体領域5は第4図に示
すような横方向濃度分布を示している。The N- type semiconductor region 5 shown in FIGS. 1 to 3 has a lateral concentration distribution as shown in FIG.
すなわち、N−型半導体領域5の表面濃度は横方向でほ
ぼ一定となっている。That is, the surface concentration of the N- type semiconductor region 5 is approximately constant in the lateral direction.
次に、第5図〜第7図に基づき本発明の実施例1〜3に
よる半導体装置の製造工程を説明する。Next, the manufacturing process of semiconductor devices according to Examples 1 to 3 of the present invention will be explained based on FIGS. 5 to 7.
まず、第5図に示すように、P型半導体基板1に素子分
離用のフィールド酸化膜を形成した後、12重mのゲー
ト酸化膜を熱酸化により形成し、ゲート絶縁膜2とする
。しきい値電圧を調整するチャネルドープはゲート酸化
の前または後に行う。First, as shown in FIG. 5, a field oxide film for element isolation is formed on a P-type semiconductor substrate 1, and then a 12-layer gate oxide film is formed by thermal oxidation to form a gate insulating film 2. Channel doping to adjust the threshold voltage is done before or after gate oxidation.
次いで、半導体基板lの表面にCVD法によりIQQn
mの多結晶シリコン膜3aを形成し、拡散またはイオン
打込み等によりリンをドープする。Next, IQQn is deposited on the surface of the semiconductor substrate l by the CVD method.
A polycrystalline silicon film 3a having a thickness of m is formed and doped with phosphorus by diffusion or ion implantation.
次いで、多結晶シリコン膜3a上にCVDにより150
nmのWSi、膜3bを形成した後、レジストをマスク
としてWSi2膜3bおよび多結晶シリコン膜3aを順
次エツチングし、ゲート電極3を形成する。Next, a layer of 150
After forming the WSi film 3b with a thickness of 1 nm, the WSi2 film 3b and the polycrystalline silicon film 3a are sequentially etched using a resist as a mask to form the gate electrode 3.
次いで、第6図に示すように、半導体基板1を酸化し、
酸化シリコン膜4を形成する。次いで、たとえば45度
の角度でリンを例えば150〜200kevで5810
”イオン打込みする。このとき、ゲート電極3の影とな
る領域では、第6図(a)のようにイオン打込みされな
いが、ウェーハを回転することにより、パターン形状に
関係なく、対称にN−型半導体領域5が形成される。な
お、イオン打込みの角度、エネルギーはゲート電極3の
高さ、すなわち多結晶シリコン膜3aとWSi2膜3b
の膜厚、パターンの粗密度、ゲート電極3とN−型半導
体領域50重なり量を考慮して決定される。Next, as shown in FIG. 6, the semiconductor substrate 1 is oxidized,
A silicon oxide film 4 is formed. Then, for example, 5810 phosphorus at 150-200 kev at an angle of 45 degrees
At this time, ions are not implanted in the region shaded by the gate electrode 3 as shown in FIG. A semiconductor region 5 is formed.The angle and energy of ion implantation depend on the height of the gate electrode 3, that is, the polycrystalline silicon film 3a and the WSi2 film 3b.
It is determined by taking into consideration the film thickness of the film, the coarse density of the pattern, and the amount of overlap between the gate electrode 3 and the N- type semiconductor region 50.
次に、第7図に示すように、垂直方向からヒ素を例えば
60kevで5810”イオン打込みする。これにより
、ゲートをマスクとしてN+型半導体領域6が形成され
る。Next, as shown in FIG. 7, arsenic is ion-implanted from the vertical direction, for example, at 60 keV to 5810 inches. As a result, an N+ type semiconductor region 6 is formed using the gate as a mask.
さらに、第2図の実施例2および第3図の実施例3に示
す半導体装置を製造するためには、第7図に示す工程を
付加的に行う。Furthermore, in order to manufacture the semiconductor devices shown in Example 2 of FIG. 2 and Example 3 of FIG. 3, the steps shown in FIG. 7 are additionally performed.
すなわち、第7図(a)に示すように、半導体基板で2
X10”cnfイオン打込みし、N型半導体領域8を形
成する。なお、実施例2ではN型半導体領域8は形成し
ない。次いで、第7図(b)に示すように、全面にCV
D法により3001mの酸化シリコン膜を形成した後、
反応性イオンエツチングによりサイドウオールスペーサ
7を形成する。次いで、半導体基板1の露出した表面に
熱酸化により酸化シリコン膜を形成した後、半導体基板
1に対して垂直方向からヒ素を例えば50kevで5×
10”/c−イオン打込みし、熱処理してN″″型半導
体領域6を形成する。さらに、900℃10分程度の熱
程度を行い、イオン打込みした不純物の活性化を行う。That is, as shown in FIG. 7(a), 2
X10"cnf ions are implanted to form an N-type semiconductor region 8. Note that in Example 2, the N-type semiconductor region 8 is not formed. Next, as shown in FIG. 7(b), CV
After forming a 3001m silicon oxide film by method D,
Sidewall spacers 7 are formed by reactive ion etching. Next, after forming a silicon oxide film on the exposed surface of the semiconductor substrate 1 by thermal oxidation, arsenic is applied 5× at 50 keV from a direction perpendicular to the semiconductor substrate 1.
10"/c- ions are implanted and heat treated to form an N"" type semiconductor region 6. Further, heat treatment is performed at 900 DEG C. for about 10 minutes to activate the implanted impurities.
この後、通常のPSGあるいはBPSG膜の形成、コン
タクト領域の形成、電極、配線の形成、パッシベーショ
ンの形成等を行う。After this, formation of a normal PSG or BPSG film, formation of contact regions, formation of electrodes and wiring, formation of passivation, etc. are performed.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
以上の説明では主として本発明者によってなされた発明
をその利用分野であるMISFETに適用した場合につ
いて説明したが、これに限定されるものではなく、たと
えばそれ以外の半導体装置にも適用できる。In the above description, the invention made by the present inventor is mainly applied to MISFET, which is its field of application, but the invention is not limited to this, and can be applied to other semiconductor devices, for example.
本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.
すなわち、本発明によれば、N−型半導体領域を、ゲー
ト電極と安定な重なりをもって、しかも、Cその重なり
部分でほぼ一定濃度となるように形成されるので、(1
)ホットキャリアの発生を低減できる。(2)寄生抵抗
を小さくできる。等の効果がある。That is, according to the present invention, the N-type semiconductor region is formed to have a stable overlap with the gate electrode, and the C concentration is approximately constant in the overlapped portion.
) The generation of hot carriers can be reduced. (2) Parasitic resistance can be reduced. There are other effects.
これによって、MOS)ランジスタの信頼性を向上させ
、かつ、駆動能力を高めることができるので、微細化さ
れた高性能の集積回路を実現できる。This makes it possible to improve the reliability of the MOS transistor and increase its driving capability, thereby realizing a miniaturized, high-performance integrated circuit.
第1図は本発明の実施例1の断面図、
第2図は本発明の実施例2の断面図、
第3図は本発明の実施例3の断面図、
第4図は本発明の横方向濃度プロファイルを示す図、
第5図〜第7図は本発明の半導体装置の製造工程を示す
断面図である。
1・・・半導体基板、2・・・ゲート絶縁膜、3・・・
ゲート電極、3a・・・多結晶シリコン膜、3b・・・
W3i2膜、4・・・酸化シリコン膜、5・・・N−型
半導体領域、6・・・N。
型半導体領域、7・・・サイドウオールスペーサ、8・
・・N型半導体領域。
第1図
第4図
第5図
8FN型半導体装置
第
図
第
図Fig. 1 is a cross-sectional view of Embodiment 1 of the present invention, Fig. 2 is a sectional view of Embodiment 2 of the present invention, Fig. 3 is a sectional view of Embodiment 3 of the present invention, and Fig. 4 is a cross-sectional view of Embodiment 3 of the present invention. 5 to 7 are cross-sectional views showing the manufacturing process of the semiconductor device of the present invention. 1... Semiconductor substrate, 2... Gate insulating film, 3...
Gate electrode, 3a... polycrystalline silicon film, 3b...
W3i2 film, 4... silicon oxide film, 5... N- type semiconductor region, 6... N. type semiconductor region, 7... side wall spacer, 8.
...N-type semiconductor region. Figure 1 Figure 4 Figure 5 Figure 8 FN type semiconductor device Figure Figure
Claims (1)
にゲート絶縁膜を介して設けられたゲート電極と、前記
ゲート電極により規定されたソースおよびドレイン領域
を有し、前記ゲート電極はほぼ垂直形状にされるととも
に、前記ソース、ドレインの少なくとも一方は低濃度領
域と高濃度領域を有し、前記低濃度領域は、前記ゲート
電極の端部からチャネル方向に延びかつその表面濃度が
横方向にほぼ一定となる領域をもつことを特徴とする半
導体装置。 2、前記ソース、ドレインの少なくとも一方は前記低濃
度領域と前記高濃度領域の間に中間濃度領域を有するこ
とを特徴とする請求項1記載の半導体装置。 3、前記高濃度領域は、サイドウォールスペーサにより
前記ゲート電極から離間されていることを特徴とする請
求項1または2記載の半導体装置。 4、MISFETであることを特徴とする請求項1、2
または3記載の半導体装置。 5、前記低濃度領域は、角度イオン打込みによりゲート
電極の端部を透過して不純物を半導体基板の表面にドー
プし、前記高濃度領域および中間濃度領域は、ほぼ垂直
方向からイオン打込みを行うこうを特徴とする請求項1
記載の半導体装置の製造方法。 6、前記サイドウォールスペーサは、半導体基板の上面
の全面に酸化シリコン膜を形成した後、反応性イオンエ
ッチングを行うことにより形成されることを特徴とする
請求項2または3記載の半導体装置の製造方法。[Claims] 1. A semiconductor substrate having a first conductivity type, a gate electrode provided on the surface of the semiconductor substrate via a gate insulating film, and a source and drain region defined by the gate electrode. , the gate electrode has a substantially vertical shape, and at least one of the source and drain has a low concentration region and a high concentration region, and the low concentration region extends from an end of the gate electrode in the channel direction. A semiconductor device characterized by having a region in which the surface concentration is approximately constant in the lateral direction. 2. The semiconductor device according to claim 1, wherein at least one of the source and drain has an intermediate concentration region between the low concentration region and the high concentration region. 3. The semiconductor device according to claim 1 or 2, wherein the high concentration region is separated from the gate electrode by a sidewall spacer. 4. Claims 1 and 2 characterized in that it is a MISFET.
or the semiconductor device according to 3. 5. In the low concentration region, impurities are doped into the surface of the semiconductor substrate by penetrating the edge of the gate electrode by angular ion implantation, and in the high concentration region and the intermediate concentration region, ions are implanted from a substantially vertical direction. Claim 1 characterized by
A method of manufacturing the semiconductor device described above. 6. Manufacturing the semiconductor device according to claim 2 or 3, wherein the sidewall spacer is formed by forming a silicon oxide film over the entire upper surface of the semiconductor substrate and then performing reactive ion etching. Method.
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JP7062489A JPH02250331A (en) | 1989-03-24 | 1989-03-24 | Semiconductor device and its manufacture |
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