JPH01293654A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To sharply change a value of an electric current flowing in a transistor by reversing a connection direction of a source electrode and a drain electrode in a MOS transistor constituting a memory cell array of a ROM. CONSTITUTION:In a MOS transistor 1, a gate oxide film 3 and a gate electrode 4 which is composed of polysilicon are laminated on the surface of a p-type semiconductor substrate 2. In addition, an n-type impurity diffusion region 8 and a second n-type impurity diffusion region 9 are formed in a positional relationship which sandwiches the gate electrode 4 from both sides. In addition, a p<+> diffusion region 10 whose concentration is higher than that of the semiconductor substrate 2 is formed to be adjacent to the second n-type impurity diffusion region 9 in a channel region 7 situated between the first and second impurity diffusion regions 8, 9. This p<+> diffusion region 10 functions as a means to suppress an inversion of the channel region 7.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a MOS (M
etal Oxide Sem1conducto
r) This relates to the structure of a read-only semiconductor integrated circuit device in which one transistor holds two bits of memory data.

[Prior Art] A fixed information read-only semiconductor integrated circuit device (hereinafter referred to as ROM) generally has a memory array in which a large number of MOS (MOS) transistors are arranged in rows and columns. A memory cell array is formed of a plurality of word lines extending parallel to the row direction of a matrix and a plurality of bit lines extending parallel to each other in a direction perpendicular to the word lines. A MOS transistor of a memory cell is formed. The cross-sectional structure of this MOS transistor is shown in FIG. In a MOS transistor 1, a gate oxide film 3 and a gate electrode 4 made of polysilicon are laminated on the surface of a p-type semiconductor substrate 2. Furthermore, a source region 5 and a drain region 6, which are n-type impurity diffusion regions, are formed in a region near the surface of the p-type semiconductor substrate 2 in a positional relationship that sandwich the gate electrode 4 from both sides thereof. And source area 5
is connected to a predetermined potential, and the drain region 6 is connected to the bit line of the output line. Further, the gate electrode 4 is connected to a word line.

A method for programming fixed information into a ROM is to implant impurity ions into the channel region of a predetermined MOS transistor in a memory cell array.
A method such as changing the threshold voltage of the S transistor is used.

Next, the operation of the MOS transistor of the memory cell will be explained. When a predetermined operating voltage is applied from the word line to the gate electrode 4 with the source region 5 connected to a predetermined potential, an inversion layer is formed in the channel region 7 of the p-type semiconductor substrate 2 and the MOS transistor is activated. It is turned on, and a signal current flows to the bit line side connected to the drain region 6.

However, in the MOS transistor, which has a high threshold voltage set by implanting impurity ions into the channel region 7 as described above, the threshold voltage remains low even when a predetermined operating voltage is similarly applied from the word line to the gate electrode 4. is set higher than this operating voltage, the OFF state is maintained.

As described above, the conventional ROM has a 1-bit/1-transistor type structure in which memory data is read in correspondence with the 0N10FF state of each MOS transistor in the memory cell array. Then, M constituting the memory cell array
The OS transistor is formed with a structure in which source and drain regions 5.6 are symmetrically arranged in the semiconductor substrate 2 on both sides of the gate electrode 4. For this reason, even if the power sources connected to source region 5 and drain region 6 are replaced, the transistor operates in the same way.

[Problems to be Solved by the Invention] In a conventional ROM having the above-described structure, as the storage capacity increases, the memory cell size increases proportionally and the chip size increases. However, in reality, it is desired to increase the memory capacity and reduce the chip size, and for this purpose, we always rely on excessive microfabrication technology to prevent the increase in the chip size and further reduce the size. I have been trying to However, there are limits to relying solely on the advancement of microfabrication technology.

Therefore, the present invention has been made to solve the above-mentioned problems, and provides a semiconductor integrated circuit device having a structure capable of increasing storage capacity without increasing the chip size of the device. The purpose is to

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes a gate electrode stacked on a semiconductor substrate of a first conductivity type with a gate oxide film interposed therebetween, and a gate electrode sandwiched between the gate electrodes from both sides. a pair of second conductivity type impurity diffusion regions formed in a semiconductor substrate in such a positional relationship, one of the impurity diffusion regions is a source region and the other is a drain region, and a voltage is applied between the source and drain regions. With this applied, a voltage is further applied from the gate electrode to form an inversion layer of the second conductivity type on the surface of the semiconductor substrate located between the source and drain regions, thereby driving the source and drain regions with conduction. It is equipped with a MOS type semiconductor element, and a voltage is applied from a gate electrode formed adjacent to either the source region or the drain region in the surface region of the semiconductor substrate located between the source and drain regions of the MOS type semiconductor element. The present invention is characterized by comprising an inversion suppressing means for suppressing the formation of an inversion layer in the surface region of the semiconductor substrate located between the source and drain regions when the voltage is applied.

In one embodiment of the present invention, the inversion suppressing means is formed in a surface region of the semiconductor substrate adjacent to one of the impurity diffusion regions and immediately below the gate electrode, and is formed using a first conductivity type impurity having a higher concentration than the semiconductor substrate. Furthermore, in another example of the present invention, the surface region of the semiconductor substrate located between the source and drain regions includes a region covered with the gate electrode and a region not covered with the gate electrode, The region not covered by the electrode is located in succession with one of the source and drain regions, and the region not covered by the gate electrode constitutes an inversion suppressing means.

Furthermore, in still another example of the present invention, the gate oxide film includes one end region located near the source region and the other end region located near the drain region, and one of the end regions has a thickness of is formed larger than other portions, and this thicker region constitutes an inversion suppressing means.

[Function] The inversion suppressing means of the MO8 semiconductor element in the present invention is
Depending on the direction of the voltage applied between the pair of impurity diffusion regions of the OS type semiconductor element, the value of the current flowing between the two impurity diffusion regions can be changed. In other words, when the inversion suppressing means is located in succession on the low potential source region side, the inversion suppressing means is connected to the source/drain region in order to suppress the formation of an inversion layer due to the voltage applied from the gate voltage. No current channel is formed between
No current flows between both impurity regions. In addition, if the power supply connected to this pair of impurity diffusion regions is changed so that the inversion suppressing means is located in series with the drain region on the high potential side, the drain region applied to the gate electrode and the drain region Due to the action of the voltage, a current conduction path is also formed in the region of the reversal suppressing means, and a predetermined current flows between the source and drain regions. In this way, one MO8
By using a semiconductor element and changing the direction of the voltage applied to the impurity diffusion region, it is possible to extract current having two different current values.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

The present invention relates to a MOS that constitutes a memory cell array of a ROM.
By reversing the connection direction of the source and drain electrodes of a transistor, we have realized a MOS (MOS) transistor structure that can significantly change the value of the current flowing through the transistor, allowing two bits of memory information to be stored in one transistor. It was designed to be held.

First, FIG. 1A shows a cross-sectional structure of a MOS transistor which is a first embodiment of the present invention. MOS transistor 1 has a gate oxide film 3 and a gate electrode 4 made of polysilicon stacked on the surface of a p-type semiconductor substrate 2. Furthermore, an n-type first impurity diffusion region 8 and an n-type second impurity diffusion region 9 are formed in a region near the surface of the p-type semiconductor substrate 2 in such a positional relationship as to sandwich the gate electrode 4 from both sides thereof. There is. Furthermore, in the channel region 7 located between the first and second impurity diffusion regions 8.9, a p+ diffusion region 10 with a higher concentration (10"cm-") than the semiconductor substrate 2 is formed as an n-type second impurity diffusion region. It is formed adjacent to 9. This p+ diffusion region 10 constitutes an inversion suppressing means for the channel region 7.

Next, the operating state of the present MOS transistor 1 will be explained using FIG. 1B and FIG. 1C. First, FIG. 1B shows a connection state in which the n-type first impurity diffusion region 8 is the drain region, the n-type second impurity diffusion region 9 is the source region, and the p+ diffusion region 10 is adjacent to the source region side. . When a voltage is applied between the source and drain 8 and 9 in this state, and a gate voltage is further applied from the gate electrode 4, an inversion layer tends to be formed on the surface of the channel region 7 of the p-type semiconductor substrate 2. However, since the p-type impurity concentration in the p-type diffusion region located in the channel region 7 is set to be high, it becomes difficult to form an inversion layer depending on the gate voltage. Therefore, this p+ diffusion region 10 becomes a current blocking region and inhibits conduction between source and drain regions 9.8.

Therefore, in such a connected state, conduction is cut off or only a very small amount of current flows between the source and drain regions 9.8.

Next, as shown in FIG. 1C, when a power source is connected so that the n-type first impurity diffusion region 8 becomes a source region and the n-type second impurity diffusion region 9 becomes a drain region, the p-type diffusion region 1
0 is located adjacent to the drain region 9. In this connected state, when a voltage is applied between the source and drain regions 8.9 and a gate voltage is further applied from the gate electrode 4, the p+ diffusion region 10 has the gate voltage from the gate electrode 4 and the drain region 9 applied to the drain region 9. It will be affected by both voltages. In this case, the p+ diffusion region 10 is included in the region of the depletion layer 21 that expands due to the influence of the two-type pressure. An inversion layer 1 is formed in the channel region 7 which is the region directly under the gate electrode 2 of the p-type semiconductor substrate 2.
1 is formed.

This forms a conductive path between the source and drain regions 8.9, allowing drain current to flow.

In this way, when the p+ diffusion region 10 is located adjacent to the source region and the power source is connected to the source and drain regions, the MOS transistor 1 is in the OFF state, and conversely, the p+ diffusion region 10 is located adjacent to the drain region. When a power source is connected to the source and drain regions so as to be located adjacent to the MOS transistor 1, the MOS transistor 1 is turned on.

Next, a second embodiment of the present invention will be described using FIG. 2. In this example, p! 2 High concentration of p+ due to semiconductor substrate
It has a double diffusion structure in which the diffusion region 10 is doubly diffused around the n-type second impurity diffusion region 9. and,
Similar to the first embodiment, this p+ diffusion region 10 is connected to the source and drain regions depending on the power supply connection direction of the source and drain regions.
Turns on or off the conduction between the drain regions.

Next, a third embodiment of the present invention will be described using a jfiB diagram. In this example, the n-type first and second impurity diffusion regions 8
．． A p-type diffusion region 10 having a higher concentration than that of the p-type semiconductor substrate is formed around the p-type semiconductor substrate 9 by double diffusion. Further, in the surface region of the p-type semiconductor substrate 2 directly under the gate electrode 4, an n- diffusion layer 12 having a higher concentration than the p+ diffusion region 10 is formed adjacent to the n-type second impurity diffusion region 9. . This n- diffusion layer 12 functions to neutralize impurities in the p-type diffusion region 10 formed around the n-type second impurity diffusion region 9, and further to form an n-type impurity diffusion region. As a result, an n-type impurity region is continuously formed from the n-type second impurity diffusion region 9 to the surface region of the n − diffusion layer 12 .

When a power source is connected to the MOS transistor of this example so that the n-type second impurity diffusion region 9 is the source region and the n-type first impurity diffusion region 8 is the drain region, the power is applied from the gate electrode 4. Source region 8 for gate voltage
No inversion layer is formed in the substrate surface region of the p+ diffusion region 10 on the side, and conduction of the transistor is interrupted by this region.

In addition, conversely, the n-type first impurity diffusion region 8 is used as the drain region,
When the n-type second impurity diffusion region 9 is connected to serve as a source region, the p-type diffusion region 10 adjacent to the drain region 8 is affected by the gate voltage and the drain voltage applied to the drain region 8. A conductive region is formed and transistor 1 is turned on.

Further, a fourth embodiment of the present invention is illustrated in FIGS. 4A to 4C.
This will be explained using figures. This example uses a so-called LDD (Light Line) to alleviate the effect of electric field concentration near the drain.
y Doped Drain) structure
It is applied to a transistor, and the manufacturing process thereof is illustrated in order.

First, as shown in FIG. 4A, a gate oxide film 3 and a gate electrode 4 are formed on the surface of a p-type semiconductor substrate 2. Then, using this gate electrode 4 as a mask, n-type impurity ions are implanted into the surface of the p-type semiconductor substrate 2 to form an n-type first impurity diffusion region 13 and an n'''-type lower second impurity diffusion region 14.
to be accomplished.

Next, as shown in FIG. 4B, B'' (boron) ions 15 are obliquely implanted into the surface of the p-type semiconductor substrate 2 at an inclination angle θ. - Lower mold 1 and second impurity region 1
It is preferable to make the conditions equivalent to those under which 3.14 was formed.

Further, the inclination angle θ is preferably 45° or more. When this oblique ion implantation method is used, the n-type first impurity diffusion region 13
On the side, B+ ions 15 are extended and implanted into the surface region of the p-type semiconductor substrate 2 directly under the gate electrode 14, where a p+ diffusion region 10 is formed. At the same time, on the n-type second impurity diffusion region 14 side, the gate electrode 4 acts as a mask, and the B+ ions 15 are implanted into the n-type second impurity diffusion region 14 away from the end of the gate electrode 4. Ru. As described above, by using the oblique ion implantation method, it is possible to easily form the p+ diffusion region 10 only on one side of the surface region of the p-type semiconductor substrate 2 directly under the gate electrode 4 using the gate electrode 4 as an implantation mask. . This p+ diffusion region 10 constitutes an inversion suppressing means.

Finally, as shown in FIG. 4C, an oxide film 16 is deposited on the surface of the p-type semiconductor substrate 2, and this is anisotropically etched to form an oxide film sidewall 16 on the side wall of the gate electrode 4. . Then, using the sidewall 16 and the gate electrode 4 as a mask, n-type impurity ions are implanted into the surface of the p-type semiconductor substrate 2 to form an n-type first impurity in the LDD structure.
Impurity diffusion region 17 and n+ second impurity diffusion region 18
The manufacturing process is completed. FIG. 5 shows the impurity concentration distribution on the substrate surface of the MOS transistor manufactured according to the fourth embodiment. The horizontal axis indicates the position of the semiconductor substrate surface from the n+ first impurity diffusion region 17 side to the n+ second impurity diffusion region 18 side, and the vertical axis indicates the impurity concentration. As shown in this figure, in this MOS transistor, an asymmetric impurity concentration distribution is formed in the surface region of the p-type semiconductor substrate 2 directly under the gate region 4.

FIG. 6 is a cross-sectional structural diagram of a MOS transistor showing a fifth embodiment of the present invention. In this example, one end of the gate electrode 4 overlaps the end of the n-type first impurity diffusion region 8, and the other end of the gate electrode 4 is separated from the end of the n-type second impurity diffusion region 9. A so-called offset gate structure having an offset region 19 formed in this manner is constituted. Then, the n-type second impurity diffusion region 9 is used as a source region, the n-type first impurity diffusion region 8 is used as a drain region, and the source and drain power supplies are connected so that the offset region 19 is located adjacent to the source region 9. In this case, no inversion layer is formed in this offset region 19 with respect to the gate voltage, and the transistor becomes a current cutoff region and maintains the OFF state. Conversely, the mouth-type first impurity diffusion region 8 is used as a source region, the n-type second impurity diffusion region 9 is used as a drain region, and the source and drain power supplies are connected so that the offset region 19 is located adjacent to the drain region 9. in case of,
A conduction region is formed in the offset region 19 under the influence of the gate voltage and drain voltage, and the transistor is turned on. In this way, the offset region 19 of the gate electrode constitutes an inversion suppressing means.

FIG. 7 is a cross-sectional structural diagram of a MOS transistor showing a sixth embodiment of the present invention. In this example, n of the gate oxide film 3 is
A thick film portion 20 that is thicker than other portions is formed in a portion located on the type second impurity diffusion region 9 side. This thick film portion 20 of the gate oxide film 3 prevents the formation of a channel in the channel region 7 of the p-type semiconductor substrate 2 by reducing the force of the gate voltage acting on the surface of the p-type semiconductor substrate 2. exerts a suppressive effect. The thick film portion 20 of the gate oxide film 3 constitutes an inversion suppressing means, and this function is similar to that of the offset region 19 in the fifth embodiment.
It has the same effect as

In this way, in the present invention, M
A region that inhibits formation of a conductive path is formed between the source and drain regions of the OS transistor. The conduction current value of the MOS transistor is greatly changed by making the effect of the inhibition region valid or invalid depending on the direction of the voltage applied between the source and drain regions. The ROM, which is a semiconductor integrated circuit device of the present invention, can change the connection method of the source and drain regions for one MOS transistor by applying the MOS transistor having this inversion suppressing means to the memory cell array. holds 2 bits of memory. Therefore, it is possible to have twice the memory capacity in a memory cell array area that is almost the same as that of the conventional one, and it is possible to obtain twice the memory with the same chip size. In addition, in the present invention, the peripheral circuit for converting the source and drain connections is slightly more complicated than the conventional one, but the chip area is smaller than the memory capacity M.
For peripheral circuits, J
This is proportional to M, and the ratio of increase in chip size to increase in memory capacity is low, making it very effective for large-capacity mask ROMs.

In addition, in the above embodiment, M using a p-type semiconductor substrate
Although the description has been made regarding a transistor (OS), it goes without saying that the present invention can also be applied to a MOS transistor formed on an n-type semiconductor substrate.

[Effects of the Invention] As described above, in the present invention, the MOS semiconductor element constituting a semiconductor integrated circuit device is turned on in the direction of voltage application between one source and drain region, and the other is turned on in the direction of voltage application between the source and drain regions. By forming a reversal suppressing means that turns off the MOS semiconductor element in the direction of voltage application between the source and drain regions, it is possible to significantly change the current value depending on the voltage application method between the source and drain. In a read-only semiconductor integrated circuit device using this MOS semiconductor element, it is possible to double the storage capacity without increasing the chip size.
It has become possible to realize a semiconductor integrated circuit device whose storage capacity can be increased without increasing the chip size.

[Brief explanation of the drawing]

FIG. 1A is a cross-sectional structural diagram of a MOS semiconductor device showing a first embodiment of the present invention. Figures 1B and 1C are
1 is a cross-sectional structural diagram for explaining the operating state of a MOS semiconductor device according to a first embodiment of the present invention; FIG. FIG. 2 is a cross-sectional structural diagram of a MOS semiconductor device according to a second embodiment of the present invention. FIG. 3 is a cross-sectional structural diagram of a MOS semiconductor device according to a third embodiment of the present invention. FIGS. 4A, 4B, and 4C are cross-sectional structural diagrams showing the cross-sectional structure of a MOS semiconductor device according to a fourth embodiment of the present invention in the order of its steps. FIG. 5 is an impurity concentration distribution diagram showing the impurity concentration distribution in the substrate surface region of the MOS semiconductor device according to the fourth embodiment of the present invention. FIG. 6 is a cross-sectional structural diagram of a MOS semiconductor device showing a fifth embodiment of the present invention. FIG. 7 is a cross-sectional structural diagram of a MOS semiconductor device showing a sixth embodiment of the present invention. FIG. 8 is a cross-sectional structural diagram showing the cross-sectional structure of a conventional MOS semiconductor element. In the figure, 1 is a MOS transistor, 2 is a p-type semiconductor substrate, 3 is a gate oxide film, 4 is a gate electrode, 8 is an n-type first impurity diffusion region, 9 is an n-type second impurity diffusion region, 10
indicates a p+ diffusion region. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1A Figure 4: ζ Pinito @ Figure 1C Figure 2 Figure 3 Fut (Mono Cliff (am3)

Claims (4)

[Claims] (1) A gate electrode laminated on a semiconductor substrate of a first conductivity type via a gate oxide film, and a pair of gate electrodes formed in the semiconductor substrate in a positional relationship sandwiching the gate electrode from both sides. an impurity diffusion region of a second conductivity type, one of the impurity diffusion regions is used as a source region, the other of the impurity diffusion regions is used as a drain region, and when a voltage is applied between the source and drain regions, further the gate A MOS type semiconductor element that is driven by applying a voltage from an electrode to form an inversion layer of a second conductivity type on the surface of the semiconductor substrate located between the source and drain regions, thereby causing conduction between the source and drain regions. In a semiconductor integrated circuit device, the semiconductor integrated circuit device is formed in a surface region of the semiconductor substrate located between the source and drain regions of the MOS type semiconductor element, adjacent to either the source region or the drain region. A semiconductor integrated circuit comprising an inversion suppressing means for suppressing formation of an inversion layer in a surface region of the semiconductor substrate located between the source and drain regions when a voltage is applied from a gate electrode. circuit device. (2) The inversion suppressing means is configured to diffuse an impurity of a first conductivity type at a higher concentration than the semiconductor substrate, which is formed in a surface region of the semiconductor substrate adjacent to one of the impurity diffusion regions and directly under the gate electrode. 2. The semiconductor integrated circuit device according to claim 1, which is a region. (3) The surface region of the semiconductor substrate located between the source and drain regions includes a region covered by the gate electrode and a region not covered, and the region not covered by the gate electrode is the region covered by the gate electrode. 2. The semiconductor integrated circuit device according to claim 1, wherein a region located adjacent to one of the source and drain regions and not covered by the gate electrode constitutes the inversion suppressing means. (4) The gate oxide film includes one end region located near the source region and the other end region located near the drain region, and one of the end regions has a thickness different from the other end region. 2. The semiconductor integrated circuit device according to claim 1, wherein the region of increased thickness constitutes the inversion suppressing means.