JPH0273666A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease the occupancy area of a memory cell and to simplify its manufacturing process by stacking each gate so as to form a complementary switching FET. CONSTITUTION:A gate electrode 13 is formed through a gate insulating film 12 on a p-type Si substrate 11, and the electrode 13 is covered with an interlayer insulating film 16, and also source and drain regions 14 and 15 consisting of n<+>-type high concentration regions are formed. Accordingly, an n-type MOSFET is constituted by these region. Also, a semiconductor layer 17 being a film is provided on the film 16, and a gate electrode 19 is provided through an insulating film 18 on this, and source and drain regions 20 and 21 are formed in the layer 17. Accordingly, a p-type MOSFET is formed. In this way, the gate electrodes 13 and 19 are stacked, and a complementary switching FET is formed.

Description

[Detailed Description of the Invention] The circuit configuration of an SRAM memory cell is such that a switching transistor is provided between each input/output terminal of a flip-flop circuit and a bit line, and the gate of the switching transistor is usually It is considered a word line.

By the way, if the switching transistor is composed of MIS transistors of only one conductivity type, the MIS
There is a potential drop corresponding to the dark value voltage of the S transistor.

For example, when a switching transistor is configured using only nMO3 transistors, the potential of each input/output terminal can only be brought to a potential lower than the bit line by a dark value voltage.

Therefore, it is known that such switching transistors have a complementary configuration, and for example, the complementary switching transistor is described in US Pat. No. 3,457,435.

[Problems to be Solved by the Invention] In general, semiconductor memory devices such as SRAMs are becoming more highly integrated, and there is a need to reduce the area of their memory cell arrays.

However, as a switching transistor, nMO
Forming three transistors and a PMOS transistor side by side increases the area, which goes against the trend toward higher integration.

Further, it is preferable to have a structure that simplifies the manufacturing process.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device having complementary switching transistors that does not increase the area of memory cells, and furthermore, provides a semiconductor memory device having a structure that can simplify the manufacturing process. The purpose is to provide.

[Means for Solving the Problems] A semiconductor memory device of the present invention for achieving the above-mentioned object has a memory cell configured with a flip-flop circuit formed of MIS transistors and a switching transistor formed of MIS transistors. In the semiconductor memory device, the switching transistor has a second conductivity type M on the gate of the first conductivity type MIS transistor.
The IS transistor is characterized in that its gate has a stacked structure. Here, the channel region of the second conductivity type MIS transistor may be formed under the gate with an insulating film interposed therebetween, or may be formed above the gate with an insulating film interposed therebetween.

The MIS transistors of each conductivity type are connected in parallel, but the connection may be made by a selective tungsten layer.

Furthermore, in the semiconductor memory device of the present invention, in the structure described above, the channel region of the MIS transistor of the second conductivity type is formed in the same layer as the load element. Furthermore, the channel region of the MIS transistor of the second conductivity type can be formed into a continuous pattern with the load element. Here, the load element may be a high resistance load, and may be an MIS of a conductivity type opposite to that of the drive transistor.
It may also be a transistor or the like.

[Function] By forming the gates of the MIS transistors of each conductivity type in a stacked manner, the elements are arranged in the vertical direction, and the area occupied on the plane can be saved. Also,
By forming the channel region of the MIS transistor of the second conductivity type in the same layer as the load element, there is no need to newly provide a channel region for the MIS transistor of the second conductivity type, and the number of steps can be reduced accordingly.

(Example〕 Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an example of an SRAM in which a memory cell array is constructed of nMO5 transistors, and the memory cell circuit is of a high resistance load type using a resistance layer as a load, as shown in FIG.

First, the circuit of the memory cell will be explained with reference to FIG. 3. The flip-flop circuit consists of a resistor 7
．． The resistor 7 and the nMO3 transistor 5 are connected in series between the power supply voltage and the ground voltage, and the resistor 8 and the nMO3 transistor 5 are similarly connected in series. Both nMO3 transistors 5.6 have their sources commonly connected, and their gates are connected to the drains of the other transistors. At the input/output terminals of the flip-flop circuit, so-called cross-coupled contacts 9.10, a switching transistor is provided between the pair of pinpoint lines B, B.

Here, the switching transistors are each of a complementary type, and a pMO transistor 1 of a second conductivity type is provided in parallel connection with an nMOS transistor 3 of a first conductivity type.
The structure is such that a 9MOS transistor 2 of a second conductivity type is connected in parallel with an nMO3 transistor 4 of a first conductivity type.

The gates of these transistors connected in parallel are stacked as described later. A word line signal W is supplied to the gates of the nMOS transistors 3 and 4, and a word line signal W is supplied to the gate of the pMO5 transistor 1.2.

As shown in FIG. 4, these signals W and W are connected to the word line selection signal Φ
can be easily obtained from WL, and each memory cell M
c. As described later, these signals W
, W can be supplied together in a stacked word line.

The structure of the semiconductor memory device of this embodiment having the above-described circuit configuration is shown in FIGS. 1 and 2. .

First, the structure of a switching transistor will be explained with reference to FIG. 1. A first gate electrode 13 is formed on a p-type silicon substrate 11 with a gate insulating film 12 interposed therebetween. It is covered with an interlayer insulating film 16. On the surface of the p-type silicon substrate 11, source/drain regions 14.15 made of n° type high concentration impurity regions are formed so as to face each other with the gate electrode 13 in between. The region between these source/drain regions 14 and 15 is a channel forming region 26. Therefore, these source/drain regions 14, 15° gate electrode 13, etc. constitute an n-type MOS transistor which is the first conductivity type. One of these source/drain regions 14 and 15 is connected to a bit line, and the other is connected to a node of a cross-coupled contact.

A thin semiconductor layer 17 is provided on the interlayer insulating film 16 . A second gate electrode 19 is provided above this semiconductor layer 17 with an insulating film 18 interposed therebetween. The semiconductor layer 17 has a ρ
Source/drain regions 20 and 21 made of a type 2 heavily doped impurity region are formed. Source/drain region 20.
The region between 21 is a channel forming region 27. These source/drain regions 20, 21, gate electrode 19, etc. form a p-type MOS transistor of the second conductivity type. The surfaces of the gate electrode 19 and the semiconductor layer 17 are covered with an insulating film 25. The source/drain region 20 is connected to the source/drain region 14 via a selective tungsten layer 22 in which a contact hole is filled. sauce·
Similarly, the drain region 21 is connected to the source/drain region 15 via a selective tungsten layer 23 in which a contact hole is filled. That is, the pMOS transistor O3 is connected in parallel through these selective tungsten layers 22 and 23.

In this way, the first gate electrode 13 and the second gate electrode 1
9 is stacked, a complementary switching transistor can be obtained without increasing the area occupied on the plane. Further, forming the selective tungsten layers 22 and 23 for parallel connection can be formed in the same process as other contact holes of the memory cell, and does not increase the process in any way.

The second gate electrode 19 can also be provided in a region 28 surrounded by a dotted line in the figure below the semiconductor layer 17.

In this case, the electric field of the gate electrode 19 is influenced from below the channel forming region 27 .

Next, without referring to FIG. 2, the entire memory cell using switching transistors having such a structure will be described. In particular, in this example, the second conductivity type MIS transistor is formed in the same layer as the high resistance load element.

First, the shaded area in FIG. 2 is the semiconductor layer 31, which is, for example, a polysilicon layer. This semiconductor layer 31
is the bit line contact area 40 in each memory cell.
It extends in a substantially straight line from the ground line to the ground line 41. A contact region 42 from the contact region 40 of the focus line of this semiconductor layer 31 to the gate electrode 43 of the drive transistor
In the region up to, p is aligned with the upper layer word line 33.
A type impurity is introduced to form a source/drain N region, which becomes a source/drain region and a channel forming region of a pMO3 transistor of the second conductivity type. This semiconductor layer 31 is further extended in a direction perpendicular to the word line extension direction, and a region from a contact region 42 to the gate electrode 43 to the ground line 41 functions as a high resistance load element 44 (resistance load). In this way, the SRAM of this embodiment
In this case, one p of the complementary switching transistor is formed using the same layer in which the high resistance load element 44 is formed.
A MO3 transistor is formed. Therefore, even if the structure has complementary switching transistors, its p
The channel region of the MOS transistor, etc. can be obtained by simply extending the existing layer in which the high resistance load element 44 is formed, and there is no significant increase in process steps. Further, by setting the thickness of the semiconductor layer 31 to 50 nm or less, an ultra-thin high-performance transistor can be obtained, and a high-resistance load can be obtained at the same time. Furthermore, instead of a resistive load, pMO3 can be used in the same process as the switching transistor.
By forming a transistor, a complete CMO3 type memory cell structure is obtained.

In this embodiment, the word line which intersects the semiconductor IJ31 substantially perpendicularly through an insulating film (not shown) is two lines, one above the other and one above the other. That is, first conductivity type nMO
An upper layer word line 33 that functions as a gate electrode of a second conductivity type pMOS transistor is arranged in substantially the same pattern as a lower layer word line 32 that functions as a gate electrode of an s transistor. The lower word line 32 corresponds to the first gate electrode I3 in FIG. 1, and the upper word line 33 corresponds to the first gate electrode I3 in FIG.
This corresponds to the gate electrode 19. The lower word line 32 performs control TJ of the channel formation region between the source and drain regions formed on the silicon substrate, and the upper word line 33
controls the channel forming region formed in the semiconductor layer 31. With this structure in which the gate electrodes are stacked one above the other, the area occupied by the gate electrodes can be prevented from increasing.

Note that regions 51 to 54 are the source region or drain region of the drive transistor, respectively, and region 55 is a field insulating film region. The circuit configuration of the memory cell is shown in FIG.

The SRA of this embodiment has such a memory cell structure.
In M, the pMO5l-transistor is a high resistance load element 44
It is formed by extending the semiconductor layer 31 that constitutes the semiconductor layer 31 as it is. Therefore, a PMOS transistor can be obtained without a significant increase in process steps, and it is also possible to respond to higher performance and complete CMO3.

Although this embodiment has been described assuming that the first conductivity type is n type and the second conductivity type is p type, it is also possible to use conductivity types opposite to each other.

〔Effect of the invention〕

In the semiconductor memory device of the present invention, complementary switching transistors are formed by stacking gates, so that the area occupied by the complementary switching transistors can be reduced. Also,
In particular, since the second conductivity type MIS transistor on the upper side of the stacked structure can be formed using the layer in which the load element is provided, complementary switching transistors can be provided without significantly increasing the number of steps. .

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of an example of a semiconductor memory device of the present invention, FIG. 2 is a plan view showing the structure of a memory cell of an example of a semiconductor memory device of the present invention, and FIG. 3 is a semiconductor memory device of the present invention. FIG. 4 is a circuit diagram showing the connection relationship of the word lines. 13...First gate electrode 19...Second gate electrode 2021...Source/rain region of PMOS transistor 1415...Source/rain region of nMO5 transistor 22.23...Selected tungsten layer 31 ...Semiconductor layer 32...Lower layer word line 33...Upper layer word line 44...High resistance load element TODO, t-4! A-eye Kagayuki J Shimoto X Ushiri & Measurement Issaj Me Kuribe Figure 1 Patent Applicant Sony Corporation Representative Patent Attorney Akira Koba (and 2 others) Me-nana-suse! 5 times - 1 (N Figure 3 4

Claims (2)

[Claims] (1) In a semiconductor memory device in which a memory cell is constituted by a flip-flop circuit formed by an MIS transistor and a switching transistor formed by an MIS transistor, the switching transistor is an MIS transistor of a first conductivity type.
A semiconductor memory device having a structure in which a gate of a second conductivity type MIS transistor is stacked on a gate of the transistor. (2) The semiconductor memory device according to claim (1), wherein the channel region of the MIS transistor of the second conductivity type is formed in the same layer as the load element.