JP3002009B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device used as a read-only memory device.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been developed in the direction of large capacity and high integration, and the demand for miniaturization has been further increased. Accordingly, a layout of a semiconductor pattern and a structure of a semiconductor device which are more advantageous for miniaturization are desired. Read-only memory devices are no exception.

The threshold voltage of a MIS transistor can be controlled by the type and concentration of impurity diffusion in a semiconductor substrate serving as a channel. A structure has been used in which information stored in a read-only memory device is selectively accumulated depending on whether a transistor operation threshold voltage of a gate is positive or negative with respect to a reference voltage. A conventional example is shown in FIG.
A description will be given according to (b).

FIG. 2A is a plan view of a main part showing a layout of an example of a conventional semiconductor device. The layout of the semiconductor device shown in FIG. 2A includes an element isolation region 1, a memory cell transistor gate electrode region 2, a select line transistor gate electrode region 3, and a depletion MOS (DM
(OS) This is a layout mainly including the N-type diffusion region 17 for channel formation and the contact pattern region 5 to the drain region 18.

A program for a read-only memory device manufactured with this layout is used to determine whether a diffusion layer formed by the N-type diffusion region 17 for forming a DMOS channel exists and becomes a DMOS or an enhancement MOS (EMOS) without it. Alternatively, data is written. When a conventional pattern layout is used, it is necessary to separate the contact pattern from the gate electrode by the distance of the overlay margin 6 for forming a contact, as a limitation on the layout of the contact pattern region 5.

Accordingly, the distance between the select line transistor gate electrode regions 3 and 3 at the respective ends of the two select line transistor gate electrode regions 3 arranged two above and below the contact pattern region 5 respectively. 7 is required to be longer than the sum of the vertical distance of the contact pattern region 5 and twice the overlapping margin 6 for forming contacts.

FIG. 2B is a sectional view of a main part of an example of a conventional semiconductor device. FIG. 2B is a sectional structural view of FIG.
FIG. 3 is a vertical cross-sectional view passing through the center of a contact pattern region 5 in the plan view shown in FIG. The cross-sectional structure shown in FIG. 2B includes a silicon substrate 8, an element isolation oxide film 19, a memory cell transistor gate electrode 9 comprising a gate oxide film and a gate electrode polysilicon, a select line transistor gate electrode 10, a silicon It comprises a drain diffusion layer 11 formed in a substrate 8, an interlayer insulating film 15, and an aluminum wiring 16 serving as a bit line.

In the sectional view of FIG. 2B, the N-type diffusion layer for forming the DMOS channel and the N-type diffusion layer between the gate electrodes are not shown. It has a structure that exists in. FIG. 3 also shows a section viewed from the cross section of the overlap margin 6 for forming the contact and the distance 7 between the select line transistor gate electrode regions 3 and 3 at the end.

[0009]

The memory cell (semiconductor device) formed as described above is generally called a single-layer polysilicon NAND gate. Since this structure has one contact for a plurality of gates, it is advantageous for high integration of a circuit. In recent years, this structure has been often used for a memory cell of a large-capacity read-only memory device. When the conventional method is used, there is a problem that, when an attempt is made to achieve higher integration, the semiconductor device is disadvantageous in terms of miniaturization because of the necessity of an overlay margin for forming an extra contact.

In addition, when miniaturization is advanced with the conventional method, the aspect ratio (the ratio between the depth and the diameter of a contact) of a contact formed in one drain region to a contact formed in one source region becomes large. Therefore, there is also a problem that it is difficult to form a stable wiring. Further, since the N-type diffusion layer for forming the DMOS channel is formed before the gate is formed, there is also a problem that a period from a program step to completion of the read-only memory device is long.

Further, since the pattern layout is such that a plurality of gates are arranged in series, the current value (current driving capability) of the transistor of the memory cell cannot be increased.
There is also a problem that it is disadvantageous for high-speed operation. The current value of the memory cell transistor depends on the characteristics of EMOS (enhancement MOS) and DMOS (depletion MOS) transistors constituting the memory cell.
Hereinafter, two points which the inventor focused on to enable high-speed operation of the semiconductor device will be described.

In general, the transconductance g _me of a MOS transistor follows the following equation, where the transconductance when the source resistance R _s is not considered is g _m . g _me = g _m / (1 + _RS × g _m ) That is, when the resistance R _{S of the} source region increases, the transconductance g _me deteriorates remarkably, and characteristics such as the amplification factor and the switching speed of the MOS transistor deteriorate. Would. According to the present invention, the characteristics of the MOS transistor are improved by lowering the source resistance R _S.

In general, when an N-type impurity diffusion layer for forming a channel of a DMOS transistor is formed on a silicon substrate by ion implantation or the like, the electric resistance increases as the amount of ion implantation increases and the impurity concentration increases. Drops,
The current drive capability of DMOS transistors tends to improve. However, the impurity element that dissolves in silicon cannot be dissolved beyond a certain value called a solid solubility limit, and therefore exhibits a characteristic of being saturated with a certain electric resistance, and it is difficult to reduce the value to a value lower than that. . It is conceivable to lower the resistance by increasing the activation rate of the impurity ions.However, even with this method, the resistance value can be reduced only to a certain value. Due to the heat treatment, the diffusion amount of the impurity in the silicon becomes remarkable, which is a disadvantageous condition for miniaturization of the memory element.

According to the present invention, a method is employed in which the resistance corresponding to the channel of the DMOS transistor is reduced and the same effect as when the current driving capability of the DMOS transistor is improved is obtained. SUMMARY OF THE INVENTION It is an object of the present invention to realize miniaturization, improve transconductance of an enhancement transistor, enable high-speed operation, and reduce the resistance of a region corresponding to the channel of a DMOS transistor. It is an object of the present invention to provide a semiconductor device which can achieve a high-speed operation by exhibiting the same effect as the improvement of the current driving capability of the present invention, and can shorten the period from the program configuration to the completion of the read-only memory.

[0015]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: one source diffusion layer and one drain diffusion layer formed below a surface of a semiconductor substrate; and a plurality of gates formed on the surface of the semiconductor substrate. A plurality of memory cell transistor gates formed on the plurality of gate insulating films in a state of being arranged in series between the insulating film and the source diffusion layer and the drain diffusion layer
An electrode and at least two select line transistor gate electrodes; a plurality of memory cell transistor gate electrodes;
An inter-gate electrode diffusion layer formed below the surface of the semiconductor substrate between two or more select line transistor gate electrodes.
Then, one of the source region and one <br/> least one and at least two selected line transistor is also the drain region
One of the inter-gate diffusion layers between the gate electrodes is covered with a conductive material, and the select line transistor between them is covered.
Connect the conductive material layer on the gate, and on the conductive material layer
A contact pattern region for connecting a bit line is arranged.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the inter-gate electrode diffusion layer is covered with a conductive material layer. According to a third aspect of the present invention, in the semiconductor device of the first aspect, a depletion type transistor is selected from a plurality of transistors including a source diffusion layer and a drain diffusion layer, a diffusion layer between gate electrodes, and a plurality of transistors. A conductive material layer covering the inter-gate electrode diffusion layer on both sides of the transistor gate electrode corresponding to the transistor functioning as the transistor is connected on the transistor gate electrode corresponding to the transistor functioning as the depletion type transistor.

According to a fourth aspect of the present invention, in the semiconductor device, one source diffusion layer and one drain diffusion layer formed below the surface of the semiconductor substrate, a plurality of gate insulating films formed on the surface of the semiconductor substrate, A plurality of memory cell transistor gate electrodes, two or more select line transistor gate electrodes formed on a plurality of gate insulating films in a state of being arranged in series between the layer and the drain diffusion layer, and a plurality of memory cell transistor gate electrodes And a diffusion layer between gate electrodes formed under the surface of the semiconductor substrate between two or more select line transistor gate electrodes. Then, one of the inter-gate electrode diffusion layers between the two or more select line transistor gate electrodes is connected to at least one of the one source region and the one drain region by a conductive material layer. .

According to a fifth aspect of the present invention, in the semiconductor device, one source diffusion layer and one drain diffusion layer formed below the surface of the semiconductor substrate, a plurality of gate insulating films formed on the surface of the semiconductor substrate, A plurality of memory cell transistor gate electrodes, two or more select line transistor gate electrodes formed on a plurality of gate insulating films in a state of being arranged in series between the layer and the drain diffusion layer, and a plurality of memory cell transistor gate electrodes And a diffusion layer between gate electrodes formed under the surface of the semiconductor substrate between two or more select line transistor gate electrodes. A plurality of memory cell transistors each including a source diffusion layer and a drain diffusion layer, a diffusion layer between gate electrodes, a plurality of memory cell transistor gate electrodes, and two or more select line transistor gate electrodes; Among the selection line transistors, the diffusion layers on both sides of the selection line transistor gate electrode corresponding to the selection line transistor functioning as a depletion type transistor are covered with a conductive material layer. In addition, the conductive material layer is connected above a select line transistor gate electrode corresponding to a select line transistor that functions as a depletion type transistor. Further, portions corresponding to two depletion-type transistors used as select line transistors and arranged with one source region or one drain region interposed therebetween are arranged in a row in the bit line direction.

According to a sixth aspect of the present invention, in the semiconductor device, one source diffusion layer and one drain diffusion layer formed below the surface of the semiconductor substrate, a plurality of gate insulating films formed on the surface of the semiconductor substrate, A plurality of memory cell transistor gate electrodes formed on the plurality of gate insulating films in a state of being arranged in series between the layer and the drain diffusion layer, and a gate formed below the semiconductor substrate surface between the plurality of memory cell transistor gate electrodes And an inter-electrode diffusion layer. And
A plurality of memory cell transistors each including a source diffusion layer, a drain diffusion layer, a diffusion layer between gate electrodes, and a plurality of memory cell transistors, and function as a depression type transistor corresponding to a program of a read-only memory among a plurality of memory cell transistors. The inter-gate electrode diffusion layers on both sides of the memory cell transistor gate electrode corresponding to the memory cell transistor are covered with a conductive material layer for programming a read-only memory. In addition, a conductive material layer for program writing is connected on a memory cell transistor gate electrode corresponding to a memory cell transistor that functions as a depletion type transistor, and the conductive material layer for program writing is connected to one source diffusion layer and It is formed on at least one contact portion of one drain region to serve as a spacer for wiring connection.

[0020]

According to the first aspect of the present invention, at least one of the source region and the drain region is covered with the conductive material layer, and the contact pattern region is disposed on the conductive material layer. As a result, the read-only memory can be miniaturized and highly integrated as much as the overlay margin increases, and the overlay margin increases, so that a stable semiconductor device can be manufactured.

According to the second aspect of the present invention, since the inter-gate electrode diffusion layer is covered with the conductive material layer, the source and drain diffusion layers, the inter-gate electrode diffusion layer, and the plurality of memory cell transistor gate electrodes are formed. Can improve the characteristics of a plurality of transistors, particularly the transconductance of an enhancement transistor, and can improve the characteristics such as the amplification factor and the switching speed of the enhancement transistor. The operation can be performed stably.

According to the third aspect of the present invention, a transistor which functions as the depletion transistor includes a conductive material layer covering the inter-gate electrode diffusion layer on both sides of the transistor gate electrode corresponding to the transistor functioning as the depletion transistor. Since the connection is made on the transistor gate electrode corresponding to the above, the characteristics of the depletion type transistor, in particular, the resistance corresponding to the channel can be reduced, and the current driving capability of the depletion type transistor is remarkably improved. Is obtained, and remarkable improvement and stabilization of characteristics can be attained. Therefore, high speed operation of the semiconductor device can be stably achieved.

According to a fourth aspect of the present invention, at least one of one of one of the diffusion layers between gate electrodes between two or more select line transistor gate electrodes and one source region and one drain region. Are connected by a conductive material layer, so that miniaturization, high integration, and high-speed operation of a semiconductor device as a read-only memory can be achieved.

According to a fifth aspect of the present invention, the inter-gate electrode diffusion layers on both sides of the select line transistor gate electrode corresponding to the select line transistor functioning as a depletion type transistor are covered with the conductive material layer. Two layers which are connected on a selection line transistor gate electrode corresponding to a selection line transistor whose layer functions as a depletion type transistor and which are disposed with one source region or one drain region interposed therebetween and used as a selection line transistor By arranging the portions corresponding to the depletion type transistors in a line in the bit line direction, the characteristics of the select line transistors can be improved in the same manner as the above depletion type transistors. Further, regions corresponding to depletion type transistors, which are two select line transistors disposed with the source region or the drain region interposed therebetween, are arranged in a line in the bit line direction, so that a semiconductor device as a read-only memory can be miniaturized. High integration can be realized.

According to the structure of the sixth aspect, the conductive material layer for program writing is connected on the memory cell transistor gate electrode corresponding to the memory cell transistor functioning as a depletion type transistor, and the conductive layer for program writing is connected. Since the conductive material layer is formed on at least one contact portion of one source diffusion layer and one drain region to serve as a spacer for wiring connection, miniaturization and high integration of the read-only memory are achieved. And the period from the programming step to completion can be shortened. Furthermore, the aspect ratio of the contact to the semiconductor substrate can be reduced, the formation of wiring can be stabilized, and the miniaturization of the semiconductor device and the stabilization in manufacturing can be achieved.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a main part plan view showing a pattern layout of an embodiment of the semiconductor device of the present invention. The layout of the semiconductor device shown in FIG. 1A includes an element isolation region 1, a memory cell transistor gate electrode region 2,
The main configuration includes a select line transistor gate electrode region 3, a conductive material layer 4, and a contact pattern region 5 to a drain region. In this configuration, the overlap margin 6 for forming a contact corresponds to the distance between the edge of the conductive material layer 4 and the contact pattern region 5.

The distance 7 between the select line transistor gate electrode regions 3 and 3 at the respective ends of the two select line transistor gate electrode regions 3 arranged two above and below the contact pattern region 5 is: This layout does not limit the superposition for forming the contact, so that it can be formed narrower than the conventional example.

As shown in FIG. 1A, the pattern layout is such that the semiconductor substrate and the drain region between the gate electrodes of the two select line transistor gate electrode regions 3 are connected by a conductive material. The drain region is covered with a conductive material layer 4, and a contact pattern region 5 is arranged on the conductive material layer 4. In addition, a pattern layout is used in which portions corresponding to two DMOS transistors that are used as selection line transistors and that are arranged with a drain region interposed therebetween are arranged in a row in the bit line direction (vertical direction).

FIG. 1B is a sectional view of a main part of the semiconductor device of this embodiment. The cross-sectional structural view of FIG.
FIG. 3 is a vertical cross-sectional view passing through the center of a contact pattern region 5 in the plan view shown in FIG. The cross-sectional structure shown in FIG. 1B is formed in a silicon substrate 8, a memory cell transistor gate electrode 9 and a select line transistor gate electrode 10 made of a gate oxide film and a gate electrode polysilicon, and the silicon substrate 8. A drain diffusion layer 11, a diffusion layer 12 between gate electrodes, an insulating film 13 formed so as to cover the gate electrode, a conductive material layer 14 made of polysilicon, polycide, or the like; , And an aluminum wiring 16 serving as a bit line.

The conductive material layer 14 is formed on the drain diffusion layer 11
And the diffusion layer 12 between the gate electrodes, and continuously covers the select line transistor gate electrode 10 closer to the drain diffusion layer 11 and the diffusion layer 12 between the gate electrodes on both sides thereof. The structure is such that the memory cell transistor gate electrode 9 and the diffusion layer 12 between the gate electrodes on both sides thereof are continuously covered according to information.

The transistors having the select line transistor gate electrode 10 and the memory cell transistor gate electrode 9 covered with the conductive material layer 14 are DMOS transistors, and those not covered are EMOS transistors. That is, a program (storage information) of the read-only memory device can be written by forming the conductive material layer 14. At this time, by forming the conductive material layer 14 also on the drain diffusion layer 11, The conductive material layer 14 for writing the program in the contact portion to the silicon substrate 8 functions as a spacer in the contact portion.

FIG. 3 shows a section viewed from a cross section of an overlap margin 6 for forming a contact and a distance 7 between the select line transistor gate electrode regions 10 at the end.

[0033]

According to the semiconductor device of the present invention, at least one of the source region and the drain region is covered with the conductive material layer, and the contact pattern region is disposed on the conductive material layer. As a result, the read-only memory can be miniaturized and highly integrated as much as the overlay margin for forming the contact increases.
In addition, since the overlay margin is increased, a stable semiconductor device can be manufactured.

According to the second aspect of the present invention, since the inter-gate electrode diffusion layer is covered with the conductive material layer, the source and drain diffusion layers, the inter-gate electrode diffusion layer, and the plurality of memory cell transistor gates are formed. It is possible to improve the characteristics of a plurality of transistors including electrodes, particularly the transconductance of an enhancement transistor, and to improve the characteristics such as amplification factor and switching speed of the enhancement transistor. High-speed operation can be performed stably.

According to the semiconductor device of the third aspect, the conductive material layer covering the inter-gate-electrode diffusion layers on both sides of the transistor gate electrode corresponding to the transistor functioning as the depletion transistor functions as the depletion transistor. Since the connection is made above the transistor gate electrode corresponding to the transistor, the characteristics of the depletion type transistor, particularly the resistance corresponding to the channel can be reduced, and the current driving capability of the depletion type transistor has been significantly improved. The same effect can be obtained, and remarkable improvement and stabilization of the characteristics can be achieved, so that a high-speed semiconductor device can be stably achieved.

According to the semiconductor device of the present invention, at least one of one of the diffusion layers between gate electrodes between two or more selection line transistor gate electrodes and one source region and one drain region. Since one of them is connected by a conductive material layer, miniaturization, high integration, and high-speed operation of a semiconductor device as a read-only memory can be achieved.

According to the semiconductor device of the present invention, the inter-gate electrode diffusion layers on both sides of the select line transistor gate electrode corresponding to the select line transistor functioning as a depletion type transistor are covered with the conductive material layer. A material layer is connected on a select line transistor gate electrode corresponding to a select line transistor that functions as a depletion type transistor, and is disposed across one source region or one drain region and used as a select line transistor. By arranging the portions corresponding to the depletion type transistors in a line in the bit line direction, the characteristics of the selection line transistor can be improved in the same manner as in the above depletion type transistor. Further, regions corresponding to depletion type transistors, which are two select line transistors disposed with the source region or the drain region interposed therebetween, are arranged in a line in the bit line direction, so that a semiconductor device as a read-only memory can be miniaturized. High integration can be realized.

According to the semiconductor device of the present invention, the conductive material layer for program writing is connected on the memory cell transistor gate electrode corresponding to the memory cell transistor functioning as a depletion type transistor, and the program writing is performed. Since the conductive material layer is formed on at least one contact portion of one of the source diffusion layer and the one drain region to serve as a spacer for wiring connection, miniaturization and high integration of the read-only memory are achieved. Not only can be achieved, but also the period from program step to completion can be shortened. Furthermore, the aspect ratio of the contact to the semiconductor substrate can be reduced, the formation of wiring can be stabilized, and the miniaturization of the semiconductor device and the stabilization in manufacturing can be achieved.

[Brief description of the drawings]

FIG. 1A is a plan view of a principal part showing a layout of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a sectional view of the principal part.

FIG. 2A is a main part plan view showing a layout of an example of a conventional semiconductor device, and FIG. 2B is a main part sectional view of the same.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Element isolation region 2 Memory cell transistor gate electrode region 3 Select line transistor gate electrode region 4 Conductive material layer 5 Contact pattern region 6 Overlap margin for contact formation 7 Distance between select line transistor gate electrodes at end 8 Silicon Substrate 9 Memory cell transistor gate electrode 10 Select line transistor gate electrode 11 Drain diffusion layer 12 Diffusion layer between gate electrodes 13 Insulating film 14 Conductive material layer 15 Interlayer insulating film 16 Aluminum wiring

Claims (6)

(57) [Claims] 1. One source diffusion layer and one drain diffusion layer formed below the surface of a semiconductor substrate, a plurality of gate insulating films formed on the surface of the semiconductor substrate, and the source diffusion layer and the drain diffusion layer A plurality of memory cells formed on the plurality of gate insulating films in a state of being arranged in series between
A plurality of memory cell transistors, the plurality of memory cell transistors and at least two select line transistor gate electrodes.
A semiconductor device having a Jisutageto electrode and the gate electrode and the formed under the surface of the semiconductor substrate between the two or more selection line transient <br/> Sutageto electrode diffusion layer, wherein one of the source region and the one <br/> least either be the drain region and the two or more selection line transients
One of the diffusion layers between the gate electrodes between the gate electrodes is covered with a conductive material, and the selection line transistor between them is covered.
A semiconductor device, wherein the conductive material layer is connected on a stud gate, and a contact pattern region for connecting a bit line is disposed on the conductive material layer. 2. The semiconductor device according to claim 1, wherein the inter-gate electrode diffusion layer is covered with a conductive material layer. 3. A transistor gate electrode corresponding to a transistor functioning as a depletion-type transistor among a plurality of transistors including a source diffusion layer and a drain diffusion layer, a diffusion layer between gate electrodes, and a plurality of transistor gate electrodes. 2. The semiconductor device according to claim 1, wherein a conductive material layer covering the inter-gate-electrode diffusion layer on both sides is connected on a transistor gate electrode corresponding to the transistor functioning as the depletion-type transistor. 4. One source diffusion layer and one drain diffusion layer formed below the surface of the semiconductor substrate, a plurality of gate insulating films formed on the surface of the semiconductor substrate, and the source diffusion layer and the drain diffusion layer. A plurality of memory cell transistor gate electrodes and at least two select line transistor gate electrodes formed on the plurality of gate insulating films in a state of being serially arranged between the plurality of memory cell transistor gate electrodes and the plurality of memory cell transistor gate electrodes; A semiconductor device having an inter-gate electrode diffusion layer formed below the surface of the semiconductor substrate between the plurality of select line transistor gate electrodes,
One or more of the inter-gate electrode diffusion layers between the at least one select line transistor gate electrode and at least one of the one source region and the one drain region are connected by a conductive material layer. Semiconductor device. 5. One source diffusion layer and one drain diffusion layer formed below the surface of the semiconductor substrate, a plurality of gate insulating films formed on the surface of the semiconductor substrate, and the source diffusion layer and the drain diffusion layer. A plurality of memory cell transistor gate electrodes and at least two select line transistor gate electrodes formed on the plurality of gate insulating films in a state of being serially arranged between the plurality of memory cell transistor gate electrodes and the plurality of memory cell transistor gate electrodes; A semiconductor device having an inter-gate diffusion layer formed below the surface of the semiconductor substrate between at least two select line transistor gate electrodes, wherein the source diffusion layer and the drain diffusion layer, the inter-gate electrode diffusion layer, A plurality of memory cells each including a plurality of memory cell transistor gate electrodes and at least two select line transistor gate electrodes. Of the memory cell transistor and the two or more selection line transistors, the diffusion layers on both sides of the selection line transistor gate electrode corresponding to the selection line transistor functioning as a depletion type transistor are covered with a conductive material layer. Are connected on the select line transistor gate electrode corresponding to the select line transistor functioning as the depletion type transistor, and are disposed as sandwiching the one source region or the one drain region and used as the select line transistor. A portion corresponding to the two depletion type transistors is arranged in a row in the bit line direction. 6. One source diffusion layer and one drain diffusion layer formed below the surface of the semiconductor substrate, a plurality of gate insulating films formed on the surface of the semiconductor substrate, and the source diffusion layer and the drain diffusion layer. A plurality of memory cell transistor gate electrodes formed on the plurality of gate insulating films in a state of being serially arranged between the plurality of memory cell transistor gate electrodes, and a gate electrode formed under the semiconductor substrate surface between the plurality of memory cell transistor gate electrodes. A semiconductor device having a diffusion layer, wherein the source and drain diffusion layers, the inter-gate electrode diffusion layer, and the plurality of memory cell transistors are read out of a plurality of memory cell transistors. A memory cell transistor that functions as a depletion transistor in response to a dedicated memory program. The inter-gate electrode diffusion layers on both sides of the corresponding memory cell transistor gate electrode are covered with a program writing conductive material layer of the read-only memory, and the program writing conductive material layer functions as the depletion type transistor. A memory cell transistor is connected on a gate electrode corresponding to a memory cell transistor, and the conductive material layer for program writing is connected to the one source diffusion layer and the one.
A semiconductor device characterized in that it is formed on at least one contact portion of any of the drain regions to serve as a spacer for wiring connection.