JPH03283569A - Semiconductor device - Google Patents

Abstract

PURPOSE:To ensure the punch-through pressure resistance of a selective transistor which requires high pressure resistance and prevent miswriting by forming the combination of a first impurity layer which is separated from a drain area and has high impurity concentration and a second impurity layer which is making contact with a source/drain area and has high impurity concentration in the element separating area of the selective transistor. CONSTITUTION:On the surface of an element area p<-> type semiconductor substrate 2, a memory transistor 6 and n<+> type impurity areas 10, 12 and 14 which are the source/drain areas of a selective transistor 8 for the bit selection of the memory transistor 6 are provided. For the memory transistor 6, a floating gate 20 is formed through a gate oxide film 16 on an impurity area 10 and on a p<-> type semiconductor substrate 2 sandwiched by impurity areas 10 and 12. A tunnel 18 composed of a tunnel oxide film is formed between the floating gate 20 and the n<-> type impurity area 10, and a control gate 24 is formed on the floating gate 20 through a space insulating layer 22. For the selective transistor 8, a selective gate 28 is formed on a semiconductor substrate 2 sandwiched by the impurity areas 12 and 14 through a gate oxide film 26.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to semiconductor devices, particularly E'PROMs having floating gates and control gates, and is capable of improving data writing reliability, improving high speed, and reducing costs. The purpose of the present invention is to provide a semiconductor device that is capable of achieving miniaturization of elements and is capable of miniaturizing elements. , a semiconductor device comprising a selection transistor for bit selection of the memory transistor, in which an element N region of the selection transistor is formed separated from at least a drain region of the selection transistor, and an impurity is more impurity-containing than the semiconductor substrate. a first impurity layer of a first conductivity type with a high concentration and an element portion N of the selection transistor;
a second impurity layer of a first conductivity type formed in a region in contact with the source and drain regions of the selection transistor and having an impurity concentration higher than that of the semiconductor substrate; and a third impurity layer of the first conductivity type that is formed separately from at least the drain region of the transistor and has a higher impurity concentration than the semiconductor substrate.

[Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to an E'PROM having a floating gate and a control gate.

[Prior Art] In recent years, non-volatile semiconductor memory devices such as electrically erasable E2PROMs with floating gates and control gates have been developed.
Because they can be easily handled without requiring a power supply to maintain the stored state, their application to memory cards and the like is attracting attention, and there is a demand for increased storage capacity and high speed.

E2PRO with such floating gate and control gate
M requires a high electric field for writing or erasing into the memory section, and requires a high voltage circuit to have a high withstand voltage. In order to achieve such high breakdown voltage characteristics, the following measures have conventionally been taken. In other words, 1. By lowering the impurity EL concentration in the drain region under the floating gate, the junction breakdown voltage is improved. 2. By increasing the thickness of the gate oxide film, the vertical electric field applied to the gate oxide film is reduced. and (2) improving the junction breakdown voltage by lowering the impurity concentration of the channel cut layer in the element isolation region.

However, these measures cause the following problems.

In the case of (2), if the impurity concentration of the drain region is lowered, data writing to the memory transistor becomes shallower. In other words, when data is written by setting the control gate of the memory transistor to 0, applying a high voltage to the drain region, and opening the source electrode, the tunnel is formed due to the extension of the depletion layer under the tunnel region of the drain region. The voltage applied to the oxide film decreases, and the charge on the floating gate becomes drained. Therefore, from the standpoint of data writing reliability, the impurity concentration in the drain region cannot be lowered.

Furthermore, in the case of (2), the high-speed operation of the transistor is sacrificed due to the increase in the thickness of the gate oxide film. Also,
In order to maintain high speed performance, it becomes necessary to separately form gate oxide films for transistors other than memory transistors, which increases the number of manufacturing steps and increases the I-strength.

Furthermore, in the case of (2), although the junction breakdown voltage is improved, the punch-through breakdown voltage of the parasitic transistor whose gate oxide film is the field oxide film in the element isolation region is lowered.

Therefore, as a solution to these problems, a first channel cut layer, which has the same conductivity type as the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate, is separated from at least the drain region of the transistor in the element isolation region of the transistor. and a similar second channel cut layer,
A method has been developed in which the first and second channel cut layers are formed in the element isolation region of the same transistor so as to be in contact with the source and drain regions of the transistor, and these first and second channel cut layers are combined.

That is, as shown in FIG. 5, a field oxide film 4 is formed on a p-type semiconductor substrate 2 to isolate device regions. A memory transistor 6 and a selection transistor 8 for bit selection of the memory transistor 6 are formed in the element region.

In the memory transistor 6, a gate oxide film 16 and an l-channel oxide film are formed on the p- type semiconductor substrate 2 sandwiched between the n+-type impurity regions 10 and 12 forming the source and drain regions and on the n+-type impurity region 12. A floating gate 20 is formed through a tunnel portion 18 consisting of. A control gate 24 is formed on the floating gate 20 with a glabella insulating layer 22 interposed therebetween. Further, in the selection transistor 8, a selection gate 28 is formed on the semiconductor substrate 2 sandwiched between the n+ type impurity regions 12, 14 with a gate oxide film 26 interposed therebetween. Further, the n0-type impurity region 14 is connected to a bit line 32 through an opened contact window 30.

In the device isolation regions 34.36 of the memory transistor 6 and the selection transistor 8, the P+ type channel cut layer 36.40 with a deep junction depth is separated from the n+ type impurity region 12.14 under the field oxide film 4, respectively. P′″ type channel cut layer 62
．． 42 is the n+ type impurity region 1 under the field oxidation M4.
It is formed in contact with 2.14.

In this way, the P+ type channel cut layer 36.40 formed separately from the n+ type impurity region 12.14 and the n
p formed in contact with + type impurity region 12.14
By combining it with the type 1 channel cut layer 62, 42, the reduction in the punch-through breakdown voltage of the parasitic transistor is suppressed and the junction breakdown voltage is improved.

[Problems to be Solved by the Invention] However, in the B2PROM not shown in FIG. Because there is a tunnel portion 18 where n1 type impurity el region j! A! There is a possibility that the vertical electric field applied to the region where the P+ type channel cut layer 12 and the P+ type channel cut layer 62 are in contact with each other deteriorates the junction breakdown voltage. Therefore, it is necessary to keep the tunnel portion 18 away from the element isolation region 34 of the memory transistor 6.

That is, as shown in FIG. 5(a), the width of the memory transistor 6 is defined by the diameter of the tunnel portion 18 and the alignment margin A between the tunnel portion 18 and the element isolation region 34, and its miniaturization is performed. There are restrictions on

Moreover, in order to miniaturize the width of the memory transistor 6,
As shown in FIG. 6(a), mi that does not require a positioning margin has been proposed. However, in this case n+
p+ type channel cut M1 in contact with type impurity region 12
162, as shown in FIG. 6(b), the n+ type impurity region wU12 and P
Since the +-type channel cut layer 62 comes into contact with this layer, it is important to ensure the junction breakdown voltage. When the impurity concentration of the P+ type channel cut layer 62.42 is lowered in an attempt to ensure the junction breakdown voltage, in the element isolation region 38 of the selection transistor 8 where a high breakdown voltage is required, as shown in FIG.
As shown by the arrow, the punch-through breakdown voltage between the n1 type impurity regions 12 and 14 serving as the source and drain regions decreases using the low impurity concentration P+ type channel cut layer 42 as a leak path. If the punch-through withstand voltage of the selection transistor 8 decreases, when writing is performed by applying a high voltage to the drain part, an erroneous write will be made to the unselected memory transistor that shares the bit line 32, resulting in data reliability. sexuality is impaired.

Therefore, the present invention improves the reliability of data writing.
It is an object of the present invention to provide a semiconductor device that can improve high speed performance, reduce costs, and enable miniaturization of elements.

[Means for Solving the Problems] The above problems include a memory transistor having a floating gate and a control gate provided on a semiconductor substrate of a first conductivity type via a gate insulating film, and a method for bit selection of the memory transistor. a first conductivity type semiconductor device formed in an element isolation region of the selection transistor, separated from at least a drain region of the selection transistor, and having an impurity concentration higher than that of the semiconductor substrate; and the source of the selection transistor in the element isolation region of the selection transistor;
a second impurity layer of a first conductivity type formed in contact with the drain region and having a higher impurity concentration than the semiconductor substrate; and a third impurity layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate.

Further, in the above device, a fourth impurity layer of the first conductivity type, which is formed in the element isolation region of the memory transistor in contact with the source and drain regions of the memory transistor, and has an impurity concentration lower than that of the second impurity layer. This is achieved by a semiconductor device characterized by having an impurity layer of.

[Function] That is, the present invention provides, on the one hand, a first impurity layer with a high impurity concentration separated from the drain region and a high impurity layer in contact with the source and drain regions in the element isolation region of the selection I transistor. By forming the second impurity layer in combination with a high concentration second impurity layer, it is possible to ensure the punch-through breakdown voltage of the selection transistor that requires a high breakdown voltage, and to prevent the occurrence of erroneous writing. On the other hand, only a third impurity layer with a high impurity concentration that is separated from the drain region is formed in the element isolation region of the memory transistor, or the third impurity layer is in contact with the source and drain regions. By forming the fourth impurity layer with a low impurity concentration in combination, the junction breakdown voltage of the drain portion of the memory transistor can be ensured.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1(a) is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 1(b) is a sectional view taken along the line XI-XI of FIG. 1(a), and FIG. 1(a) is a sectional view taken along the line X2-X2, and FIG. 1(C) is a sectional view taken along the line Yl-Yl in FIG. 1(a).

A field oxide film 4 is formed on a P-type semiconductor substrate 2 to isolate device regions. On the surface of the p-type semiconductor substrate 2 in the element region, n+-type impurity regions 10, 12, and 14, which form the source and drain regions of the memory transistor 6 and the selection transistor 8 for bit selection of the memory transistor 6, are formed. ing.

In the memory transistor 6, the n″ type impurity region 1
A floating gate 20 is formed on the p- type semiconductor substrate 2 sandwiched between the p-type impurity regions 10 and 10 and the n+-type impurity regions 10 and 12, with a gate oxide film 16 interposed therebetween. Also, this floating gate 2
A tunnel portion 18 made of a tunnel oxide film is formed between the n+ type impurity region 10 and the n + type impurity region 10 . Furthermore, a control gate 2 is placed on the floating gate 20 via an insulating layer 22 between the eyebrows.
4 is formed.

Further, in the selection transistor 8, a selection gate 28 is formed on the semiconductor substrate 2 sandwiched between the lo1 type impurity regions 12 and 14 with a gate oxide film 26 interposed therebetween. Note that this selection gate 28 has a two-layer structure made of, for example, a polysilicon layer, and these two layers are short-circuited at a location other than the cell. Furthermore, n+ type impurity region 1
4 is connected to a bit line 32 through an opened contact window 30.

In the element isolation region 34 of the memory transistor 6, a p+ type channel cut layer 36 with deep junction purity or
It is formed under field oxide film 4 and separated from rl+ type impurity region 12 . In addition, in the element isolation region 38 of the selection transistor 8, a p+ type channel cut layer 40 with a deep junction depth is formed under the field oxide film 4 and separated from the n+ type impurity region 14, and a p+ type channel cut layer 40 is formed separately from the n+ type impurity region 14. A cut layer 42 is formed under field oxide M4 and in contact with n1 type impurity region 14.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be explained using FIG. 2.

After a silicon oxide film 44 is formed on the p-type semiconductor substrate 2 by initial oxidation, an oxidation-resistant film 46, for example, silicon nitride, is grown. Then, using photolithography technology, patterning is performed to remove the silicon nitride film 46 in the element isolation region 34 of the memory transistor and the element isolation region 38 of the selection transistor, so that only the element region 48 of the memory transistor and the element region 50 of the selection transistor are removed. (See Figure 2<a)).

Next, after applying a resist 52 to the entire surface, the resist 52 in the element isolation region 38 and the connecting region 50 of the selection transistor is removed. Then, using the remaining resist 52 and silicon nitride film 46 as a mask, P type impurity ions are implanted into the element isolation region 38 of the selection transistor to form a P+ type channel cut layer 42. Therefore, this P+ type channel cut layer 42 is formed in the element region 5 of the selection transistor.
0 (see FIG. 2(b)).

Next, after removing the resist 52, a resist 54 is applied again to the entire surface, and only a portion of the element isolation regions 34 of the memory 1 to the transistor and the element isolation region 38 of the selection transistor are removed. Then, using the remaining resist 54 as a mask, p-type impurity ions are implanted into a part of the element isolation region 34 of the memory transistor and the element isolation region 38 of the selection transistor, and the P+ type channel cut layer 33 is
Form 6.40. Therefore, these P+ type channel cut layers 36 and 40 have a certain distance from the element region 48 of the memory transistor and the element region 50 of the selection transistor, respectively (see FIG. 2(C)).

Next, after removing the resist 54, the silicon nitride film 4 is removed.
Selective oxidation is performed using 6 as a mask to form field oxidation 1 and 4 in the element isolation region 34 of the memory transistor and the element isolation region 38 of the selection transistor. Then, the silicon nitride R146 is removed (see FIG. 2(d)).

Next, on the P-type semiconductor substrate 2 in the element region 48 of the memory transistor and the element region 50 of the selection transistor,
Gate oxide film 16.2 to thickness 100-500 respectively
form 6. After applying a resist 56 to the entire surface, photolithography is used to apply a resist 56 to the channel region 58 of the memory transistor and the element region 5 of the selection transistor.
o to remain. Then, using the remaining resist 56 as a mask, ions of n-type impurity are implanted into the element region 48 of the memory transistor at a dose of 1X10's to 1X10''cm2, thereby forming an n+-type impurity that forms the source and drain regions of the memory transistor 6. A region 10.12 is formed (see FIGS. 2(e) and (f)). Note that FIG. 2(f)
is a cross-sectional view taken along the line 21-Zl in FIG.
is shown by a broken line.

Next, after removing the resist 56, a part of the gate oxide film 16 of the memory transistor 6 is selectively removed, and a tunnel oxide film is grown to form a tunnel portion 18 on the n+ type impurity region 10. Next, CVD (vapor phase growth)
After growing a polysilicon layer with a thickness of approximately 500 to 2,000 layers over the entire surface using a method, a floating gate 20 is formed on the gate oxide film 16 and tunnel portion 18 of the memory transistor 6 by patterning (see FIG. 2). g), (h)), and Figure 2 (h) is 22-2 in Figure 2 (g).
It is a 2-line sectional view.

After this, the process is similar to that of a normal E2PROM. That is, a control gate 24 made of, for example, a polysilicon layer is placed on the floating gate 20 with an interlayer insulating layer 22 interposed therebetween.
A selection gate 28 is formed to form a memory transistor 6 (see FIGS. 2(i) and 2(j)). In addition, Figure 2 (
J) is a cross-sectional view taken along the line 23-23 in FIG. 2(i), where the first polysilicon layer and the second polysilicon layer forming the selection gate 28 of the selection transistor are short-circuited at a location other than the cell. I'm being forced to do it. This can be done simultaneously with bit line formation and is not shown.

Furthermore, after opening a contact window on the n+ type impurity region 14 of the selection transistor 8, a bit line 32 connected to the n+ type impurity region 14 via this contact window is formed (FIGS. 2(k) and (1)). ), see Figure 2 (j)
is a sectional view taken along the line Z4-24 in FIG. 2(k).

As described above, according to this embodiment, since the p1 type channel cut layer 36 with a deep junction depth is formed in the element isolation region 34 of the memory transistor 6, the field oxide film 4 in the element isolation region 34 is gate oxidized. It is possible to suppress a decrease in the punch-through breakdown voltage of the parasitic transistor formed as a film. Since the P+ type channel cut layer 36 is separated from the n+ type impurity region 12, the junction breakdown voltage of the n+ type impurity region 12 serving as the drain region of the memory transistor 6 can be increased.

This eliminates the need to lower the impurity concentration of the n+ type impurity region 12 as the drain region, so data writing to the memory transistor 6 does not become shallower, thus improving the reliability of data writing. I can do it.

Furthermore, since there is no need to increase the thickness of the gate oxide film 16, the gate oxide film 26 of the selection transistor 8 can be made thinner at the same time, and the gate oxide films of transistors other than the memory transistor 6 can be formed separately. It will no longer form.

Therefore, high-speed operation can be maintained and vJ
It is possible to prevent an increase in costs due to an increase in manufacturing processes.

Furthermore, the alignment margin A between the tunnel portion 18 on the n+ type impurity region 12 as a drain region and the element isolation region 34 is
Not only does it become unnecessary to take a large value for
), this embodiment can also be applied to structures that do not require alignment margins. Therefore, the width of the memory transistor can be miniaturized.

On the other hand, in the element isolation region 38 of the selection transistor 8, the P+ type channel cut layer 40 with a deep junction depth is
Since the P+ type channel cut layer 42 is formed separately from the n+ type impurity region 14 and is formed in contact with the n+ type impurity region 14, the combination of these two P+ type channel cut layers 40 and 42 , it is possible to suppress a decrease in the punch-through breakdown voltage of the parasitic transistor as in the conventional case.

This makes it possible to prevent erroneous writing due to punch-through of the selection transistor.

Note that because the p+ type channel cut layer, which is formed in contact with the n+ type impurity region 12 as in the conventional case, is not formed in the element isolation region 34 of the memory transistor 6, the punch-through breakdown voltage may be lowered. I would like to explain my concerns that this may be the case.

E2PROM reads information by comparing the current flowing through the selected memory transistor with the sense level.
This binary value is achieved by charging the floating electrode positively and turning the memory transistor on, and charging the floating electrode negatively and turning the memory transistor off. However, in the latter case, as long as the current flowing through the memory transistor is below the sense level, some leakage current is not a problem.Moreover, when reading out such information from the selected memory transistor, the charge accumulated in the floating electrode is Since the drain voltage is suppressed to prevent leakage, even if some punch-through current flows through the memory transistor, it is easy to suppress it below the sense level.

Next, a semiconductor device according to another embodiment of the present invention will be described using FIG.

FIG. 3(a) is a sectional view corresponding to FIG. 1(b), and FIG. 3(b) is a sectional view corresponding to FIG. 1(c).

In this embodiment, in the element isolation region 34 of the memory transistor 6 of the embodiment shown in FIG. It is formed. This P type channel cut layer 60 is characterized in that it has a lower impurity concentration than the P+ type channel cut layer 42 formed in contact with the rl'' type impurity region 14 in the element isolation region 38 of the selection transistor 8.

Therefore, in the element isolation region 34 of the memory transistor 6, a p+ type channel cut NA 36 with a deep junction depth is formed under the field oxide film 4 and separated from the n+ type impurity region 12, and a p type channel cut layer 60 is formed under field oxide film 4 in contact with n + type impurity region 12 .

The other configurations are similar to the above embodiment shown in FIG.

Next, a method for manufacturing the semiconductor device shown in FIG. 3 will be explained using FIG. 4.

Since this manufacturing method is also almost the same as the steps shown in FIG. 2, only the different steps will be described.

FIG. 4(a) is similar to FIG. 2(a).

Next, in FIG. 4(b), the element isolation region 38 and the element region 50 of the selection transistor are covered with a resist, and using this resist and the silicon nitride film 46 of the memory transistor as a mask, p is applied to the element isolation region 34 of the memory transistor. A p-type channel cut layer 60 is formed by ion-implanting type impurities. Therefore, this p-type channel cut layer 60 is formed in contact with the element region 48 of the memory transistor.

Subsequently, the element isolation region 34 and the element region 48 of the memory transistor are covered with a resist, and using this resist and the silicon nitride 31146 of the selection transistor as a mask, P type impurity ions are implanted into the element isolation region 38 of the selection transistor to form a P+ type impurity. A channel cut layer 42 is formed. Therefore, this P+ type channel cut layer 42 is formed in contact with the element region 50 of the selection transistor. In this way, the p-type channel cut layer 60 and the P+ type channel cut layer 42 having different impurity concentrations form the device isolation region 34.3 of the memory 1-transistor and selection transistor, respectively.
Formed at 8.

The subsequent steps are performed in the same manner as shown in FIG. 2(c) to (k) above, and the E" PROM as shown in FIG.
form.

In FIG. 4(b), the p-type channel cut layer 60 and the P+ type channel cut layer 42 are formed using separate masks, but the following method may be used.

That is, using the resist covering the element isolation region 34 and element region 48 of the memory transistor and the silicon nitride WA 46 of the selection transistor as a mask, p-type impurity ions are implanted into the element isolation region 38 of the selection transistor. After removing the resist, using the silicon nitride film 46 of the memory transistor and selection transistor as a mask, p-type impurity ions are first implanted into the element region 48 of the memory transistor and second time into the element isolation region 38 of the selection transistor. Then, the p-type channel cut layer 60 and the P+ type channel cut layer 42, which are responsible for the impurity concentration, are respectively connected to the memory transistor and the element isolation region 3 of the selection 1 to transistor.
4.38 may be formed.

As a result, the number of lithography steps can be reduced by just one, and the process can be simplified.

According to this embodiment, the p1 type channel cut layer 36 with a deep junction depth is formed in the element isolation region 34 of the memory transistor 6, and the p type channel cut layer 60 is formed in the element isolation region 34 of the memory transistor 6.
Since they are formed in contact with the + type impurity region 12, the combination of these two p" type channel cut layers 34 and p type channel cut layers 60 can produce the same effects as in the above embodiment.

That is, the P-type chi-le cut layer 60 is connected to the n+ type impurity region 4 in the element isolation region 38 of the selection transistor 8.
p + type channel cut layer 42 formed in contact with
Since the impurity concentration is lower than that of the n+ type impurity region 12 as the drain region of the memory transistor 6, the junction breakdown voltage of the n+ type impurity region 12 as the drain region of the memory transistor 6 can be relatively increased. Furthermore, although the concentration is low, since the P-type channel cut-off layer 60 is formed in contact with the n+-type impurity region 12, the effect of suppressing the decrease in punch-through breakdown voltage is greater than in the above embodiment. Become.

Therefore, the p-type channel cut layer 6
It is desirable to control 0 to a predetermined impurity concentration.

[Effects of the Invention] As described above, according to the present invention, on the one hand, in the element isolation region of the selection transistor, the first impurity layer with a high impurity concentration separated from at least the drain region and the source;
By forming the second impurity layer with a high impurity concentration in contact with the drain region, it is possible to ensure the punch-through voltage of the selection transistor that requires high voltage resistance and prevent the occurrence of erroneous writing. can. On the other hand, only a third impurity layer with a high impurity concentration separated from at least the drain region is formed in the element isolation region of the memory transistor, or this third impurity layer is separated from at least the drain region. tk
By forming a fourth impurity layer with a low impurity concentration in contact with the source and drain regions,
The junction breakdown voltage of the drain portion of the memory transistor can be ensured.

This makes it possible to improve data writing reliability, improve high speed, and reduce costs, as well as to miniaturize elements.

[Brief explanation of drawings]

1 is a diagram showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process diagram showing a method for manufacturing the semiconductor device of FIG. 1, and FIG. 3 is a diagram showing a semiconductor device according to another embodiment of the present invention. FIG. 4 is a process diagram showing a method for manufacturing the semiconductor device shown in FIG. 3, and FIGS. 5 and 6 are views showing conventional semiconductor devices, respectively. In the figure, 2... p-type semiconductor substrate, 4... field oxide film, 6... memory transistor, 8... selection transistor, 10.12 .14...n+ type impurity region, 16
．． 26...Gate oxide film, 20...Floating gate, 18.64...Tunnel portion, 22...Interlayer insulating layer, 24...・Control gate, 28... Selection gate, 30... Contact window, 32... Bit line, 34.38... Element isolation region, 36.40 .4
2.62...P+ layer 36 44...Silicon oxide film, 46...Silicon nitride film, 48.50...Element region, 52.54 .56...Resist, 5.8...
... Channel region, 60 ... P-type channel cut layer. type channel cup

Claims (1)

[Claims] 1. A memory transistor having a floating gate and a control gate provided on a semiconductor substrate of a first conductivity type via a gate insulating film, and a selection transistor for selecting bits of the memory transistor. A semiconductor device comprising: a first impurity layer of a first conductivity type, which is formed in an element isolation region of the selection transistor, separated from at least a drain region of the selection transistor, and has a higher impurity concentration than the semiconductor substrate; formed in the element isolation region of the selection transistor in contact with the source and drain regions of the selection transistor,
a second impurity layer of a first conductivity type having a higher impurity concentration than the semiconductor substrate; and a second impurity layer of a first conductivity type having a higher impurity concentration than the semiconductor substrate; and a third impurity layer of the first conductivity type having a high concentration. 2. The device according to claim 1, wherein a first conductivity type layer is formed in the element isolation region of the memory transistor in contact with the source and drain regions of the memory transistor, and has an impurity concentration lower than that of the second impurity layer. A semiconductor device comprising a fourth impurity layer.