JPS5958868A - Semiconductor non-volatile memory - Google Patents

Abstract

PURPOSE:To stabilize the low voltage write/erase and read characteristic of a floating gate type semiconductor non-volatile memory cell by a method wherein the device is made to off-set structure and to the depletion type, and moreover a tunnel implantation region is provided at the part other than a channel region. CONSTITUTION:Thick field oxide films 12 are provide at the circumferential parts of a P type semiconductor substrate 1 having P<+> type interelement isolation regions 17 as the underlay, and a thin gate insulating film 5 is adhered on the channel region 4 consisting of the substrate 1 surrounded with the fixed oxide films thereof. Then a polycrystalline Si floating gate 6 is adhered extending from the upper part of the film 5 over the upper parts of the films 12, and an insulating film 7' is provided surrounding the floating gate thereof. After then, a polycrystalline Si control gate 8 is formed similarly on the film 7' corresponding to the film 5, a part of the film 7' on the film 12 on one side is removed, a newly thin insulating film 13 is adhered thereto, and a polycrystalline Si implanting gate 8' is adhered thereon. Then N type source.drain regions are formed by diffusion in the substrate 1 on both sides of the gate 6 according to the usual method.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrically writable and erasable nonvolatile memory using MIS type transistors.

Conventionally, this type of memory element includes a so-called MNOS transistor, which uses the nitride film-oxide film interface state for carrier accumulation, and a floating gate transistor, which has a double gate structure with the first gate floating in direct current. However, the retention characteristics of the injected carriers of the MNO8WI transistor are generally worse than those of the floating gate type.
In addition, even in floating gate transistors with a conventional structure, hot carriers are generated due to the high electric field in the drain depletion layer region during operation, and these hot carriers jump into the gate through the oxide film, causing the disappearance of accumulated carriers. Due to this phenomenon, if an attempt is made to reduce the amount of injected carriers by improving the write/erase speed or reduce the write/erase current, there is a drawback that sufficient retention characteristics cannot be obtained. Furthermore, when performing tunnel injection for carrier accumulation, conventional devices use the oxide film on the channel region as the tunnel oxide film, so repeated memory rewrites cause deterioration of the tunnel oxide film, causing fluctuations in the threshold voltage of the transistor. This has the disadvantage that retention characteristics deteriorate. As a method to overcome the first drawback mentioned above, there is a so-called offset structure transistor in which the floating gate is separated from the drain and source regions to prevent injection of hot carriers and improve retention characteristics. High voltage is required to form an inversion layer in the region, making it unsuitable for low voltage operation. Furthermore, the offset structure does not provide any improvement for the second drawback.

The present invention was made in view of the above-mentioned circumstances, and an object thereof is to provide a method that improves the retention characteristics of a semiconductor nonvolatile memory, enables low-voltage operation, and enables high-speed writing and erasing operations. do.

The nonvolatile memory transistor used in the present invention has an offset structure only on the drain side of the floating gate to improve retention characteristics, and at the same time enables low voltage read operation by using a depletion type normally-on structure. Instead of using a gate oxide film on the channel region, we used an oxide film on the floating gate to prevent deterioration of the gate oxide film on the channel region, and to ensure stable transistor characteristics even after repeated carrier writing. It is something.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a specific example of a nonvolatile memory transistor according to the present invention, in which the source, channel region,
This figure shows a cross section including a drain, where 1 is a semiconductor substrate, 2 and 3 are diffusion layers of the opposite conductivity type to the substrate, and each represents a source and a drain. 4 is a channel formed by ion-implanting impurities of a conductivity type opposite to that of the substrate, and plays the role of providing conduction between the drain and source of the transistor when there are no accumulated carriers in the floating gate 6. When carriers of the same type as the majority carriers in the channel are injected into the floating gate, a depletion layer or an inversion layer and a depletion layer are induced in the channel region, resulting in an extremely small channel conductance and a so-called cut-off. It is designed to give rise to a condition. This condition occurs only in the channel region under the floating gate, but if a part of the channel is completely off, it is sufficient to cut off between the drain and the source, so the problem caused by the offset structure is eliminated. Nothing happens. Therefore, there is no need to determine the entire distance from the drain of the floating gate by accurate positioning, so there is an advantage that manufacturing is easy. Injection of carriers into the floating gate is performed using the control gate and injection gate shown at 8 and 8' in FIG. In FIG. 2, the same numbers as in FIG. 1 are used to indicate the same areas as in FIG. 1. The same applies to the figures shown below.

Now, since the control gate and the floating gate, and the injection gate and the floating gate are capacitively coupled through the thin insulating films 7 and 13, respectively, when the appropriate full voltage is applied to the control gate and the injection gate, the floating gate has a capacitance between each gate. A potential according to
m If the size is sufficient to cause tunneling, a tunneling current will flow through the insulating film. However,
In order to efficiently inject carriers, it is important that tunneling occur only in one side of the insulating film, that is, in the part 13, and for this purpose, the electric field applied to the insulating film 13 is larger than the electric field applied to the insulating film 7. must satisfy the following conditions. On the other hand, since the injection voltage increases in proportion to the thickness of the insulating film 13, it is necessary to make the insulating film 13 thinner in order to lower the carrier writing and erasing voltages. Increasing the capacitance of the floating gate reduces the voltage divided between the gates, making it difficult to perform implantation efficiently. The area and insulating film thickness of the injection gate region relative to the floating gate are expressed as Sl and tl+The area and insulating film thickness of the control gate region relative to the floating gate t82
and t2, and assuming that the insulating film quality in both regions is the same, the electric field E1 applied to the insulating film in the first region (injection gate region) and the electric field E2 applied to the insulating film in the second region are relative to the injection voltage V. It is expressed by the following formula.

El-V/(tt +(ss/sx) t2) +E
2=V/('t2+(82/81) tt)...
...(1) E1/E2 ”=” 2/31
・・・・・・(2) Therefore 82)
By using Sl, carrier injection efficiency can be increased by injecting carriers only from the injection gate.
In addition, by setting tl<t2, it is possible to reduce the injection voltage. FIGS. 1 and 2 show such examples, and the planar layout of the transistors is shown in FIG. 3. In the figure, the dotted line represents one transistor cell, 3 is the bit line of the diffusion layer, and 11 is the bit line of the diffusion layer.
8 is a word line, 8 is a control line, 14 is a write/erase line, and the 8° 14 line is used for writing and erasing the cell, and the 3 and 11 lines are used for reading the cell. Now, to explain the case of an n-channel device as an example, in order to change the memory from the ``0'' state to the ``1'' state, it is necessary to inject electrons into the floating gate. Apply negative voltage to the gate. At this time, it is desirable that the word line be at ground potential, but this is not always necessary. Electrons are injected from the injection gate to the floating gate, creating a negative potential and becoming a 1" state. To erase, conversely, when a positive voltage is applied to the injection gate, electrons flow 1,000... ~ injected from the gate. tunnels to the gate, the accumulated carriers disappear, and the state returns to "0".For reading, the word line and bit line are left in a floating state, and the word line of the memory cell at the read address is lowered to ground potential. All you have to do is read the information from the bit line.

Another method for writing and erasing is a method that does not use a negative potential. That is, taking advantage of the structure in which carriers are always injected from the injection gate side, in the case of writing, electrons are injected into the floating gate by setting the injection gate to the ground potential and applying a positive voltage to the control gate. 1″ state. In this case as well, it is preferable that the word line etc. be at the same potential as the control gate, but this is not always necessary. In the case of erasing, the control gate is set to the ground potential, and a positive voltage is applied to the injection gate to cause accumulated carriers to flow out. When reading data, it is sufficient to set the control gate to the ground potential and then read the data in the same manner as described above.

Next, the method for manufacturing the memory transistor of this embodiment will be explained in the case of an n-channel transistor. First, element isolation regions 12 are formed on a p-type semiconductor substrate using selective oxidation technology.

At this time, a p-type impurity such as boron is implanted in advance under the element isolation region by ion implantation technology, and the entire channel stopper layer 17 between the resistors is formed. Next, apply a photoresist, remove only the resist on the region that will become the channel using IJ lithography technology, and form a channel by ion-implanting n-type impurities such as phosphorus from above, and remove the resist. Figure 4 (al
become that way. FIG. 4 corresponds to the cross section of FIG.

Next, a gate electrode material is grown, and a region that will become the floating gate 6 is patterned using IJ lithography technology, and a thin oxide film 7' of about 100 to 500 A is grown on the floating gate 4. Then, patterning is performed to etch and remove only the oxide film in the implanted region (FIG. 4(b)). Next, an extremely thin oxide film of 100X or less is grown to form a tunnel oxide film 13 gold, and then a second gate electrode material is grown and buttered to form the injection gate 8' and the control gate 8 ( Figure 4(C)). FIG. 5 shows a cross section corresponding to FIG. 1 at this time. After this, a thin oxide film is grown on the second gate electrode material, and then n-type impurities such as p-arsenic are implanted into the substrate using ion implantation technology using the first and second gate electrode materials as masks. Form an n region that will become the source and drain with
After depositing about μ, contact openings are made to the source diffusion layer region and injection gate region, metal wiring materials such as aluminum are deposited thereon, and patterning is performed using lithography technology to form word lines and write/erase lines. to obtain the structure shown in FIGS. 1 and 2. When this mounting method is used, a gate oxide film is formed on the channel, and an oxide film is formed under the control gate.

A feature of this method is that the design of the transistor is easy because the thickness of each tunnel oxide film under the injection gate can be set separately.

The above has been described for the case of n-channel devices, but p-channel devices have been described above.
It is clear that the present invention is similarly applicable to channel elements. Further, the gate insulating film 5. Control gate insulating film 7. Even if an insulating film other than an oxide film is used for part or all of the injection gate insulating film 13, the effects of the present invention will not be lost in any way.

As explained above, the present invention provides a floating gate type semiconductor nonvolatile memory cell with an offset structure and a depression type, and also provides a tunnel injection region in a place other than a channel region, thereby improving retention characteristics and lowering voltage writing/erasing. , it is possible to realize stabilization of read characteristics, and furthermore, since the retention characteristics are good, write/erase current or write/erase time can be reduced, thereby realizing faster write/erase times.

[Brief explanation of drawings]

FIG. 1 shows an example of a cross-sectional view of the nonvolatile memory of the present invention, FIG. 2 shows an example of a cross-sectional view of the memory of the present invention viewed from a different direction from FIG. 1, and FIG. An example of a plan layout diagram on a memory integrated circuit is shown in Figure 4 (fat to (
C1 is a step-by-step cross-sectional view of the nonvolatile memory manufacturing process of the present invention, and FIG. 5 is a step-by-step cross-sectional view of the memory manufacturing process of the present invention, viewed from a different direction from FIG. 4. In the figure, 1... semiconductor substrate, 2...
...Source diffusion layer region, 3...Drain diffusion layer region, 4...Channel region, 5...
・Gate insulating film, 6...Floating gate)
, 7.7'... Insulating film, 8... Control gate, 8'... Injection gate, 9... Insulating film, 10...・PEG film, 11...metal wiring, 12...field insulating film, 13...
...Insulating film, 14...Metal wiring, 15...
. . . contact region, 16 . . . contact region, 17 . . . impurity region for element isolation. Fig. Z Fig. 1 ◇ Fig. 3 (C) Fig. 4 S

Claims (5)

[Claims] (1) A semiconductor nonvolatile memory characterized in that a MIS (metal-insulator-semiconductor) transistor has an offset region between a gate electrode and a drain diffusion layer, and the MIS transistor is a depression type transistor. . (2) The semiconductor nonvolatile memory according to claim (1), characterized in that a floating gate is used as the storage region. (3) Claim (2) in which carriers are injected not from the channel region but from a tunnel injection region provided on the floating gate.
Semiconductor nonvolatile memory described in Section 1. (4) Claim (3) characterized in that the insulation film between the control gate and the injection gate provided on the floating gate is thicker between the control gate and thinner between the injection gate and the control gate. Semiconductor nonvolatile memory described in Section 1. (5) The semiconductor nonvolatile memory according to claim (3), wherein the area of the control gate and injection gate provided on the floating gate is large for the control gate and small for the injection gate. .