JPH03253072A - Semiconductor device - Google Patents

Abstract

PURPOSE:To give a nonvolatile memory element, for EPROM use, which is effective in a high integration by a method wherein a single-crystal Si layer is formed on an insulating film formed on an Si substrate and a MOSFET is formed on it. CONSTITUTION:An insulating film which is composed of an oxide Si film 2 and a nitride Si film 3 is formed on a P-type Si single-crystal substrate 1; a P-type single-crystal Si layer 4 is formed on it; an SOI structure is formed. A drain region 5 and a source region 6 which are composed of an N-type semiconductor are formed in parts on the surface of the layer 4. A gate electrode 3 composed of a poly-Si film is formed, via a gate insulating film 7 composed of an oxide film, on the surface of the layer 4 between the regions 5 and 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective for use in a storage element structure of an electrically programmable and erasable nonvolatile memory.

[Prior art] Electrically programmable and erasable nonvolatile memory (EEPR)
OM) is already known, for example IE DM
82, pp. 733-736.1982. A known structure using a P-type wheel crystal silicon substrate will be described with reference to FIG. 4.

In the same figure, MO8FET for selection and MNOS (Met
al N1tride Oxide Sem1c
A well-known E
The circuit configuration and cross-sectional structure of a typical memory element portion of an EPROM are shown.

Selective MO on a part of the surface of the P-type wheel crystal silicon substrate 1
N-type semiconductor regions 15a and 15b are formed to become the source and drain regions of S F E T Q s, and next to them, an N-type semiconductor region 15c is formed to become the source region of the memory element Qm.
is formed, and the N-type semiconductor region 15b is MO3FE for selection.
It also serves as the source of TQs and the drain of memory element Qm. A gate electrode 18 made of polysilicon is formed on the surface of the P-type wheel crystal silicon substrate l between the N-type semiconductor regions 15a and 15b with a gate insulating film 17a made of a silicon oxide film interposed therebetween. In addition, the N-type semiconductor region 15
A gate insulating film 17b, a silicon nitride film 17c, and a gate electrode 19 are formed on the surface of the P-type wheel crystal silicon substrate 1 between b and 15c. The silicon oxide film as the gate insulating film 17b in this memory element part is formed thinner than other parts, and when a high voltage is applied to the gate electrode 19, the gate insulating film 17b and the silicon nitride film 17c are connected by tunneling effect. Writing is performed by injecting electrons into traps near the interface. On the other hand, erasing is performed by applying an electric field opposite to that of writing and injecting holes into the traps.

[Problems to be Solved by the Invention] In the EEPROM having the above-described structure, one memory cell is formed by the gate electrode 18 which is a selection gate and the pole 19 which is a write/erase gate.

Therefore, two transistors are required for each memory cell, which poses a problem of hindering high integration.

The present invention has been made in view of the above points, and its main purpose is to provide a structure of a nonvolatile memory element for EEPROM that is effective for high integration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, S OI (Silicon on In
At least one insulating film is formed on a single-crystal silicon substrate using a 5ulator structure, a single-crystal silicon layer is formed on the insulating film, and a MOSFET is formed on the surface of this single-crystal silicon layer.

[Function] In an element having such a structure, a high voltage is applied between the source and drain and between the gate and the substrate of the MO3FET, and a substrate current is passed to trap holes generated by impact ionization in the insulating film. to be captured. Then, the threshold voltage of the MOS FET changes due to the substrate effect of the captured carriers.

Therefore, reading can be performed by setting the selection level between the two threshold voltages, so one transistor can serve both as a selection MOS FET and a storage element, which is different from the conventional writing/erasing transistor. The selection MO8FET that was paired with the EEPRO is no longer required, and the EEPRO
High integration of M can be achieved.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the principle of the semiconductor device of the present invention.

Reference numeral 1 designates a P-type wheel crystal silicon substrate, on which insulating films 2 and 3, such as a silicon oxide film and a silicon nitride film, are sequentially formed.

Reference numeral 4 denotes a P-type wheel crystal silicon layer, which is formed on the silicon nitride film 3. This provides a type of SOI
The structure is constructed.

A drain region 5 of an N-type semiconductor and a source region 6 of an N-type semiconductor are formed in a part of the surface of the P-type wheel crystal silicon layer 4.

Further, a gate electrode 8 made of polysilicon is formed on the surface of the P-type crystal silicon layer 4 between the drain region 5 and the source region 6 with a gate insulating film 7 made of a silicon oxide film interposed therebetween. .

Next, the operation of the semiconductor device of the present invention will be explained.

The potentials applied to the P-type wheel crystal silicon substrate 1, the drain region 5, the source region 6, and the gate electrode 8 are Vsub and VD.
, VS, and Vc, writing, erasing, and reading can be performed by setting the following potential conditions.

(1) When writing Vsub<OV, OV<VG<VD, Vs=OVFor example, if Vsub=-5V, VD=:8V, and VG=3V, impact ionization occurs in the high electric field region near the drain region 5. Electron/hole pairs are generated. Electrons are drawn in the direction of the drain region 5, while holes flow into the P-type wheel crystal silicon layer 4, but the - part has a negative substrate potential, that is, Vsub=
It is pulled to -5V and is implanted into the silicon nitride film 3. The injected holes are captured by traps existing near the interface with the P-type wheel crystal silicon layer 4, and writing is performed by being captured.

Further, as the holes are captured by the traps, the threshold voltage decreases due to the so-called substrate effect.

(2) When writing is prevented Vsub(OV, VD=OV, Vs=OV.

V G) OV In cells to which writing is not performed, that is, non-selected bit cells, if V D = OV, impact ionization will not occur even if the gate potential VG is a positive potential.

Therefore, no holes are captured in the traps of the silicon nitride film 3, and writing is not performed.

(3) When erasing Vsub=OV, VD<OV, Vs==OV.

V c, = OV For example, if V D = −5 V, electrons flow from the drain region 5 toward the P-type wheel crystal silicon substrate 1 and are injected into the silicon nitride film 3 . The injected electrons and the holes captured in the traps recombine, and the holes captured in the traps disappear, resulting in erasure.

In this case, all memory cells connected to one bit line can be erased simultaneously.

(4) When erasing is prevented Vsub=OV, VD=OV, VS=OV.

V G = OV In cells where erasing is not performed, that is, non-selected bit cells, if V D = OV, electrons are not injected into the silicon nitride film 3 . Therefore, the holes captured in the traps of the silicon nitride film 3 retain their state and are not erased.

(5) When reading Vsub=OV, VD>0. VS=OV.

VG=Vt.

For example, if V D = 5 V and V c is set to Vt (threshold voltage at which holes are trapped in the traps of the silicon nitride film 3), the transistor is in the on state in the written bit. That is, it becomes conductive and a drain current flows. On the other hand, in unwritten bits, the transistors are in an off state and no drain current flows.

This is because, as mentioned in the section (1) during writing, in the written bit, the threshold voltage decreases due to the so-called substrate effect as holes are captured in traps. .

In other words, the threshold voltage Vt of the written bit is lower than the threshold voltage Vth of the unwritten bit, so the gate potential vG during reading is set to the threshold voltage Vt reduced due to the substrate effect. By doing so,
It can be determined whether writing has been done or not. At this time, if writing has been performed, the transistor is turned on.

On the other hand, if writing is not performed, gate potential VG (=
Vt) is lower than the threshold voltage Vth, so the transistor does not turn on. Note that the gate potential vG may have a value between the low threshold voltage Vt and the high threshold voltage Vth.

Next, the manufacturing process of the above-mentioned semiconductor device will be explained based on FIG.

First, the surface of the P-type wheel crystal silicon substrate l is thermally oxidized, and 1
After forming a silicon oxide film 2 with a thickness of about 000A, a silicon nitride film 3 of about 500A is formed thereon by CVD or the like.
deposit. Thereafter, a portion of the silicon oxide film 2 and silicon nitride film 3 is opened by etching to form a window 50 for recrystallization. On top of that, CVD polysilicon or amorphous silicon 4O of about 500OA is applied.
It is formed by the D method or the sputtering method. Furthermore, on top of that
A protective silicon oxide film 60 is formed by CVD. The process up to this point is shown in FIG. 2(A).

Next, after this, polysilicon or amorphous silicon 40 is single-crystallized using the single crystal in the window 50 as a seed by a zone melting method to obtain single-crystal silicon. Thereafter, the silicon oxide film 60 is removed, and a P-type impurity, for example, boron, is implanted into the exposed single crystal silicon layer at a depth of about 10'' cm. And MOSFET
The periphery of the area where the wafer is to be formed is removed by etching.

The process up to this point is shown in FIG. 2(B).

Next, using a known isolation technique between elements, the portions removed by etching are filled with silicon oxide 7o. This silicon oxide 70 electrically insulates the P-type crystal silicon substrate l and the P-type crystal silicon layer 4.

The process up to this point is shown in FIG. 2(C).

Furthermore, a MOSFET is formed using a known technique. In FIG. 2(D), source electrodes 20.20. A state in which gate electrodes 8, 8 and a drain electrode 3° are formed is shown. The source electrodes 20 and 20 are formed of polysilicon, the gate electrodes 8 and 8 are formed of polysilicon on the gate insulating film 7 to form a word line, and the drain electrode 3O is formed of aluminum to form a data line. . The source/drain regions 6 and 5 are N-type semiconductor regions, and the impurity is, for example, arsenic or phosphorus, with a concentration of about 10 cm. In the figure, although not particularly limited, silicon oxide 70.
2 in a region separated from surrounding elements by 70.
Bit's memory is reflected.

In the above embodiment, the insulating film formed between the P-type crystal silicon substrate 1 and the P-type crystal silicon layer 4 was composed of two layers: silicon oxide M2 and silicon nitride film 3. As long as it has a trap for trapping holes, it may be a single layer of silicon oxide film, silicon nitride film, or an insulating film made of other insulators, or it may be composed of three or more layers by combining these. Also good.

Further, the substrate potential may be applied by forming an electrode on the back surface of the P-type wheel crystal silicon substrate l, but the SOI structure is formed only in the center of the chip, that is, the P-type wheel crystal silicon layer 4 is formed only in the center. Then, an electrode may be formed on the exposed peripheral portion of the substrate surface to apply a substrate potential.

Further, in the above embodiments, a case has been described in which a P-type wheel crystal silicon substrate l is used, but an N-type single crystal silicon substrate may also be used. In this case, the applied potential is reversed, and the carriers injected into the silicon nitride film 3 are electrons during writing and holes during erasing.

Furthermore, a substrate having an SOI structure can also be realized using a known bonding technique. In that case, the window 50 serving as a growth nucleus for the upper single crystal silicon layer 4 and the silicon oxide 70 for insulation become unnecessary.

The semiconductor device configured as described above has the following effects.

That is, at least one insulating film is formed on a single-crystal silicon substrate, a single-crystal silicon layer having the same conductivity type as the single-crystal silicon substrate is formed on the insulating film, and on this single-crystal silicon layer, Writing is performed by forming a MOSFET, and holes generated by impact ionization are captured in traps existing in the insulating film, and erasing is performed by injecting electrons into the insulating film.
Because reading is performed based on the phenomenon that the threshold voltage of the FET changes, the selection MOS FET that was previously paired with the write/erase transistor is no longer required, and one transistor forms one memory cell. By this action, it is possible to achieve high integration of the EEPROM.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, the periphery of the active region may be separated for each element, or only the silicon nitride film may be patterned, leaving a pad-shaped silicon nitride film under each gate.

Also, like the conventional EEPROM memory cell, the selection M
The O3FET and the memory element of the present invention may be used together.

In the following explanation, the invention made by the present inventor will be mainly explained in terms of electrical writing and
I explained the structure of erasable non-volatile memory,
The present invention is not limited thereto, and can be used in general semiconductor integrated circuit devices having memory elements.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

Due to the effect that one memory cell is formed by one transistor, the EEPROM can be highly integrated.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the semiconductor device of the present invention, and FIG.
(D) is a process diagram showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps; FIG. 3 is a partial plan view of a semiconductor device according to an embodiment of the present invention; ) is a circuit configuration diagram showing an example of the configuration of a memory cell using the conventional MNO3 structure, and FIG. 4(B) is a sectional view showing an example of the element structure. l...P type wheel crystal silicon substrate (conductive substrate), 2
... Silicon oxide film (insulating film), 3... Silicon nitride film (insulating film), 4... P-type wheel crystal silicon layer (semiconductor layer), 5... Drain region, 6 . . . Source region, 7 . . . Gate insulating film, 8 . . . Gate electrode. Figure 1 Figure 2 (A) sub

Claims (1)

[Claims] 1. At least one insulating film is formed on a conductive substrate, a semiconductor layer is formed on the insulating film, and a semiconductor region serving as a source/drain region is formed on the surface of the semiconductor layer. A semiconductor device characterized in that a gate insulating film is formed on a surface of a semiconductor layer between these semiconductor regions, and a gate electrode is formed on the gate insulating film. 2. The insulating film has a two-layer structure of a silicon oxide film formed on the conductive substrate and a silicon nitride film formed on the silicon oxide film. semiconductor devices. 3. The semiconductor device according to claim 1 or 2, wherein the conductive substrate and the semiconductor layer are made of single crystal silicon.