JPH04299573A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To erase data en bloc by applying an 'L' potential to control gates of all NAND cells in a selected cell block and a substrate, and applying a program.pulse of 'H' level to bit lines, a source side selection gate, and a drain side selection gate. CONSTITUTION:An element isolation insulating film is formed on a P-type Si substrate 11. In an element region, a floating gate 14 of a first layer polycrystalline silicon film which gate turns to an electron storage layer is formed via a first gate insulating film 13. On the floating gate 14, a control gate 19 of a second layer polycrystalline silicon film is formed via a second gate insulating film 18. 'L' level potential is applied to the control gates of all NAND cells in a selected cell block and the substrate. A program.pulse of 'H' level is applied to a drain side selection gate and a source side selection gate. Thereby data are eliminated en block.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM) constructed using memory cells of a MOS transistor structure having a charge storage layer and a control gate.

0002

2. Description of the Related Art In the field of EEPROM, memory cells having a MOS transistor structure having a floating gate and a control gate are widely known, and advances in processing technology have led to significant progress in miniaturization and high integration of devices. As the miniaturization of devices progresses, the gate insulating film thickness is becoming extremely thin due to the scaling law. Recently, in such microscopic devices, deterioration of memory cells due to hot holes generated in the diffusion layer near the gate electrode has become a problem when a high voltage is applied to the drain, that is, when data is erased. Furthermore, in the data erasing sequence of the NAND type EEPROM, data must be erased in order from the memory cells farthest from the bit line, resulting in a complicated data erasing sequence.

0003

[Problem to be solved by the invention] As described above, fine EE
In PROMs, deterioration of memory cells due to hot holes generated in the diffusion layer near the gate electrode during data erasing has become a problem. It is an object of the present invention to provide a NAND type EEPROM memory cell and its operating method that solve these problems. [Structure of the invention]

0004

[Means for solving the problems] NAND according to the present invention
As a memory cell constituting a nonvolatile semiconductor memory device, a source layer and a drain layer are formed on a semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate are further laminated in this order. The memory cell has a structure in which electrical rewriting is possible by transfer of charge between the charge storage layer and the drain layer, and the memory cell has a source layer,
When an "L" level potential is applied to the substrate and control gate. This semiconductor memory device has a drain breakdown voltage that is higher than the voltage applied to the drain when reading the memory cell and lower than the voltage applied to the drain layer when extracting charges from the charge storage layer to the drain layer. As an erase operation method when applied to a NAND cell configured with a plurality of serially connected selection gate transistors and a selection gate transistor connected in series on the drain side and the source side,
All NANDs in at least the selected cell block
Apply "L" level potential to the control gate and substrate of the cell, and at least all NAs in the selected cell block
By applying an “H” level program pulse to the bit line, source side selection gate, and drain side selection gate of the ND cell, the data of all NAND cells in at least the selected cell block is erased at once. It is characterized by

[0005]

[Operation] In conventional nonvolatile semiconductor memories, deterioration of memory cells due to hot holes generated in the diffusion layer near the gate electrode has become a problem during data erasing. This deterioration phenomenon is caused by holes becoming hot holes due to a strong lateral electric field at the end of the drain diffusion layer, and an electron trap level being formed by injection of these hot holes into the gate oxide film. Therefore, this deterioration phenomenon can be suppressed by reducing the strong lateral electric field at the end of the drain diffusion layer during data erasing. Therefore, as shown in the present invention, when an "L" level potential is applied to the substrate and the control gate, the drain breakdown voltage is made higher than the voltage applied to the drain when reading the memory cell, and the charge storage layer is By making the voltage lower than the voltage applied to the drain layer when extracting charges to the drain layer, the deterioration phenomenon during data erasing of the nonvolatile semiconductor memory is suppressed by the following effect. In other words, when data is erased, that is, when a high voltage is applied to the drain, the memory cell punches through, charging the source and increasing the source potential, thereby reducing the strong lateral electric field at the edge of the drain diffusion layer. It becomes possible to do so. In addition, a NAN configured by connecting a plurality of semiconductor memory devices in series and selecting gate transistors connected in series on the drain side and the source side.
Conventionally, as an erase operation of a D-structure cell, an "L" level potential is applied to the control gate of a selected memory cell in the NAND cell, the substrate, and the selection gate transistor on the source side, and the selected NAND cell is "H" on the bit line of
” By applying a program pulse of
All the data in the selected NAND cell is erased by erasing the data in the selected memory cell in the NAND cell and performing this operation in order starting from the memory cell on the drain side. However, by using the memory cell of the present invention, when data is erased, that is, when a high voltage is applied to the bit line source, drain side selection gate, and source side selection gate, the memory cell punch-through allows each memory Since the diffusion layer and the cell part of the cell are charged, all N in at least the selected cell block is charged.
Applying “L” level potential to the control gate, substrate, and source side selection gate transistor of the AND cell, and
By applying an “H” level program pulse to the bit lines of all NAND cells in the selected cell block, all NAND cells in the selected cell block are
It becomes possible to erase cell data all at once.

[0006]

[Examples] Examples of the present invention will be described below.

FIGS. 1(A) and 1(B) are a plan view showing the EEPROM memory cell structure of one embodiment and its A-
It is an A' sectional view. An element isolation insulating film (not shown) is formed on a P-type Si substrate 11, and a floating gate 14 serving as a charge storage layer is formed by a first layer polycrystalline silicon film in the element region via a first gate insulating film 13. ing. floating gate 1
4 partially extends over the element isolation region. A control gate 19 made of a second layer polycrystalline silicon film is further formed on the floating gate 14 with a second gate insulating film 18 in between. Using these gate electrodes as a mask, impurity ions are implanted to form an N+ type layer 23 which will become a source and a drain. A P-type layer (not shown) is formed entirely below the element isolation insulating film as a channel stopper layer.

FIG. 2 shows potential distributions when an "L" level potential is applied to the substrate and control gate for the embodiment of the present invention and the conventional example. The device parameters of the embodiment of the present invention and the conventional example are that the gate oxide film thickness is 1
10 A, the diffusion layer dose is 1E15 cm-2, and the effective channel length is 0.1 A in the case of the embodiment of the present invention.
2 μm, and 1.6 μm in the conventional example. When a high voltage is applied to the drain, unlike the conventional example, in the case of the embodiment of the present invention, the depletion layer from the drain extends into the source, charging the source and raising the potential of the source. It is possible to reduce the strong electric field in the lateral direction at the edge.

FIG. 3 shows an NA in which a plurality of memory cells are connected in series and selection gate transistors T1 and T2 are connected in series on the drain side and the source side.
A plurality of ND cells are arranged in a matrix, and the NAND
A method of erasing data in a nonvolatile semiconductor memory device in which a drain at one end of a cell is connected to a bit line and a control gate of each memory cell is connected to a word line will be described. In this operation method, as shown in FIG. 4, the control gates and substrates of all NAND cells in the selected cell block are
” level potential and apply a “H” level program pulse to the bit lines, drain side selection gates, and source side selection gates of all NAND cells in the selected cell block. This erases the data of all NAND cells in a cell block at once. By erasing data at once in this way, it is possible to erase data at high speed without having to erase data sequentially as in the conventional case. In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

0010

As described above, according to the present invention, the deterioration phenomenon of memory cells due to hot holes generated in the diffusion layer near the gate electrode during data erasing is suppressed, resulting in high density and high reliability. Non-volatile semiconductor memory can be provided. Furthermore, as an erase operation method for a NAND structure cell configured by connecting a plurality of nonvolatile semiconductor memories of the present invention in series and selecting gate transistors connected in series on the drain side and the source side, data is erased all at once. It became possible.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an EEPROM memory cell structure according to an embodiment of the present invention and a sectional view thereof taken along line AA'.

FIG. 2: Substrates for embodiments of the present invention and conventional examples;
and a comparison diagram showing potential distribution when an “L” level potential is applied to the control gate.

[Fig. 3] A plurality of NANAD cells each having a plurality of memory cells connected in series and a selection gate transistor connected in series on the drain side and the source side are arranged in a matrix, and one end side of the NAND cell is arranged in a matrix. 1 is a circuit diagram showing a data erasing operation method of a nonvolatile semiconductor memory device configured such that a drain is connected to a bit line and a control gate of each memory cell is connected to a word line. FIG.

FIG. 4 is a waveform diagram illustrating the present invention.

[Explanation of symbols]

11 P-type Si substrate 1
3 Gate insulating film 14 Floating gate
18 Gate insulating film 19 Control gate 23 N+ type layer serving as source and drain

Claims (1)

[Claims] 1. A source layer and a drain layer are formed on a first conductivity type semiconductor substrate by a second conductivity type impurity diffusion layer, and further include a first gate insulating film, a charge storage layer, and a second gate. In a memory cell in which a composite film and a control gate are laminated in this order and electrical rewriting is possible by transfer of charge between the charge storage layer and the drain layer, an "L" level potential is applied to the substrate and the control gate. A non-volatile semiconductor whose drain breakdown voltage is higher than the voltage applied to the drain when reading a memory cell and lower than the voltage applied to the drain layer when extracting charge from the charge storage layer to the drain layer. A NAN in which a plurality of memory devices are connected in series and selection gate transistors are connected in series on the drain side and the source side.
In a nonvolatile semiconductor memory device in which a plurality of D cells are arranged in a matrix, the drain at one end of the NAND cell is connected to a bit line, and the control gate of each memory cell is connected to a word line, The control gates of all NAND cells in the cell block were connected to “L” on the substrate.
” level potential and applying an “H” level program pulse to the bit lines, source side selection gates, and drain side selection gates of all NAND cells in at least the selected cell block. A nonvolatile semiconductor memory device characterized in that data of all NAND cells in a cell block that has been erased is erased at once.