JP2005184028A - Nonvolatile storage element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To erase a tunnel of a nonvolatile storage element in which an insulating charge trap film is used as a charge storage area, and to prevent characteristics from being deteriorated. <P>SOLUTION: The nonvolatile storage element includes a source region (8), a drain region (7) formed in a semiconductor region and a channel region (9) between them, a first insulating film (2) provided on the channel region, a semiconductor film (3) formed on the first insulating film, a second insulating film (4) formed on the semiconductor film, and a gate electrode (6) provided on the second insulating film. The second insulating film is a charge trap film. Charge is stored by capturing by the trap of the second insulating film. The silicon film is a film in which silicon particles (88) are dispersed. Even if an operation for discharging the charge held by the charge trap film is performed by the tunnel, a state that an electron is retained in the first insulating film in the gate insulating film can be prevented. Erasure by hot hole implantation is not required. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electrically erasable and writable nonvolatile memory element, and a semiconductor integrated circuit having the nonvolatile memory element, for example, a nonvolatile memory using a nonconductive charge trapping film as an information holding region, Further, the present invention relates to a technique effective when applied to a microcomputer or a data processor having such a nonvolatile memory on-chip.

  In recent years, as a memory device for storing data and data constituting a program, a nonvolatile storage device capable of electrically erasing stored data collectively in a predetermined unit and electrically writing data can be used. Flash EEPROMs (hereinafter referred to as flash memories) are attracting attention. In flash memory, memory cells are composed of electrically erasable and writable nonvolatile memory elements. Data and programs once written in the memory cells are erased, and new data and programs are rewritten in the memory cells. (Programming) is possible.

  Conventionally, a charge storage region of a flash memory has been performed by storing electrons in a floating gate made of a polysilicon film and electrically insulated from the surroundings. This electron accumulation operation, so-called write operation, is generally hot electron injection, and the erase operation for releasing the accumulated electrons to the outside of the floating gate is performed by a tunnel current passing through the gate oxide film. When writing and erasing are repeated, a trap level is formed inside the gate oxide film, and the trap level at the interface between the substrate and the gate oxide film increases. In particular, the former has an essential problem of deteriorating charge retention characteristics, that is, retention characteristics after rewriting.

  As a method for solving the above problems, a method of using a non-conductive charge trapping film for charge accumulation of an EEPROM has been proposed in recent years. For example, U.S. Patent No. 5,768,192, U.S. Patent No. 5,966,603, U.S. Patent No. 6,011,725, U.S. Patent No. 6,180,538, And B. Eitan et al., “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cell”, International Conference on Solid State Devices and Materials, Tokyo, 1999. For example, in US Pat. No. 5,768,192, a silicon nitride film 133 sandwiched between insulating films 132 and 134 such as a silicon oxide film, so-called ONO (Oxide) is shown in FIG. / Nitride / Oxide) is used as a gate insulating film, and 0 V is applied to the source 137 and an appropriate positive voltage is applied to the drain 136 and the control gate 135 to turn on the transistor, and hot electrons generated in the vicinity of the drain 136 are generated. This is a method of writing by implanting and trapping electrons in the silicon nitride film 133. In this charge accumulation method, compared with a method in which charge accumulation is performed on a polysilicon film which is a continuous conductive film, the electron traps in the silicon nitride film 133 are discontinuous and discrete, and therefore, a part of the oxide film 132 is formed. Even when a charge leakage path such as a pinhole occurs, all of the accumulated charges are not lost, and the retention characteristic is essentially strong.

  Further, in US Pat. No. 6,011,725, as shown in FIG. 25, the locality of hot electron injection is used to determine the vicinity of the drain 136 and the source 137. A so-called multi-value cell technology is disclosed in which 2-bit information is realized in one memory cell by independently controlling charge accumulation at two locations.

  Further, US Pat. No. 5,966,603 discloses a method of forming an ONO film, for example, forming an ONO structure by forming an ON laminated film on a substrate and then oxidizing the upper portion of the silicon nitride film. In addition, it is disclosed that oxygen is introduced into a silicon nitride film by adding an oxidation process after an ONO laminated film is formed on a substrate, thereby improving the retention characteristics of the memory cell. Further, US Pat. No. 6,180,538 discloses a method for forming an ONO film by a rapid thermal chemical vapor deposition (Rapid Thermal Chemical Vapor Deposition), and an oxide film deposition temperature is 700 to 800 ° C. In addition, it is described that the thickness of the oxide film is 5 to 15 nm.

US Pat. No. 5,768,192 US Pat. No. 6,011,725 US Pat. No. 5,966,603 US Pat. No. 6,180,538

  In the above known example, the erase operation for extracting the electrons trapped in the silicon nitride film is performed by tunnel emission to the substrate, source, or drain side, or neutralization of charges by hot hole injection from the vicinity of the source or drain. Has been done by. For example, according to B. Eitan et al., “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cell”, International Conference on Solid State Devices and Materials, Tokyo, 1999. The erase operation is performed by applying 7 V, −3 V to the control gate, and 3 V to the source, and injecting hot holes due to the interband tunneling phenomenon generated in the substrate near the drain into the silicon nitride film.

  The present inventor has found that there are some problems in the conventional memory cell employing the above-described operation method, as schematically illustrated in FIG.

  The first problem is that in the erasing operation by hot hole injection, the holes injected in the erasing operation pass through the oxide film 132, so once captured in the oxide film 132, the mobility of the holes is small. Therefore, it becomes a hole trap and becomes a factor that deteriorates the retention characteristic after rewriting, that is, the charge retention characteristic.

  The second problem is that in the erasing operation by hot hole injection, the hole injection in the erasing operation generates a trap level at the interface between the semiconductor substrate 131 and the oxide film 132, remarkably deteriorates the subthreshold characteristic, and is turned off. -Increase leakage current. This increases the drain leakage current when reading the stored information of the memory cell in the erased state, causing read data inversion failure, so-called read failure.

  The third problem is that even if an electron is emitted to the substrate side by a tunnel current to solve the problem caused by hot hole injection, the distribution center of the charges trapped in the nitride film is sufficiently far from the substrate. It is difficult to erase. In short, in order to obtain the required write characteristics, the nitride film needs to have a relatively large thickness so that a relatively large number of electrons are held in the nitride film and the held charges are not easily released. Therefore, there is a limit to the electron emission from the substrate due to the tunnel current.

  The fourth problem is that there is a problem that is newly generated when an erase operation is not performed by hole injection but electron emission to the substrate 131 side by a tunnel current. For example, when −10 V is applied to the control gate 135 and +10 V is applied to the substrate 131, electrons trapped in the silicon nitride film are emitted to the substrate 131 side by a tunnel current through the oxide film 132. The remaining of the holes injected into the oxide film 132 immediately below the silicon nitride film region where no electron trap exists in the vicinity of the source 137 becomes more prominent than in the oxide film 132 directly below the silicon nitride film region where the trap exists. The accumulated amount of holes in the oxide film increases as rewriting is repeated, and only the channel region in the vicinity of the source 137 is partially depleted (threshold voltage is in a depletion state). This state corresponds to a state in which the channel length is shortened, and various characteristics, write characteristics, read current, and the like of the memory cell vary depending on the number of rewrites, and the characteristic variation is greatly deteriorated.

  An object of the present invention is to prevent a situation in which electrons remain unconsumably in a gate insulating film even when an electron emission operation such as an erasing operation for a nonvolatile memory element using an insulating film such as a silicon nitride film for charge retention is performed by a tunnel. It is an object to provide a nonvolatile memory element and a semiconductor integrated circuit that can be blocked.

  Another object of the present invention is that even if an electron emission operation such as an erasing operation for a nonvolatile memory element using an insulating film such as a silicon nitride film for charge retention is performed by an FN tunnel, the channel region is slightly offset. It is an object of the present invention to provide a nonvolatile memory element and a semiconductor integrated circuit that can prevent a situation in which holes accumulate and cause characteristic deterioration.

  Still another object of the present invention is to eliminate the need for hot electron injection for electron emission in a nonvolatile memory element that uses an insulating film such as a silicon nitride film for charge retention. An object of the present invention is to provide a nonvolatile memory element and a semiconductor integrated circuit capable of suppressing or mitigating an increase in subthreshold leakage current due to deterioration and rewriting.

  Another object of the present invention is to provide a nonvolatile memory element that can easily reduce the chip occupation area of a nonvolatile memory cell that uses an insulating charge trapping film as a charge storage region.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A nonvolatile memory element according to the present invention includes a source region (8), a drain region (7) formed in a semiconductor region (1), a channel region (9) therebetween, and the channel region. A first insulating film (2) provided thereon, a semiconductor film (3) provided on the first insulating film, a second insulating film (4) provided on the semiconductor film, A third insulating film (5) provided on the second insulating film; and a gate electrode (6) provided on the third insulating film. The trap density of the second insulating film is higher than the trap density of each of the first insulating film and the third insulating film. The trap density at the interface between the semiconductor film and the second insulating film is higher than the trap density of the second insulating film. Electrons trapped in the trap are tunneled through the first insulating film.

  In the nonvolatile memory element, since a charge holding function by a trap having a deep energy level (interface trap) formed at the interface between the semiconductor film and the second insulating film is added, information storage is conventionally performed. Therefore, it is possible to reduce the thickness of the second insulating film that is responsible for charge retention. Even with the thin film, it is guaranteed that the memory element as a whole retains a necessary amount of electrons. When the electrons trapped in the second insulating film and its interface are tunneled, the second insulating film is thinned, so the electrons trapped in the traps in the bulk of the second insulating film can be easily The semiconductor film reaches the semiconductor film and flows through the semiconductor film and the first insulating film as a tunnel current and is emitted. The electrons trapped at the interface between the second insulating film and the semiconductor film are detrapped by the electric field against the trap level, and the detrapped electrons flow from the semiconductor film as a tunnel current through the first insulating film. Released. Since the interface between the semiconductor region and the second insulating film is formed close to the first insulating film through which a tunnel current flows, the electrons trapped therein pass through the second insulating film during the tunnel emission. I don't need it. Compared with the case where such an interface state is formed on the gate electrode side to function, the means of the present invention can easily perform an electron emission operation such as an erase operation.

  Therefore, even when an electron emission operation such as an erasing operation for a nonvolatile memory element using an insulating film such as a silicon nitride film for charge holding is performed by the tunnel effect, a situation in which electrons are not consumed in the second insulating film is prevented. be able to.

  In the erasing operation, it is not necessary to perform hot hole injection from the channel region side, so that all the problems caused by hot hole injection can be solved. First, generation of hole traps in the first insulating film on the channel region can be suppressed. Second, the subthreshold characteristic is not deteriorated due to the generation of the interface state between the channel region and the first insulating film. Accordingly, it is possible to prevent the deterioration of the write characteristics and the read characteristics. Furthermore, subthreshold leakage is reduced, contributing to low power consumption.

  Furthermore, the electrons trapped in the trap at the interface between the semiconductor film and the second insulating film, which mainly hold electrons for information storage, are detrapped and detrapped in the semiconductor film that is not an insulator. The electrons behave like free electrons in the semiconductor film. In writing by hot electron injection, even if electrons are trapped in an interface trap near the drain, the detrapped electrons are not concentrated near the drain, and holes do not remain in the first insulating film near the source. Also in this respect, deterioration of the writing and reading characteristics in the nonvolatile memory element is prevented.

  In the nonvolatile memory element, when electrons are injected, for example, a potential higher than a potential applied to a source region is applied to the drain region and the gate electrode to turn on the channel region, and Electrons are captured by the second insulating film and the interface between the semiconductor film and the second insulating film by hot electrons generated in the vicinity of the drain region. Further, when electron tunneling is performed, for example, a potential higher than the potential applied to the gate electrode is applied to the semiconductor region, and the interface portion between the semiconductor film and the second insulating film and the precursor second The electrons trapped in the insulating film are extracted as a tunnel current through the first insulating film.

  As a desirable mode, the trap density at the interface between the semiconductor film and the second insulating film is preferably higher than the trap density at the interface between the second insulating film and the third insulating film. The semiconductor film may be thinner than the second insulating film.

  As one specific form, the first insulating film may be a silicon oxide film, the semiconductor film may be a silicon film, the second insulating film may be a silicon nitride film, and the third insulating film may be a silicon oxide film. The first insulating film is a silicon oxide film, the semiconductor film is a silicon film, the second insulating film is a metal oxide film, and the third insulating film is a silicon oxide film. The silicon film is a polysilicon film. As a desirable mode, impurities are introduced into the polysilicon film. Instead of the polysilicon film, a film in which polysilicon particles (88) are dispersed in an insulating film may be adopted as the silicon film.

  [2] A semiconductor integrated circuit according to the present invention includes a first insulating film (2) on a channel region (9) between a source region (8) and a drain region (9) formed in a semiconductor region (1). ), A semiconductor film (3) provided on the first insulating film, a second insulating film (4) provided on the semiconductor film, and a third insulation provided on the second insulating film. A memory array having a plurality of nonvolatile memory elements each having a film (5) and a gate electrode (6) provided on the third insulating film; and electron injection and electrons passing through the first insulating film And a memory control circuit for controlling a threshold voltage of the nonvolatile memory element by the tunnel emission. The trap density of the second insulating film is higher than the trap density of each of the first insulating film and the third insulating film. The interface portion trap density between the semiconductor film and the second insulating film is higher than the trap density of the second insulating film.

  This semiconductor integrated circuit is a non-volatile memory or a data processor having a non-volatile memory on-chip. This semiconductor integrated circuit exhibits the effects obtained by the nonvolatile memory element described in item [1].

  As a desirable mode, it is preferable to integrally form semiconductor films of a plurality of non-volatile memory elements adjacent to each other in the direction in which the gate electrodes are shared and extend. If the semiconductor film is divided in units of memory cells, an interval of at least the minimum processing dimension is required between the nonvolatile memory elements, and the chip occupation area increases. In this respect, it is possible to contribute to a reduction in the area occupied by the chip of the memory array or an increase in the storage capacity. Furthermore, electrons detrapped by the erase operation can move in a common semiconductor film among a plurality of nonvolatile memory elements, and tunnel emission of the detrapped electrons is performed in units of a common gate electrode, thereby making it nonvolatile. Variation in erasing characteristics between memory elements can be reduced.

  As a specific form, the memory control circuit applies a potential higher than a potential applied to the source region to the drain region and the gate electrode in response to an instruction of an electron injection operation, thereby The electrons are turned on, and electrons are captured by the interface between the semiconductor film and the second insulating film and the second insulating film by hot electrons generated in the vicinity of the drain region. The memory control circuit applies a potential higher than a potential applied to the gate electrode to the semiconductor region in response to an instruction of an electron tunneling emission operation, so that the semiconductor film and the second insulating film The electrons trapped in the interface portion and the precursor second insulating film are extracted as a tunnel current through the first insulating film.

  The semiconductor region may be formed on a third insulating film (42) formed on the semiconductor substrate. In short, it is possible to adopt a TFT (Thin Film Transistor) structure as the device structure of the nonvolatile memory element. At this time, the semiconductor region may be formed of a silicon film, for example. For example, n-type impurities are introduced into the source / drain regions formed therein, and p-type impurities are introduced into the channel region. As one desirable mode when adopting the TFT structure, a common source wiring region (54) is formed in the semiconductor substrate (41) of the third insulating film, and the common source wiring region is formed on the third insulating film. The connection is made to the source regions of the plurality of memory cells through the formed connection holes (53H). The connection hole can be formed by removing the third insulating film in a self-aligned manner with respect to a sidewall spacer (52) formed on the side wall of the gate electrode.

  [3] The nonvolatile memory element utilizes an interface state between a semiconductor film such as a polysilicon film and a second insulating film such as a silicon nitride film. As another aspect, a silicon nitride film is provided on the first insulating film above the channel region, and a portion of the silicon nitride film near the first insulating film has a silicon-rich composition. Specifically, the nonvolatile memory element is provided on the channel region, the source region (8), the drain region (7) and the channel region (9) therebetween formed in the semiconductor region, respectively. A first insulating film (2), a second insulating film (90) provided on the first insulating film, a third insulating film (5) provided on the second insulating film, And a gate electrode (6) provided on the third insulating film. The second insulating film is a silicon nitride film in which the value of Si / N is increased closer to the first insulating film (90A) than to the third insulating film (90B). The trap density of the second insulating film is higher than the trap density of each of the first insulating film and the third insulating film. Electrons trapped in the trap are tunneled through the first insulating film.

  The silicon-rich portion (90A) of the silicon nitride film replaces the trap function at the interface between the semiconductor film (polysilicon film) and the second insulating film (silicon nitride film) described in item [1]. Basically, it has the same effect as that.

  [4] As an invention of substantially the same viewpoint as the invention using the interface state between the semiconductor film and the insulating film, the semiconductor integrated circuit includes a first insulating film (on the channel region (9) of the semiconductor region ( 2), an intermediate film (3) formed on the first insulating film, a non-conductive charge trap film (4) formed on the intermediate film, and on the charge trap film A non-volatile memory element having a second insulating film (5) formed and a gate electrode (6) formed on the second insulating film is provided. The trap density of the charge trapping film is higher than the trap density of each of the first insulating film and the second insulating film. The trap density at the interface between the intermediate film and the charge trap film is higher than the trap density at the interface between the charge trap film and the second insulating film and higher than the trap density of the charge trap film. In the nonvolatile memory element, information is written by trapping injected electrons in the trap, and information is erased by tunneling emission of electrons trapped in the trap through the first insulating film. Is done.

  As an invention substantially the same as the invention in which a part of the silicon nitride film is silicon-rich to increase the trap density, the semiconductor integrated circuit includes a first insulating film (2) formed on the channel region (9) of the semiconductor region. A second insulating film (90) formed on the first insulating film, a third insulating film (5) formed on the second insulating film, and on the third insulating film A non-volatile memory element having a gate electrode (6) formed is provided. The trap density of the second insulating film is higher than the trap density of each of the first insulating film and the third insulating film. The trap density of the second insulating film is higher near the first insulating film (90A) than near the third insulating film (90B). In the nonvolatile memory element, information is written by trapping the injected electrons in the trap, and information is erased by tunneling the electrons trapped in the trap through the first insulating film. Is called.

  [5] The nonvolatile memory element according to another aspect of the present invention using the interface state between the semiconductor film and the insulating film includes a source region (8), a drain region (7) formed in the semiconductor region, and those A channel region (9) between the gate insulating film, a gate insulating film (10) provided on the channel region, and a gate electrode (6) provided on the gate insulating film. The gate insulating film includes a first insulating film (2), a semiconductor film (3) provided on the first insulating film, a silicon nitride film (4) provided on the semiconductor film, and the silicon It consists of a second insulating film (5) provided on the nitride film. Electrons trapped in the gate insulating film by hot electron injection can be tunneled through the first insulating film.

  From this point of view, there is no positive mention of the trap density, but since the combination of the semiconductor film and the silicon nitride film is clearly stated, a deep interface state is formed at the interface, and the interface state is the tunnel emission destination. As described above, the silicon nitride film that has been responsible for charge storage for information storage can be made thinner as described above, and the electron emission operation such as the erase operation is performed by the tunnel effect. However, it is possible to prevent a situation in which electrons remain in the silicon nitride film without being consumed. Since it is not necessary to perform hot hole injection from the channel region side, generation of hole traps in the first insulating film on the channel region can be suppressed, and the interface state between the channel region and the first insulating film can be suppressed. The subthreshold characteristic is not deteriorated due to the occurrence. Further, the detrapped electrons do not concentrate near the drain, and no holes remain in the first insulating film near the source.

  The same applies to the case where a metal oxide film having a high dielectric constant such as a tantalum pentoxide film or a titanium oxide film is employed instead of the silicon nitride film.

  A non-volatile memory element according to another aspect of the present invention using a silicon nitride film having a silicon-rich portion includes a source region (8), a drain region (7) formed in the semiconductor region (1), and a portion therebetween. Channel region (9), a gate insulating film (10A) provided on the channel region, and a gate electrode (6) provided on the gate insulating film. The gate insulating film includes a first insulating film (2), a silicon nitride film (90) provided on the first insulating film, and a second insulating film (5) provided on the silicon nitride film. Become. The silicon nitride film has a larger Si / N value closer to the first insulating film (90A) than to the second insulating film (90B). In the nonvolatile memory element, electrons trapped in the gate insulating film by hot electron injection can be tunneled through the first insulating film. From this point of view, there is no positive mention of the trap density, but since it is clearly stated that a silicon nitride film with a silicon-rich part facing the semiconductor region is used, the trap density of the silicon-rich part is relative. As a result, the same effect as described above is obtained.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  An interface state is formed by an insulating film such as a semiconductor film and a silicon nitride film near the insulating film on the tunnel emission side, and this is responsible for charge retention for information storage, and an insulating film such as a silicon nitride film Made it possible to reduce the film thickness. This prevents a situation in which electrons remain in the gate insulating film even when an electron emitting operation such as an erasing operation for a nonvolatile memory element using an insulating film such as a silicon nitride film for charge retention is performed by a tunnel. Can do.

  Since an insulating film such as a silicon nitride film that forms an interface state is not an insulating film but a semiconductor film, an electron such as an erase operation for a nonvolatile memory element that uses an insulating film such as a silicon nitride film for charge retention Even if the emission operation is performed by a tunnel, it is possible to prevent a situation in which holes accumulate in a part of the channel region and cause characteristic deterioration.

  Since it is not necessary to inject hot holes to release retained electrons, the deterioration of charge retention characteristics after rewriting of a nonvolatile memory element using an insulating film such as a silicon nitride film for charge retention, and the subthreshold leakage current caused by rewriting Increase can be suppressed.

  By integrating an insulating film such as a semiconductor film or silicon nitride film that forms the interface state in the direction of the gate electrode, the cell area of a nonvolatile memory that uses a non-conductive charge trapping film as a charge storage region can be reduced. Reduction is possible.

<< First Memory Cell Structure Having Semiconductor Film and Nitride Film >>
FIG. 1 illustrates a first basic memory cell structure having a semiconductor film and a nitride film in a longitudinal section. The nonvolatile memory cell MC1 shown in FIG. 1 includes an n-type source region 8, an n-type drain region 7, and a channel region sandwiched between the source region 8 and the drain region 7 in a semiconductor region, for example, a p-type semiconductor region 1. 9 A gate insulating film 10 provided on the channel region 9 and a gate electrode (also simply referred to as a control gate) 6 made of a conductive film provided on the gate insulating film 10 are provided. The gate insulating film 10 is provided on the first insulating film, for example, the silicon oxide film 2, the semiconductor film provided on the first insulating film 2, for example, the polysilicon film 3 that is a silicon film, and the semiconductor film 3. The second insulating film is constituted by a silicon nitride film 4 as a non-conductive charge trapping film, for example, and a third insulating film such as a silicon oxide film 5 provided on the silicon nitride film 4. The channel region 9 means a region where a conductive channel can be formed.

  The trap density of the silicon nitride film 5 is higher than the trap density of the silicon oxide films 2 and 5. The trap density at the interface between the polysilicon film 3 and the silicon nitride film 4 is higher than the trap density of the silicon nitride film 4.

Although not particularly limited, the control gate 6 is composed of a polysilicon film having a thickness of 100 nm doped with phosphorus having a concentration of 3 × 10 ²⁰ / cm ³ . Although not particularly limited, the silicon oxide film 2 has a thickness of 5 nm, the polysilicon film 3 has a thickness of 4 nm in which phosphorus having a concentration of 3 × 10 ²⁰ / cm ³ is ion-implanted, the silicon nitride film 4 has a thickness of 5 nm, silicon The oxide film 5 has a thickness of 5 nm. The effective thickness of the gate insulating film 10 is 13.5 nm in terms of silicon oxide film. The gate insulating film having the conventional ONO (oxide film / nitride film / oxide film) structure described with reference to FIG. 24 is, for example, sequentially formed as a 5 nm silicon oxide film, a 10 nm silicon nitride film, and a 5 nm silicon oxide film. The thickness is 15 nm in terms of silicon oxide film. In the memory cell according to the present invention, the silicon nitride film 4 is halved compared to the conventional case, and the polysilicon film 3 is thinner than the silicon nitride film 4. The control gate 6 may be composed of a polysilicon film 3 and a laminated film of a silicide film or a refractory metal formed on the polysilicon film 3. Although not particularly limited, the control gate 6 is formed integrally with the word line WL.

  FIG. 2 illustrates a detailed structure of the nonvolatile memory cell of FIG. 1 in a plan view. The active regions 11 of the memory cells are arranged in a line-and-space manner in the horizontal direction, that is, in parallel with a predetermined interval, and the control gates 6 are arranged in a line-and-space manner in the vertical direction perpendicular thereto. The active region 11 is a semiconductor region related to impurity introduction to be a source region, a drain region, and a channel region. Contact holes 13a and 13b for making contact (electrical connection) to the drain region and the source region, and a connection hole 14 for connecting the bit line 15 arranged in parallel to the active region 11 and the contact hole 13a on the drain region are provided. Is arranged. The contact hole 13b extends in the direction of the control gate 6.

  FIG. 3 illustrates an A-A ′ cross section in FIG. 2. In FIG. 3, on the channel region 9 between the drain region 7 and the source region 8 of the semiconductor region 1, a silicon oxide film 2, a polysilicon film 3, a silicon nitride film 4, a silicon oxide film 5, a control gate 6, and An insulating film 28 is stacked. One contact hole 13 a formed on the drain region 31 and the other contact hole 13 b formed on the source region 8 are disposed through the insulating film 33 and formed through the insulating film 36. One contact hole 13 a and the bit line 15 are connected via the connection hole 14. Contact plugs 34 and 35 are formed in the contact holes 13 a and 13 b, and connection plugs 37 are formed in the connection holes 14. The contact plugs 34 and 35 and the connection plug 37 are made of a wiring material such as aluminum, tungsten, or polysilicon.

  FIG. 4 illustrates a B-B ′ cross section in FIG. 2. In FIG. 4, a silicon oxide film 2 is formed in the surface region of the active region isolated by the element isolation region 22 in the semiconductor base region 1, and a polysilicon film 3, a silicon nitride film 4, and a silicon oxide film 5 are formed thereon. The control gate 6 and the insulating film 28 are sequentially stacked, and the bit line 15 is disposed above the insulating film 33 and the insulating film 36.

  The write operation to the nonvolatile memory cell MC1 is performed by hot electron injection as in the conventional case. The erase operation is performed by tunnel emission over the entire surface of the channel region 9. For example, when electron injection is performed, a potential higher than the potential applied to the source region 8 is applied to the drain region 7 and the gate electrode 6 to turn on the channel region 9, and the drain region 7 Many electrons are captured at the interface between the polysilicon film 3 and the silicon nitride film, and the electrons are captured by traps in the bulk of the silicon nitride film 4. Further, when electron tunneling is performed, for example, a higher potential than that applied to the gate electrode 6 is applied to the semiconductor region 1, so that an interface portion between the polysilicon film 3 and the silicon nitride film 4 is applied. The electrons trapped in the bulk of the silicon nitride film are extracted from the polysilicon film 3 into the channel region 9 as a tunnel current in the silicon oxide film 2.

  In the nonvolatile memory cell MC1, since the trap density at the interface between the polysilicon film 3 and the silicon nitride film 4 is higher than the trap density at the interface between the silicon nitride film 4 and the silicon oxide film 5, the injected hot Most of the electrons are trapped at the interface between the polysilicon film 3 and the silicon nitride film 4. Needless to say, electrons are also trapped in the trap in the bulk of the silicon nitride film 4. As described above, in the nonvolatile memory cell MC, a charge holding function by a deep energy level trap (interface trap) formed at the interface between the polysilicon film 3 and the silicon nitride film 4 is added. Therefore, it is possible to reduce the thickness of the silicon nitride film that has been responsible for holding charges for storing information. Even when the film thickness is reduced, it is guaranteed that a necessary amount of electrons are held as the memory cell MC. That is, since the trap density which is the density of the interface trap between the polysilicon film 3 and the silicon nitride film 4 is high, a charge holding function can be added.

  In the erasing operation, with respect to the electrons trapped at the interface between the polysilicon film 3 and the silicon nitride film 4, the first step of once detrapping into the polysilicon film 3 and the detrapped electrons pass through the silicon oxide film 2. This is performed by the second step that is emitted to the semiconductor region 1 by the tunneling current. Electrons trapped in the bulk of the silicon nitride film 4 pass through the polysilicon film 3, pass through the silicon oxide film 2 as a tunnel current, and are emitted to the semiconductor region 1. When tunneling emission of electrons trapped in the bulk of the silicon nitride film 4 and its interface, the silicon nitride film 4 is thinned, so that the electrons trapped in the bulk of the silicon nitride film 4 can be easily obtained. It reaches the polysilicon film 3 and flows through the silicon oxide film 2 as a tunnel current and is emitted to the semiconductor region 1. Electrons trapped at the interface between the silicon nitride film 4 and the polysilicon film 3 are detrapped by the polysilicon film 3 by an electric field against the trap level, and the detrapped electrons use the silicon oxide film 2 as a tunnel current. It flows and is discharged. Since the trap that forms the interface state is formed on the silicon oxide film 2 side, the electrons trapped therein do not need to pass through the silicon nitride film 4 in the tunnel emission. Compared with the case where such an interface state is formed on the side of the gate electrode 6 to function, the means of the present invention can easily perform an electron emission operation such as an erase operation.

  Therefore, even when an electron emission operation such as an erasing operation for the nonvolatile memory using the silicon nitride film for charge holding is performed by the tunnel effect, it is possible to prevent a situation in which electrons are left in the silicon nitride film 4 without being consumed.

  In the erasing operation, it is not necessary to perform hot hole injection from the channel region 9 side, so that generation of hole traps in the silicon oxide film 2 on the channel region 9 can be suppressed, and the channel region 9 and the silicon oxide film can be suppressed. 2 does not deteriorate the subthreshold characteristic due to the generation of the interface state with 2. Accordingly, it is possible to prevent the deterioration of the write characteristics and the read characteristics. Furthermore, subthreshold leakage is reduced, contributing to low power consumption.

  Further, the electrons trapped in the interface trap between the polysilicon film 3 and the silicon nitride film 4 for information storage are detrapped in the polysilicon film 3 which is not an insulator, and the detrapped electrons are trapped in the polysilicon film 3. Acts like a free electron. Even if many electrons are trapped in the interface trap in the vicinity of the drain 7 by writing by hot electron injection, the detrapped electrons are not concentrated in the vicinity of the drain region 7 and holes are formed in the silicon oxide film 2 in the vicinity of the source region 8. Does not remain. Also in this respect, deterioration of the writing and reading characteristics in the nonvolatile memory element is prevented.

<< Second Memory Cell Structure Having Semiconductor Film and Nitride Film >>
FIG. 5 illustrates a second basic memory cell structure having a semiconductor film and a nitride film in a longitudinal section. The nonvolatile memory cell MC2 shown in the figure is formed on the relatively thick silicon oxide film 42 on the semiconductor substrate 41 by TFT technology. On the silicon oxide film 42, a channel region 43 made of polysilicon doped with p-type impurities such as boron, and a drain region 31 and a source region 32 made of polysilicon doped with n-type impurities such as arsenic are formed. Is done. On the channel region 43, the gate insulating film 10 composed of the silicon oxide film 2, the polysilicon film 3, the silicon nitride film 4, and the silicon oxide film 5 is formed as described above. The gate electrode 6 and the insulating film 28 are provided on the gate insulating film 10. The drain region 31 and the bit line are connected by the contact plug 34 in the contact hole 13a and the connection plug 37 in the connection hole 14, and the source region 32 is connected to the contact plug 35 in the contact hole 13b.

  Even in this TFT structure, the erase / write operation is basically the same as the memory cell structure of FIG. The source region 32 is set to a circuit ground potential, an appropriate positive potential is applied to the drain region 31 and the control gate 6, the channel region 43 is turned on, and hot electrons generated in the vicinity of the drain region 31 are injected. Thus, writing is performed by capturing electrons in the interface portion between the polysilicon film 3 and the silicon nitride film 4 and in the bulk of the silicon nitride film 4. An appropriate negative potential is applied to the control gate 6, an appropriate positive potential is applied to the drain region 31, and electrons trapped at the interface between the polysilicon film 3 and the silicon nitride film 4 are removed from the polysilicon film. 3 is detrapped, the electrons trapped in the bulk of the silicon nitride film 4 are guided to the polysilicon film, and the electrons in the polysilicon film 3 are extracted from the silicon oxide film 2 to the drain region 31 by the tunnel current. I do.

  Similarly to the first memory cell structure, in the second memory cell structure, hot holes are not injected into the silicon oxide film 2 in the erase operation. The generation of the charge trap level can be suppressed, the deterioration of the subthreshold characteristic due to the generation of the interface level between the channel region 43 and the silicon oxide film 2 due to hot hole injection can be eliminated, and the semiconductor film Since the polysilicon film 4 is commonly connected to a plurality of memory cells arranged in the extending direction of the control gate 6, tunnel electron emission in the erasing operation is performed in units of the control gate 6. Variations in erasing characteristics can be significantly reduced.

<< Third Memory Cell Structure Having Semiconductor Film and Nitride Film >>
FIG. 6 illustrates a third basic memory cell structure having a semiconductor film and a nitride film in plan view. The nonvolatile memory cell MC3 shown in the figure is configured as a TFT similar to that in FIG. 5, and the same components as those described in FIG.

  In the figure, the active region 11 of the memory cell is arranged in a line-and-space form in the horizontal direction, and the control gate 6 is arranged in a line-and-space form in the vertical direction perpendicular thereto, and contacts the drain region. A contact hole 13 for processing the common source line, a mask pattern 16 for processing the common source line, and a connection hole 14 for connecting the bit line 15 arranged in parallel to the active region 11 and the contact hole 13 on the drain region. .

FIG. 7 illustrates a CC ′ cross section in FIG. 6. FIG. 8 illustrates a DD ′ cross section in FIG. 6. In each figure, a semiconductor film doped with, for example, boron having a thickness of 50 nm and a concentration of 2 × 10 ¹⁸ / cm ³ on a semiconductor substrate 41 via a silicon oxide film 42 which is an insulating film having a thickness of 100 nm. A channel region 43 made of a polysilicon film is arranged, and a drain region 31 and a source region 32 made of polysilicon, which are semiconductor films doped with arsenic at a concentration of 1 × 10 ²⁰ / cm ³ , are formed. On the channel region 43 sandwiched between the drain region 31 and the source region 32, for example, a silicon oxide film 2 with a thickness of 5 nm, a non-doped polysilicon film 3 that is a semiconductor film with a thickness of 4 nm, and a silicon nitride with a thickness of 6 nm. A film 4 and a silicon oxide film 5 having a thickness of 5 nm are stacked to form a gate insulating film. On top of that, for example, a control gate 6 made of a polysilicon film with a thickness of 100 nm doped with phosphorus at a concentration of 3 × 10 ²⁰ / cm ³ and a silicon nitride film 28 with a thickness of 100 nm are laminated to form a word line. Is done. Sidewall spacers 52 made of a silicon nitride film having a thickness of 80 nm are disposed on side surfaces of the gate insulating film and the word line which are stacked and extended. A contact plug 34 made of a tungsten film, which is a conductive film, is formed through the insulating film 33 deposited on the word line with a film thickness of 100 nm above the drain region 31. Connected source plugs 53 are formed through. The source plug 53 penetrates the oxide film 43 through a contact hole 53H, and is also electrically connected to a common source line 54 formed to extend thereunder. The source plug 53 is made of a polysilicon film that is a conductive film. The drain region 31 is electrically connected to the corresponding bit line 15 by the drain plug 34 and the connection plug 37 through the contact hole 13 and the connection hole 14.

  Here, the drain plug 34 and the source plug 53 are formed in a self-aligned manner by oxide film etching having a selection ratio with respect to the sidewall spacer 52 and the silicon nitride film 51. For this reason, the opening dimensions of the drain plug 34 and the source plug 53 can be made smaller than the minimum dimension. The 0.13 micron process rule used in this example is not particularly limited, but the word line width is 0.2 μm, the word line space in the drain region is 0.3 μm, and the word line space in the source region is 0.2 μm. Therefore, the length of the unit memory cell in the word line direction is 0.45 μm. Further, since the width of the active region 11 is 0.15 μm and the separation width between the active regions 11 is also 0.15 μm, the length of the unit memory cell in the bit line direction is 0.3 μm. Therefore, the unit memory cell area is 0.45 × 0.3 = 0.135 square μm.

  FIG. 9 illustrates a part of a memory array using the nonvolatile memory cell MC3. In the figure, four nonvolatile memory cells MC3 arranged in a matrix are representatively shown. A pair of nonvolatile memory cells MC3 arranged in the row direction are arranged like a mirror surface, a common drain is electrically connected to the corresponding bit lines BL1 and BL2, and a control gate is a word line WL1 corresponding to each column. It is electrically connected to WL2.

  As illustrated in FIG. 10, in the write operation to the nonvolatile memory cell MC3, when the memory cell connected to the word line WL1 and the bit line BL1 is to be written, the write operation to the drain region 31 is performed via the bit line BL1. A pulse voltage of 8V is applied to the control gate 6 through the word line WL1 with a pulse width of 2 microseconds. The word line WL2 and the bit line BL2 to which the write target memory cell is not connected are set to 0V. As a result, the threshold voltage of the write target memory cell increased from 2V to 4.5V, for example. Further, as illustrated in FIG. 11, in the erase operation, when the memory cell connected to the word line WL1 is to be erased, the potential of the source region 32 of the memory cell MC3 is opened and the bit lines BL1, 4V is applied to the drain region 31 through BL2, and a pulse voltage of −8V is applied to the control gate 6 through the word line WL1 on the erase target side for a pulse width of 10 milliseconds. A pulse voltage of 4V is applied to the word line WL2 on the non-erasing target side. As a result, the threshold voltage of the erase target memory cell MC3 sharing the word line WL1 can be lowered from 4.5V to 2V. As a result of 10,000 rewriting operations under the above-mentioned programming / erasing voltage conditions, the threshold voltage variation after programming and erasing is within 0.2 V, and the memory cell characteristic variation due to rewriting is very small. Was confirmed.

  Next, a method for manufacturing a semiconductor integrated circuit such as a flash memory employing the nonvolatile memory cell MC3 will be schematically described.

  12 to 18 are sectional views showing a method of manufacturing a semiconductor integrated circuit employing the memory cell MC3 in each manufacturing process. Each cross-sectional view illustrates a cross section of a peripheral circuit region and a memory cell region. The memory cell region means a portion of the memory array in which the nonvolatile memory cells MC3 are arranged in a matrix. The peripheral circuit region means a portion of a memory control unit that controls a read operation, an erase / write operation, and the like of stored information with respect to the nonvolatile memory cell MC3 in response to an access instruction.

First, as illustrated in FIG. 12, for example, an oxide film is buried in a groove having a depth of 200 nm in a surface region of a p-type semiconductor substrate 60 having a resistivity of 10 Ωcm, and is planarized by a CMP (Chemical Mechanical Polishing) method. After forming the mold element isolation region 61, for example, phosphorus ions with an acceleration energy of 1 MeV are implanted at an injection amount of 1 × 10 ¹³ / cm ² , phosphorus ions at an acceleration energy of 500 keV are implanted at an implantation amount of 3 × 10 ¹² / cm ² , and phosphorus ions with an acceleration energy of 150 keV. An n-type well region 62 is formed by implanting an implantation amount of 1 × 10 ¹² / cm ² . Then, for example, boron ions with an acceleration energy of 500 keV are implanted at 1 × 10 ¹³ / cm ² , boron ions at an acceleration energy of 150 keV are implanted at 5 × 10 ¹² / cm ² , and boron ions at an acceleration energy of 50 keV are implanted at 1 × 10. ^A p-type well region 63 is formed by implanting ¹² / cm ² . Thereafter, for example, a surface oxide film 64 having a thickness of 10 nm is grown, and phosphorus ions having an acceleration energy of 50 keV are implanted only into the memory cell region by an implantation amount of 2 × 10 ¹⁵ / cm ² to form an n-type common source region 65. Next, an oxide film having a thickness of 100 nm is deposited on the surface oxide film 64 in the memory cell region by a CVD (Chemical Vapor Deposition) method, and a polysilicon film having a thickness of 20 nm is deposited thereon by the CVD method. A laminated film of an oxide film 66 and a first polysilicon film 67 which are processed by using a resist mask which is laminated and patterned by a photolithography method is formed. In this state, the first polysilicon film 67 film on the oxide film 66 is processed in a line and space form.

  Next, as illustrated in FIG. 13, for example, an oxide film 68 having a thickness of 5 nm, a polysilicon film 69 having a thickness of 4 nm, a silicon nitride film 70 having a thickness of 6 nm, and an oxide film 71 having a thickness of 5 nm are formed by CVD. Are stacked and processed using a resist mask patterned by a photolithography method.

Further, as illustrated in FIG. 14, after the surface oxide film 64 is removed in the peripheral circuit region, for example, a first gate oxide film 72 having a thickness of 7 nm and a second gate oxide film 73 having a thickness of 18 nm are grown. Then, a polysilicon film 75 having a film thickness of 100 nm and a silicon nitride film 75 having a film thickness of 100 nm doped with phosphorus having a concentration of 3 × 10 ²⁰ / cm ³ are deposited by CVD, and a resist mask patterned by the photolithography method is formed. Use to process. Then, for example, the n-type halo region 76 to form a phosphorous ions observed acceleration energy 30keV to a low-voltage p-channel transistor in the peripheral circuit region region by implanting of 1 × 10 13 ^/ cm ² injected from the direction of oblique 30 °, An n-type LDD (Lightly Doped Drain) region 77 is formed by implanting phosphorus ions having an acceleration energy of 30 keV only into the peripheral circuit region to be a high-voltage n-channel transistor at an injection amount of 1 × 10 ¹³ / cm ² . Then, for example, arsenic ions having an acceleration energy of 20 keV are implanted only into the memory cell region at a dose of 2 × 10 ¹⁴ / cm ² to form the cell source / drain region 78.

Subsequently, as shown in FIG. 15, after forming a sidewall spacer 79 made of a silicon nitride film having a thickness of 80 nm deposited by, for example, the CVD method and processed by the etch back method, the low-voltage p-channel transistor in the peripheral circuit region and Boron ions having an acceleration energy of 30 keV are implanted only into the region to be implanted to form a p-type source / drain region 80 by implanting 3 × 10 ¹⁵ / cm ^2, and the acceleration energy is applied only to the region that becomes the high-voltage n-channel transistor in the peripheral circuit region An n-type source / drain region 81 is formed by implanting 40 keV arsenic ions at a dose of 2 × 10 ¹⁵ / cm ² . Thereafter, an oxide film having a thickness of 900 nm is deposited by a CVD method, and a planarized oxide film 82 is formed by a CMP method.

Further, as shown in FIG. 16, for example, the oxide film 82, the oxide film 71, the silicon nitride film 70, the polysilicon film 69, the oxide film 68, the polysilicon film 67, the oxide film 66, the sidewall spacer 79 as an etching mask, Then, the surface oxide film 64 is collectively etched to form a source line connection hole, and a polysilicon film doped with phosphorus having a concentration of 4 × 10 ²⁰ / cm ³ is buried by CVD to form a source plug 83.

  Subsequently, FIG. 17 shows a state where a bit line plug 85 made of tungsten is formed after an oxide film 84 having a thickness of 100 nm is deposited by the CVD method.

  Finally, as illustrated in FIG. 18, after depositing an oxide film 85 having a thickness of 100 nm by, for example, CVD, contact holes are formed on the source / drain of the transistor in the peripheral circuit region and on the bit line plug 85. The first metal wiring 86 is patterned. Further, although not shown, in the manufacturing process, the first interlayer insulating film is deposited on the first metal wiring 86, the first connection hole is formed, the second metal wiring is patterned, and the second interlayer insulating film is deposited. Then, the formation of the second connection hole, the patterning of the third metal wiring, the deposition of the passivation film and the opening of the bonding pad part are completed, and the wafer process manufacturing process of the semiconductor integrated circuit such as the flash memory is completed.

  The write operation to the nonvolatile memory cell of the semiconductor integrated circuit manufactured by the above manufacturing process is performed, for example, by applying 5V to the bit line plug 85 and applying a pulse voltage of 8V to the control gate 74 with a pulse width of 1 microsecond, As a result, the threshold voltage of the write target memory cell increased from 2V to 4V. The erase operation is performed by applying 4V to the bit line plug 85 and −8V pulse voltage to the control gate 74 with a pulse width of 50 milliseconds with the source region potential open. The threshold voltage of the memory cell could be reduced from 4V to 2V. As a result of performing the rewrite operation 100,000 times under the above-described program / erase voltage conditions, the threshold voltage variation after programming and erasing was within 0.4V. Changes in memory cell characteristics due to rewriting can be suppressed by a 1.2-fold increase in write time, a 3-fold increase in erase time, and a 0.8-fold decrease in read current, confirming the effectiveness of the present invention. It was done.

<< Another form of memory cell structure >>
FIG. 19 illustrates another form of the memory cell structure corresponding to the DD ′ section of FIG. In the memory cell MC3 described in FIGS. 6 to 8, the polysilicon film 3 extends in the word line direction, and is integrally formed between the memory cells sharing the word line. As another form of the memory cell structure, for example, as illustrated in FIG. 19 corresponding to the section DD ′ in FIG. 8, the polysilicon film 3 may be divided into memory cells. The polysilicon film 3 shown in the figure can be formed using a mask for processing the bit line 38 before the silicon nitride film 4 serving as a charge trapping region is deposited by the CVD method. In this example, the unit memory cell area is 0.45 × 0.3 = 0.135 square μm, similarly to the memory cell MC3. In this memory cell structure, for example, electrons trapped at the interface between the polysilicon film 3 and the silicon nitride film 4 are undesirably detrapped separately from the erase operation to move the polysilicon film 3 and move to other memory cells. This structure is effective when there is a possibility of affecting the threshold voltage.

  The write operation to the nonvolatile memory cell having the structure of FIG. 19 was performed by applying 4 V to the drain region and applying a pulse voltage of 8 V to the control gate with a pulse width of 2 microseconds, and the threshold voltage increased from 2 V to 4.5 V. . In addition, the erase operation is performed by applying a pulse voltage of 4 V to the drain region and a pulse voltage of −7 V to the control gate with a pulse width of 100 milliseconds while the potential of the source region is open, and the threshold voltage is 4.5 V to 2 V. Could be reduced. As a result of 10,000 times of rewriting operation under the above-mentioned programming / erasing voltage conditions, the threshold voltage variation after programming and erasing is within 0.3V, and the memory cell characteristic variation due to rewriting is very small. confirmed.

  FIG. 20 illustrates still another form of the memory cell structure corresponding to the D-D ′ cross section of FIG. 8. The memory cell MC3 described with reference to FIGS. 6 to 8 employs the polysilicon film 3 as a semiconductor film. As another form of the memory cell structure, for example, as illustrated in FIG. 20 corresponding to the DD ′ cross section of FIG. 8, non-doped polysilicon grains 88 having a diameter of about 10 nm are discretely arranged in the insulating film. Adopted semiconductor film. In this example, the unit memory cell area is 0.45 × 0.3 = 0.135 square μm, similarly to the memory cell MC3.

  For example, the write operation to the nonvolatile memory cell having the structure shown in FIG. 20 is performed by applying a pulse voltage of 5 V to the drain region and a pulse voltage of 8 V to the control gate with a pulse width of 2 microseconds. Raised to 5V. In addition, for example, the erase operation is performed by applying a pulse voltage of 6 V to the drain region and a pulse voltage of −8 V to the control gate with a pulse width of 50 milliseconds while the potential of the source region is open. The voltage could be lowered from 4.5V to 2V. As a result of 10,000 times of rewriting operation under the above-mentioned programming / erasing voltage conditions, the threshold voltage variation after programming and erasing is within 0.3V, and the memory cell characteristic variation due to rewriting is very small. confirmed.

In the above description, the silicon nitride film 4 is used as the insulating film as the charge trapping film. Instead of the silicon nitride film, a metal oxide film may be employed as the charge trapping film. As the metal oxide film, for example, a tantalum pentoxide film (Ta ₂ O ₅ ) having a thickness of 20 nm can be employed. For example, the non-volatile memory cell may be configured by changing the silicon nitride film 4 to a tantalum pentoxide film having a thickness of 20 nm in the cross-sectional structure of FIG. Under the write conditions in which a pulse voltage of 5 V is applied to the drain region of this nonvolatile memory cell and a pulse voltage of 8 V is applied to the control gate, the threshold voltage rose from 2 V to 5 V. As an alternative to the tantalum pentoxide film, an appropriate film corresponding to each dielectric constant can be used even when a metal oxide having a high dielectric constant typified by an alumina film (Al ₂ O ₃ ) or a titanium oxide film (TiO ₂ ) is used. If the thickness is set, it can be used for the nonvolatile memory cell of the present invention.

  FIG. 21 illustrates a device structure of a nonvolatile memory cell using a silicon nitride film that is relatively silicon-rich near the channel region in a vertical section. In the description so far, the nonvolatile memory element uses the interface state between a semiconductor film such as a polysilicon film and a high dielectric film such as a silicon nitride film. In the memory cell MC4 of FIG. 21, a silicon nitride film 90 is provided on the silicon oxide film 2 as the first insulating film on the channel region 9, and a portion 90A of the silicon nitride film 90 near the silicon oxide film 2 is silicon-rich. It was set as the composition. Specifically, the nonvolatile memory cell MC4 has a source region 8, a drain region 7 and a channel region 9 between the source region 8 and the drain region 7 respectively formed in the semiconductor region 1, and this channel region. A gate insulating film 10 A is formed on the substrate 9. The gate insulating film 10A includes a silicon oxide film 2 as a first insulating film provided on the channel region 9, a silicon nitride film 90 as a second insulating film provided on the silicon oxide film 2, The silicon oxide film 5 is provided on the silicon nitride film 90 as a third insulating film. A gate electrode 6 is provided on the silicon oxide film 5. The silicon nitride film 90 is a silicon nitride film in which the Si / N value is larger in the portion 90A closer to the silicon oxide film 90A than in the portion 90B closer to the silicon oxide film 5. The trap density of the silicon nitride film 90 is higher than the trap density of the silicon oxide films 2 and 5. The electrons trapped in the trap are tunneled to the channel region 9 or the drain region 7 through the silicon oxide film 2.

  The silicon-rich portion 90A of the silicon nitride film is a region having a relatively large number of traps such as lattice defects and dangling bonds, and in this respect, the polysilicon film 3 and the silicon nitride in the memory cells MC1 to MC3. It can be positioned as an alternative to the trap function at the interface with the film 4, and basically has the same function and effect.

《Nonvolatile memory》
FIG. 22 illustrates a flash memory as an electrically erasable and writable nonvolatile memory employing the nonvolatile memory cell represented by MC3.

  The flash memory 99 shown in the figure performs a read operation, an erase operation, and a write operation on the memory array 100 in which the nonvolatile memory cells MC3 are arranged in a matrix and the nonvolatile memory cell MC3 in response to an external access instruction. And a memory control circuit for controlling. In this example, all circuit parts other than the memory array 100 are positioned as memory control circuits.

  The memory array 100 includes a memory mat, a data latch circuit, and a sense latch circuit. This memory mat has a large number of electrically erasable and writable nonvolatile memory cells represented by the memory cell MC3. In the nonvolatile memory cell, the control gate is connected to the corresponding word line 101, the drain is connected to the corresponding bit line 102, and the source is connected to a source line (not shown). The nonvolatile memory cell stores information corresponding to the level of the threshold voltage with respect to the word line voltage (control gate applied voltage) for reading data. Although not particularly limited, in this specification, a state in which the threshold voltage of the memory cell transistor is low is referred to as an erased state, and a state in which the threshold voltage is high is referred to as a written state. Since the definitions of writing and erasing are relative concepts, they can be defined in reverse to the above.

  The external input / output terminals I / O0 to I / O7 of the flash memory 99 are also used as address input terminals, data input terminals, data output terminals, and command input terminals. X address signals input from the external input / output terminals I / O 0 to I / O 7 are supplied to the X address buffer 105 via the multiplexer 104. The X address decoder 106 decodes the internal complementary address signal output from the X address buffer 105 and drives the word line 101.

  A sense latch circuit is provided at one end of the bit line 102, and a data latch circuit is provided at the other end. The bit line 102 is selected by the Y switch array 108 based on the selection signal output from the Y address decoder 107. The Y address signal inputted from the external input / output terminals I / O0 to I / O7 is preset in the Y address counter 109, and the address signal sequentially incremented from the preset value is given to the Y address decoder 107.

  The bit line selected by the Y switch array 108 is conducted to the input terminal of the output buffer 110 during the data output operation, and is conducted to the output terminal of the data control circuit 112 via the input buffer 111 during the data input operation. The connection between the output buffer 110 and the input buffer 111 and the input / output terminals I / O 0 to 7 is controlled by the multiplexer 104. Commands supplied from the input / output terminals I / O 0 to I / O 7 are supplied to the mode control circuit 113 via the multiplexer 104 and the input buffer 111.

  The control signal buffer circuit 115 inputs a chip enable signal / CE, an output enable signal / OE, a write enable signal / WE, a serial clock signal SC, a reset signal / RES, and a command enable signal / CDE as access control signals. The symbol / immediately before the signal name means that the signal is low enable. The mode control circuit 113 controls a signal interface function with the outside via the multiplexer 104 according to the state of these signals. Command inputs from the input / output terminals I / O0 to I / O7 are synchronized with the command enable / CDE. Data input is synchronized to the serial clock SC. Address information input is synchronized with the write enable signal / WE. When the command code instructs the start of the erase or write operation, the mode control unit 113 asserts and outputs the ready / busy signal R / B indicating that the erase or write operation is in progress to the outside.

  An internal power supply circuit (internal voltage generation circuit) 116 generates an operation power supply 117 having various internal voltages for writing, erasing, verifying, reading, etc., and supplies it to the X address decoder 106, the memory cell array 100, and the like. .

  The mode control circuit 113 controls the flash memory as a whole according to the input command. The operation of the flash memory 99 is basically determined by commands. The commands of the flash memory 99 include commands such as read, erase, and write. For example, the read command includes a read command code, a read X address, and a necessary Y address. The write command includes a write command code, an X address, a necessary Y address, and write data.

  The flash memory 99 has a status register 118 for indicating its internal state, and its contents can be read from the input / output terminals I / O0 to I / O7 by asserting the signal / OE.

  Since the flash memory 99 employs a nonvolatile memory cell represented by MC3, the characteristic deterioration does not proceed remarkably even after a large number of rewrites, and high reliability of data retention can be realized even after long-term use. In addition, it is possible to reduce the chip occupation area with respect to the storage capacity.

<Computer system>
FIG. 23 illustrates a computer system using the flash memory. The computer system shown in the figure includes a host CPU 121, an input / output device 122, a RAM 123, and a memory card 124 that are connected to each other via a system bus 120.

  Although the memory card 124 is not particularly limited, a system bus interface circuit 125, a memory controller 126, and a plurality of flash memories 99 are mounted on a card substrate.

  The system bus interface circuit 125 is not particularly limited, but enables a standard bus interface such as an ATA (AT Attachment) system bus. The memory controller 126 connected to the system bus interface circuit 125 receives access commands and data from the host system of the host CPU 121 and the input / output device 122 connected to the system bus 120.

  For example, when the access command is a read command, the memory controller 126 accesses one or more necessary flash memories 99 and transfers read data to the host CPU 121 or host system. When the access command is a write command, the memory controller 126 accesses one or more necessary flash memories 99 and stores write data from the host CPU 121 or the host system therein. This storage operation includes a write operation and a write verify operation to a necessary block, sector or memory cell of the flash memory. When the access command is an erase command, the memory controller 126 accesses one or more necessary flash memories 99 and erases data stored therein. This erase operation includes an erase operation and an erase verify operation for a necessary block, sector or memory cell of the flash memory 99.

  Data stored for a long period of time is stored in this non-volatile storage device, while data that is processed and frequently changed by the host CPU 121 is stored and used in the RAM 123 as a volatile memory.

  Although the memory card 124 is not particularly limited, it is used for compatibility with a hard disk storage device, and a large capacity storage of several tens of gigabytes is realized by a large number of flash memories 99. Employing the flash memory 99, advantages derived from the characteristics of nonvolatile memory cells represented by MC3, such as high integration density, low power consumption, high-speed writing, high-speed reading speed, and highly reliable storage information retention characteristics It has sex.

  The memory card 124 is not limited to a memory card having a relatively small thickness. Even when the memory card 124 is relatively thick, it analyzes the interface with the host bus system and the command of the host system and flashes the nonvolatile memory card. Needless to say, the present invention can be realized as any nonvolatile storage device including an intelligent controller capable of controlling the nonvolatile memory.

  Although the invention made by the present inventor has been specifically described in various forms, it is needless to say that the present invention is not limited thereto and can be appropriately changed without departing from the gist thereof.

  For example, in the above description, the case where a nonvolatile memory cell has a binary threshold voltage in order to store one bit of digital data in one memory cell has been described. Since the present invention uses a charge trapping insulating film such as a silicon nitride film for storing stored information, the present invention is not limited to this, and a memory for storing multiple bits of digital data in one nonvolatile memory cell. The cell may be controlled so as to have a four-value threshold voltage or more. For example, in order to set a quaternary threshold voltage, hot electron injection writing may be performed by switching the source and drain. If the read operation is performed by switching the source and drain accordingly, each stored information can be read separately.

  In addition, the film components, film thicknesses, film manufacturing methods, etc. in the device structures described above can be changed as appropriate.

  The semiconductor integrated circuit to which the nonvolatile memory cell according to the present invention is applied is not limited to the flash memory LSI. For example, such a flash memory may be realized as a data processor such as a microcomputer provided on-chip for storing data or programs.

1 is a longitudinal sectional view illustrating a first basic memory cell structure having a semiconductor film and a nitride film. FIG. 2 is a plan view illustrating a detailed structure of the nonvolatile memory cell in FIG. 1. It is A-A 'sectional drawing in FIG. FIG. 3 is a B-B ′ sectional view in FIG. 2. It is a longitudinal cross-sectional view which illustrates the 2nd basic memory cell structure which has a semiconductor film and a nitride film. It is a top view which illustrates the 3rd basic memory cell structure which has a semiconductor film and a nitride film. FIG. 7 is a C-C ′ sectional view in FIG. 6. It is D-D 'sectional drawing in FIG. FIG. 6 is a circuit diagram illustrating a part of a memory array using nonvolatile memory cells having a third basic memory cell structure. FIG. 10 is a circuit diagram illustrating a voltage application state in a write operation of a nonvolatile memory cell in the circuit of FIG. 9. FIG. 10 is a circuit diagram illustrating a voltage application state of an erase operation of a nonvolatile memory cell in the circuit of FIG. 9. It is a principal part longitudinal cross-sectional view of the non-volatile memory cell in the first manufacturing process of the manufacturing method of the semiconductor integrated circuit which employ | adopted the non-volatile memory cell which has a 3rd basic memory cell structure. FIG. 13 is a longitudinal sectional view of main parts of a nonvolatile memory cell during a manufacturing process following FIG. 12. FIG. 14 is a longitudinal sectional view of main parts of a nonvolatile memory cell during a manufacturing process following FIG. 13; FIG. 15 is a longitudinal sectional view of main parts of a nonvolatile memory cell during a manufacturing process following FIG. 14; FIG. 16 is a fragmentary longitudinal cross-sectional view of the nonvolatile memory cell during a manufacturing step following that of FIG. 15; FIG. 17 is a longitudinal sectional view of main parts of a nonvolatile memory cell during the manufacturing process following FIG. 16. FIG. 18 is a longitudinal sectional view of main parts of a nonvolatile memory cell during a manufacturing process following FIG. 17; FIG. 9 is a longitudinal sectional view illustrating a memory cell structure in which a polysilicon film is divided into memory cell units as another form of the memory cell structure corresponding to the D-D ′ section of FIG. 8. FIG. 9 is a longitudinal sectional view illustrating a memory cell structure that employs a semiconductor film in which polysilicon grains are discretely arranged in an insulating film as yet another form of the memory cell structure corresponding to the D-D ′ section of FIG. 8. It is a longitudinal cross-sectional view illustrating a device structure of a nonvolatile memory cell using a silicon nitride film relatively silicon-rich near the channel region. 1 is a block diagram illustrating a flash memory as an electrically erasable and writable nonvolatile memory employing nonvolatile memory cells according to the present invention. 1 is a block diagram illustrating a computer system using a flash memory. It is explanatory drawing which illustrates the device structure of the conventional non-volatile memory element which has a gate oxide film of ONO structure. It is explanatory drawing which illustrates the multi-value storage technique using the conventional non-volatile memory element which has a gate oxide film of ONO structure. It is explanatory drawing which illustrates typically the problem which this inventor discovered regarding the conventional non-volatile memory element which has a gate oxide film of ONO structure.

Explanation of symbols

MC1, MC2, MC3 Nonvolatile memory cell 1 Semiconductor region 2 Silicon oxide film 3 Polysilicon film 4 Silicon nitride film 5 Silicon oxide film 6 Gate electrode 7 Drain region 8 Source region 9 Channel region 10, 10A Gate insulating film 11 Active region 15 Bit line 34 Drain plug 41 Semiconductor substrate 42 Silicon oxide film 43 Channel region 52 Side wall spacer 53 Source plug 88 Polysilicon grain 90 Partially silicon-rich silicon nitride film 90A Silicon-rich part 99 Flash memory 100 Memory array

Claims (10)

A source region, a drain region formed in the semiconductor region, and a channel region therebetween, a first insulating film provided on the channel region, and a semiconductor film provided on the first insulating film; A second insulating film provided on the semiconductor film, and a gate electrode provided on the second insulating film,
The second insulating film is a charge trapping film;
Charge accumulation is performed by trapping charges in the trap of the second insulating film,
The nonvolatile memory element, wherein the silicon film is a film in which silicon particles are dispersed. A source region, a drain region formed in the semiconductor region, and a channel region therebetween, a first insulating film provided on the channel region, and a semiconductor film provided on the first insulating film; A second insulating film provided on the semiconductor film, and a gate electrode provided on the second insulating film,
The second insulating film is a charge trapping film;
Charge accumulation is performed by trapping charges in the trap of the second insulating film,
The non-volatile memory element, wherein the silicon film is a film in which silicon particles are dispersed in an insulating film.   3. The nonvolatile memory element according to claim 1, wherein the thickness of the semiconductor film is smaller than that of the second insulating film. A non-volatile memory element that uses a charge trapping film for charge retention,
A source region, a drain region, and a channel region between them are formed in the semiconductor region,
A first insulating film is provided on the channel region;
A second insulating film which is the charge trapping film is provided on the first insulating film;
A non-volatile memory element, wherein a gate electrode is provided on the second insulating film, and silicon particles are dispersed between the first insulating film and the second insulating film. A non-volatile memory element that uses a charge trapping film for charge retention,
A source region, a drain region, and a channel region between them are formed in the semiconductor region,
A first insulating film is provided on the channel region;
Silicon particles are dispersed on the first insulating film,
A second insulating film which is the charge trapping film is provided on the dispersed silicon particles;
A non-volatile memory element, wherein a gate electrode is provided on the second insulating film.   6. The nonvolatile memory element according to claim 4, wherein the film thickness of the dispersed silicon particles is thinner than the film thickness of the second insulating film.   8. The nonvolatile memory element according to claim 1, wherein the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film. 9.   The non-volatile memory element according to claim 1, wherein a third insulating film is provided between the second insulating film and the gate electrode.   3. The nonvolatile memory element according to claim 1, wherein the charges trapped in the charge trapping film are tunneled through the first insulating film. 6. The nonvolatile memory element according to claim 4, wherein charges trapped in the charge trapping film are tunneled through the first insulating film.

Images